A6850 Dual Channel Switch Interface IC Features and Benefits ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ Description 4.75 to 26.5 V operation Low VIN-to-VOUT voltage drop 1/ current sense feedback 10 Survive short-to-battery and short-to-ground faults Survive 40 V load dump >4 kV ESD rating on the output pins, >2 kV on all other pins Output current limiting Low operating and Sleep mode currents Integrates with Allegro A114x and A118x Hall effect two-wire sensors The Allegro® A6850 is designed to interface between a microprocessor and a pair of 2-wire Hall effect sensors. The A6850 uses protected high-side low resistance DMOS MOSFETs to switch the supply voltage to the two Hall effect devices. Each switch can be controlled independently via individual ENABLE pins and both switches are protected with current-limiting circuitry. The output switches are rated to operate to 26.5 V and will source at least 25 mA per channel before current limiting. Typical two-wire Hall sensor applications require the user to measure the supply current to determine whether the Hall sensor is switched on (magnetic field present) or switched off (no magnetic field present). This is usually accomplished by using an external series shunt resistor and protection circuits for the microprocessor. In many systems, the sensed voltage is used as the input to a microprocessor analog-to-digital (A-to-D) input. This provides the system with an indication of the status of the two-wire switch as well as provides the capability for diagnostic information if there is an open or shorted sensor. Package: 8 pin SOIC (suffix L) Approximate Scale 1:1 Continued on the next page… Functional Block Diagram VIN ENABLE1 Control Block ENABLE2 SENSE1 × IOUTPUT1 1/ 10 Fault Detection OUTPUT1 Fault Detection OUTPUT2 SENSE2 × IOUTPUT2 1/ 10 GROUND 6850-DS Dual Channel Switch Interface IC A6850 Description (continued) The A6850 eliminates the need for the external series shunt resistor is available (<15 µA) by driving both ENABLE pins low. Also, the A6850 can be used to interface to mechanical switches. in Hall sensor applications by incorporating an integrated current mirror which reports the Hall sensor supply current as a 1/10 value The A6850 is supplied in an 8-pin Pb (lead) free SOIC package, with 100% matte tin leadframe plating. on the SENSE1 or SENSE2 output pin. A low current Sleep mode Selection Guide Part Number Packing A6850KLTR-T 13-in. reel, 3000 pieces/reel A6850KL-T Tube, 98 pieces/tube Absolute Maximum Ratings Characteristic Symbol Notes Rating Units Supply Voltage VIN 40 V Output Voltage VOUTPUTx –0.3 to 40 V SENSEx Voltage Range VSENSEx –0.3 to 7 V ENABLEx Voltage Range VENABLEx –0.3 to 7 V –40 to 125 ºC Operating Ambient Temperature TA Maximum Junction Temperature TJ(max) 150 ºC Tstg –55 to 150 ºC AEC-Q100-002; OUTPUT1 and OUTPUT2 4.5 kV AEC-Q100-002; all other pins 2.5 kV 1050 V Storage Temperature Range K ESD Rating - Human Body Model HBM ESD Rating - Charged Device Model CDM Pin-out Diagram ENABLE1 1 Control Terminal List Table 8 OUTPUT1 Switch SENSE1 2 7 GROUND ENABLE2 3 6 OUTPUT2 Switch SENSE2 4 AEC-Q100-011; all pins 5 VIN Name Number Description ENABLE1 1 Digital input pulled to ground SENSE1 2 Sensed current output ENABLE2 3 Digital input pulled to ground SENSE2 4 Sensed current output VIN 5 Chip power supply voltage OUTPUT2 6 Switchable voltage supply to sensor GROUND 7 Ground reference OUTPUT1 8 Switchable voltage supply to sensor Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Dual Channel Switch Interface IC A6850 ELECTRICAL CHARACTERISTICS at TJ = -40 to +150°C (unless noted otherwise) Characteristics Symbol Test Conditions Supply Input Voltage Range VIN Operating mode, IOUTPUTx = 0 mA Sleep mode: Supply Input Quiescent Current IINQ ENABLE1 and ENABLE2 low VOUTPUT1 = VOUTPUT2 = 0 V Power-Up Time1 tON OUTPUTx Source Resistance RDS(on) IOUTPUTx = 20 mA OUTPUTx Leakage Current IOUTPUTQ VOUTPUTx = 0 V; disabled ISENSEx = (IOUTPUTx / 10) + ISENSE(ofs) ISENSE(ofs), IOUTPUT = 2 mA to 20 mA SENSEx Output Current Offset2 ISENSEQ VSENSEx = 0 V; disabled VIN > 7 V SENSEx Voltage3 VSENSEx VIN < 7 V VENABLEH ENABLEx Input Voltage Range VENABLEL ENABLEx Input Hysteresis VENABLEhys At least one output enabled ENABLEx = 2.0 V ENABLEx Current IENABLE ENABLEx = 0.4 V OUTPUT Current Limit IOUTPUTM Reverse bias blocking: VIN = 4.75 V, OUTPUT Reverse Bias Current IOUTPUT(rvrs) VOUTPUT = 26.5 V Overvoltage Protection Threshold VOVP Rising VIN Overvoltage Protection Hysteresis VOVPhys Thermal Shutdown Threshold TTSD Temperature Increasing Thermal Shutdown Hysteresis TTSDhys Min. 4.75 – Typ. – – Max. 26.5 5.0 Units V mA – – 15 µA – – – – – – 20 35 20 µs Ω µA –100 – 100 µA – 0 0 2.0 – 150 – – 25.0 – – – – – – 40 8.0 35.0 10 6 VIN – 1 – 0.4 350 100 20 45.0 µA V V V V mV µA µA mA – 500 750 µA 27.0 – – – – 2.0 175 15 33.0 – – – V V °C °C 1Delay from end of Sleep mode to outputs enabled. input and output current specifications, negative current is defined as coming out of (sourced from) the specified device pin. 3User to ensure that V SENSEx remains within the specified range. If VSENSEx exceeds the maximum value, the device is self-protected by an internal clamp, but not all parameters perform as specified. 2For THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information Characteristic Package Thermal Resistance Symbol RθJA Value Units 4-layer PCB based on JEDEC standard Test Conditions* 80 ºC/W 1-layer PCB with copper limited to solder pads 140 ºC/W *Additional thermal data available on the Allegro Web site. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Dual Channel Switch Interface IC A6850 Functional Description Example: Calculating the power dissipation and temperature rise, given: Thermal Shutdown (TSD) The A6850 protects itself from excessive heat damage by disabling both outputs when the junction temperature, TJ , rises above the TSD threshold (TTSD). The outputs will remain off until the junction temperature falls below the TTSD level minus the TSD hysteresis, TTSDhys. TJ can be estimated by calculating the power dissipation (PD) of the A6850. To calculate PD: PD = VIN IINQ – VOUTPUT1 IOUTPUT1 – VOUTPUT2 IOUTPUT2 – VSENSE1 ISENSE1 – VSENSE2 ISENSE2 . (1) TA = 25°C, VIN = 5 V, IINQ = 5 mA, IOUTPUT1 = IOUTPUT2 = 15 mA, VDropx = VIN – VOUTPUTx = 0.7 V, ISENSEx = IOUTPUTx /10 = 1.5 mA, and RSENSE1 = RSENSE2 = 2 kΩ. Then: PD = 5 V × 5 mA + 0.7 V×15 mA+[5 V – (1.5 mA×2 kΩ)]×1.5 mA + 0.7 V×15 mA+[5 V – (1.5 mA×2 kΩ)]×1.5 mA = 52 mW . PD = VIN IINQ + (VIN – VOUTPUT1 ) IOUTPUT1 + (VIN – VOUTPUT2 ) IOUTPUT2 Substituting in equation 3: + (VIN – VSENSE1 ) ISENSE1 + (VIN – VSENSE2 ) ISENSE2 . Substituting in equation 4: (2) The temperature rise of the A6850 can be calculated by multiplying PD and the thermal resistance from junction to ambient, RθJA . The formula for temperature rise, ΔT, is: ΔT = PD × RθJA . (3) The RθJA for an 8-pin SOIC (Allegro L package) on a onelayer board with minimum copper area is 140°C / W. (More thermal data is available on the Allegro MicroSystems Web site.) The total junction temperature can be calculated by: TJ = TA + ΔT , where TA is the ambient air temperature. (4) ΔT = 52 mW × 140°C / W = 7.3°C . TJ = 25°C + 7.3°C = 32.3°C . Output Current Limit The A6850 limits the output current to a maximum current of IOUTPUTM. The output current will remain at the current limit until the output load is reduced or the A6850 goes into thermal shutdown. The high output current limit allows the bypass capacitor, CBYP , on the Hall sensor to charge up quickly. This allows a high slew rate on the VCC pin of the Hall sensor, ensuring that the sensor Power-On State will be correct. See the Applications Information section for schematic diagrams and power calculations. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Dual Channel Switch Interface IC A6850 Output Faults limits on the sense pin (see Electrical Characteristics table). The A6850 withstands short-to-ground or short-to-battery of the OUTPUTx pins. In the case of short-to-ground, current is held to the current limit (IOUTPUTM). Sleep Mode If VOUTPUTx > (VIN + 0.7 V) during short-to-battery, the A6850 monitors VOUTPUTx and disables the outputs. Because the protection circuitry requires a finite amount of time to disable the outputs, a bypass capacitor of 1 µF is necessary on VIN. Although OUTPUTx sinks current into the A6850 in this state, the current is bled to ground and does not chargeup capacitors tied to VIN. Overvoltage Protection The A6850 has built-in overvoltage protection against a load dump on the supply bus. In the case of a load dump, or when VIN is connected to the battery supply bus and VIN rises above the overvoltage threshold, VOVP , the A6850 will shut off the outputs. Low-leakage or sleep modes are required in automotive applications to minimize battery drain when the vehicle is parked. The A6850 enters sleep mode when both ENABLE pins are low. In sleep mode, the internal regulators and all other internal circuitry are disabled. When enabling an output, the part must first come out of sleep mode. Consequently, the wake-up time amounts to a propagation delay before the outputs turn on. Also, the ENABLE pins do not switch with hysteresis until the regulators stabilize. After the internal regulators stabilize, internal circuitry is enabled and the outputs turn on, as shown in figure 1. As long as one ENABLE pin is held high, the A6850 operates with hysteresis. SENSE Pin Outputs The A6850 divides the OUTPUTx pin current by 10 and mirrors it onto the corresponding SENSEx pin. Putting sense resistors, RSENSE , from these pins to ground will create a voltage that can be read by an ADC (analog-to-digital converter). The value of RSENSE should be chosen so that the voltage drop across the sense resistor (VRSENSE) does not exceed the maximum voltage rating of the ADC. For further protection of the ADC, an external clamping circuit, such as a Zener diode, can be used to clamp any transient current spikes that may occur on the output that would be translated onto the SENSE pins. The sense current is one tenth of the output current, plus an offset current. This offset current is consistent across the whole range of the output current. The sense current can be calculated by the following formula: ISENSEx = (IOUTPUTx / 10) + ISENSE(ofs) . (5) The sense resistor must also be chosen to meet the voltage ENABLE VENABLEL > tON RegOk VREG OUTPUT Figure 1. Activation Timing Diagram. Exiting Sleep mode via ENABLE signal to output waveform. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Dual Channel Switch Interface IC A6850 Applications Information Two-Wire Sensor Interfacing The following table describes some of the possible output When voltage is applied to two-wire Hall effect sensors, current flows within one of two narrow ranges. Any current conditions that can be monitored through the SENSE pins. level not within these ranges indicates a fault condition. Hall effect sensors. Figure 2 is a typical application using the A6850 with dual Signal and Fault Table Output Pin Current (mA) Sense Pin Current (mA) Sense Pin Voltage, Rsense= 1.5 kΩ (V) OUTPUT Pin Short-to-Ground 25 to 45 2.5 to 4.5 3.75 to 6.75 Logic High from Hall Sensor 12 to 17 1.2 to 1.7 1.8 to 2.55 Condition Short-to-Battery 0.0 0.0 0 2 to 6.9 0.2 to 0.69 0.3 to 1.04 Thermal Shutdown 0.0 0.0 0 OUTPUT Pin Open 0.0 0.0 0 Logic Low from Hall Sensor* *This current range includes all A114x and A118x sensors. VCC or VBAT VCC VIN Digital Output Digital Output 1 µF 1 ENABLE1 3 ENABLE2 5 VIN OUTPUT1 8 CBYP 0.01 µF A6850 Controller ADC ADC 2 SENSE1 4 SENSE2 Wiring Harness OUTPUT2 6 A114x or A118x GROUND RSENSE1 1.5 kΩ RSENSE2 1.5 kΩ CBYP 0.01 µF 7 A114x or A118x Figure 2. Typical Application with 2-Wire Hall Effect Sensors Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Dual Channel Switch Interface IC A6850 Mechanical Switch Interfacing A series resistor included in the circuit reduces power dis- The A6850 can be used as an interface between mechanical switches, set in a switch-to-ground configuration, and a low voltage microprocessor. A series resistor must be placed in the circuit to limit current when the mechanical switch is closed, in order to prevent excessive power dissipation in the A6850. sipation in the A6850. The voltage drop across the resistor For example, to calculate the power dissipation in the A6850 driving two mechanical switches with 1 kΩ series resistors, with VIN = 12 V, assume that the current limit for each of the outputs is set to the maximum value, IOUTPUTM (max) = 45 mA. When the mechanical switch is closed without a series resistor, the A6850 will be at the current limit. The full 12 V of the power supply will drop across the A6850 at 45mA The power dissipation for one mechanical switch closed would be: PD1 = VDrop1 × IOUTPUT1 = 12 V × 45 mA = 540 mW . (6) VCC or VBAT VCC VIN Digital Output Digital Output would be: VRSERIES = VIN – VDrop1 = 12 V – 0.7 V = 11.3 V . (7) The current is then limited to: IOUTPUT1 = VRSERIES / RSERIES = 11.3 V / 1 kΩ = 11.3 mA . (8) Power dissipation in the A6850 from this switch is much lower: PD1 = VDrop1 × IOUTPUT1 = 0.7 V × 11.3 mA = 7.91 mW . 1 µF 1 ENABLE1 3 ENABLE2 5 VIN OUTPUT1 8 (9) Wiring Harness RSERIES A6850 Controller Input1 Input2 2 SENSE1 4 SENSE2 OUTPUT2 GROUND RSENSE1 RSENSE2 6 RSERIES 7 Figure 3. Typical Application with Mechanical Switches Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Dual Channel Switch Interface IC A6850 Ganging SENSE1 and SENSE2 and ENABLE2 may be activated simultaneously, with the In certain applications both outputs may be read with a single ADC channel. The OUTPUTx loads are enabled by alternatively activating ENABLEx. In fact, both ENABLE1 SENSE1 and SENSE2 currents added together. For valid Vin Digital Output Digital Output VSENSEx remain within specification. 0.47µF Enable 1 Enable 2 Controller Vin Output 1 LOAD1 Vcc or Vbat Vcc measurements the load resistor need only be selected so that A6850 Sense 1 Sense 2 ADC Output 2 LOAD2 R VENABLE1 VENABLE2 IOUTPUT1 ILOAD1 ILOAD2 IOUTPUT2 VADC ILOAD1 R*ILOAD1/10 ILOAD2 R*ILOAD2/10 R*(ILOAD1/10 + ILOAD2/10) Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Dual Channel Switch Interface IC A6850 L Package, 8-Pin SOIC 6.20 .244 5.80 .228 0.25 [.010] M B M 5.00 .197 4.80 .189 8º 0º A B 8 0.25 .010 0.17 .007 Preliminary dimensions, for reference only Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only (reference JEDEC MS-012 AA) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 4.00 .157 3.80 .150 1.27 .050 0.40 .016 A A Terminal #1 mark area B Reference pad layout (reference IPC SOIC127P600-8M); adjust as necessary to meet application process requirements 1 2 0.25 .010 8X SEATING PLANE 0.10 [.004] C 8X 0.51 .020 0.31 .012 C SEATING PLANE GAUGE PLANE 1.75 .069 1.35 .053 0.25 [.010] M C A B 0.25 .010 0.10 .004 1.27 .050 2.50 .098 REF B 0.65 .026 MAX 4.90 .193 REF 1.27 .050 REF The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright©2006 AllegroMicroSystems, Inc. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com