ORINOCO Product Brief STS-12/STM-4 DS3/E3/STS-1E SONET/SDH Mapper Features Part Number S1204CBI21, Revision 1.5, Dec. 2002 The ORINOCO is a highly integrated chip that implements SONET/SDH processing and DS3/E3/STS-1E mapping functions for an STS-12/STM-4 or STS-3/STM-1 data stream. The ORINOCO is compliant with the following standards: Bellcore GR253, GR-499 and GR-820; ANSI T1.105 and T1.107; and ITU G.751-2; G.775, G.783, G.804, G.823-5, and G.832. • Processes any valid combination of SONET/SDH STS-1/AU-3 or TUG-3/AU-4 tributaries in STS-12/STM-4 or STS-3/STM-1. • Terminates/generates SONET/SDH section, line, and path OH • Provides on the SONET/SDH side a serial 622 MHz or a 77.76 MHz 8-bit interface for STS-12/STM-4 applications; or a serial 155.52 MHz interface for STS-3/STM-1 applications. The ORINOCO supports full-duplex processing of SONET/SDH data streams with section, line, & path overhead processing. The device supports framing, scrambling/descrambling, alarm signal insertion/detection, and bit interleaved parity (B1/B2/B3) processing. Serial interfaces for E1, E2, F1 and Line and Section DCC are also provided. • Supports flexible assignment of STS-1E and DS3 or STS-1E and E3 mappings on a per tributary basis. • Provides STS-1E mapping/demapping for up to 12 STS-1s. • Provides DS3 or E3 mapping/demapping for up to 12 tributaries, through SONET STS1, SDH AU-3, and/or TUG-3/AU-4 containers. A general purpose microprocessor interface is provided for device initialization, control, and monitoring. This interface can operate either as an 8-bit asynchronous interface, or a 16-bit synchronous interface. The interface supports both Intel and Motorola type microprocessors, and is capable of operating in either an interrupt driven or polled-mode configuration. • Supports mixed M23 and C-bit parity DS3 frame formats on a pertributary basis. • Supports mixed G.751 and G.832 E3 frame formats on a pertributary basis. • Supports full-featured DS3/E3/STS-1E performance monitoring in both transmit and receive directions. • 12 serial clock/data ports are provided on the system side for DS3/ E3/STS-1E interfaces. • Integrates DS3/E3 desynchronizer circuitry necessary to provide DS3/E3 clear channel outputs that meet Bellcore, ANSI and ITU jitter requirements. • 622/155 MHz APS interface for redundancy applications. • Loopback capability for SONET/SDH and DS3/E3/STS-1Es data streams. TX_ASYNC_FRM_IN TX_TOH_CLK_OUT TX_TOH_FRM_OUT TX_TOH_DATA_IN GPPIO[23:0] TX_ASYNC_FRM_OUT SYS_REFCLK_OUT Figure 1: Block Diagram TX_PCLK_OUT TX_LINE_PRTY RX_PFRM_IN RX_PDATA_IN_[7:0] RX_PCLK_IN RX_LINE_PRTY LINE SIDE INTERFACE TX_PDATA_OUT_[7:0] FR PM 1 TOH INSERT TX TX_SDATA_OUT TX_SCLK_OUT Dmap 1 12 FRAMER SEL TOH MON STS-1 FR/TOH MON STS-1 PTR PROC 1 GENERATE DS3 E3 MAP Intrfc DS3/E3 FIFOGenerator Frame 1 1 12 1 12 POH MONITOR 12 RX_LS_[1:4]_[1:3]_DATA RX DS3/E3 PTR INTPRT TOH DROP DS3/E3 FR PM DMAP 1 12 DeSynchronization RX RX_LS_[1:4]_[1:3]_CLK Block Intrfc RX_LS_[1:4]_[1:3]_FRM_OUT 1 12 STS-1 FR GEN SEL 1 12 1 MICROPROCESSOR I/F RX_STS_CLK_IN PROT_DATA_IN PROT_CLK_IN PROT_CLK_OUT PROT_DATA_OUT Final/Production Release Information - The information contained in this document is about a product in its fully tested and characterized phase.All features described herein are supported. Contact AMCC for updates to this document and the latest product status Empowering Intelligent Optical Networks APS_INTB BUSMODE RDYB_DTACKB RDB_DSB WRB_RWB CSN ADDR[13:0] D[15:0] INTB RSTB RX_TOH_CLK_OUT RX_TOH_DATA_OUT RX_TOH_FRM_OUT RX_LOSEXT RX_ALM_OUT TX_LS_[1:4_][1:3]_DATA TX_LS_[1:4]_[1:3]_CLK TX_LS_[1:4]_[1:3]_FRM_IN TX SPE/VC FRAMER RX_SDATA_IN RX_SCLK_IN DS3 DS3/E3 GPIO REG 12 ORINOCO Product Brief STS-12/STM-4 DS3/E3/STS-1E SONET/SDH Mapper Overview SONET/SDH Processing The ORINOCO implements SONET/SDH processing for STS-12/ STM-4 or STS-3/STM-1 data streams. It can support STS-1 signals within an STS-12 or STS-3, or any combination of TUG-3/ AU-4 or AU-3 signals within an STM-1 or STM-4. The ORINOCO supports the mapping of DS3, E3 or STS-1 tributaries into SONET or SDH. For DS3/E3/STS-1E tributaries, the ORINOCO provides full framing and performance monitoring. In the SONET/SDH receive direction, the ORINOCO performs framing, descrambling, and TOH monitoring, including B1/B2 performance monitoring, serial channel access to the DCC, User Channel and Orderwire bytes, and monitoring of the J0, K1K2 (APS, AIS-L and RDI-L detection), S1 and M1 bytes. While processing the received pointers, the ORINOCO locates the start of the embedded SPEs and provides monitoring capabilities for the POH and pointer bytes. In the SONET/SDH transmit direction, the ORINOCO generates the appropriate SPE/VCs containing the input DS3/E3/STS-1E signals, including generation of path overhead (with generation of AIS-P and RDI-P). A SONET/SDH STS-12/STM-4 or STS-3/STM1 frame is then created, with its corresponding TOH. The user has the ability to control the contents of all defined TOH bytes, including register map control of the K1K2, J0, M1 and S1 bytes, as well as serial channel access to the DCC, User Channel and Orderwire bytes. The B1 and B2 bytes are automatically generated, as well as AIS-L and RDI-L indications. The ORINOCO is SONET and SDH standards compliant with Bellcore GR-253 and GR-499 and ITU G.707 and G.783. DS3/E3 Processing The ORINOCO provides DS3/E3 mapper and de-mapper functions. The DS3/E3 mapper accepts data from an external DS3/E3 input, looped-back DS3/E3 tributaries, or internal DS3/E3 frame generators. The ORINOCO provides full DS3/E3 framing and performance monitoring in both transmit and receive directions. The ORINOCO supports both M23 and C-bit parity DS3 frame formats. It provides the following DS3 mapping options: DS3/STS-1, DS3/AU-3 and DS3/TUG-3/AU-4. The ORINOCO supports both the G.751 and G.832 E3 frame formats. It provides the following E3 mapping options: E3/AU-3 and E3/TUG-3/AU-4. DS3 monitoring functionality includes support for AIS, idle, RAI, AIC, FEAC, path parity, FEBE detection/insertion, detection of DS3 frame errors (OOF and SEF), and DS3 performance monitoring per ANSI T1.231. E3 monitoring functionality includes detection of REI, RDI, LOF, AIS, and BIP-4/BIP-8 parity errors, as well as errored block and errored second indications. STS-1 Processing The ORINOCO provides STS-1 mapper and de-mapper functions. The STS-1 mapper accepts data from external STS-1E 2 Part Number S1204CBI21, Revision 1.5, Dec. 2002 inputs and/or from looped-back STS-1 tributaries. The ORINOCO provides full STS-1 framing, descrambling, performance monitoring and pointer processing in the transmit direction. In the receive direction, the ORINOCO provides full STS-1 frame generation and scrambling. Line Interface On the line side, the ORINOCO supports an 8-bit parallel interface which operates at 77.76 MHz for STS-12/STM-4 applications. In this mode, the device is connected to the S3037 parallel-to-serial converter (see application figure below). Optionally, the ORINOCO supports a serial line interface which operates at 622.08 MHz for STS-12/STM-4 applications, or at 155.52 MHz or STS-3/STM-1. In these applications, the device is connected to the S3024 clock recovery device. APS Interface The ORINOCO provides APS input and output interfaces to convey signals between two S1204 devices configured for APS operation. This configuration supports both 1+1 and 1:1 configurations. The APS interface consists of serial clock and data, operating a 622 MHz for STS-12/STM-4 operation, or 155 MHz for STS-3/STM-1 operation. System Interface The ORINOCO supports up to 12 DS3/E3/STS1 tributaries. In the SONET/SDH Receive direction, the ORINOCO generates a serial (NRZ) data signal, accompanied by a smoothed DS3/E3 clock and a start of frame indication for each DS3/E3 tributary. For STS1E tributaries, the ORINOCO provides RX serial (NRZ) data and clock and frame start signals at 51.84 MHz. In the SONET/SDH Transmit direction, the ORINOCO provides two modes of operation. In clear-channel mode, the ORINOCO accepts a full DS3/E3 signal, payload and overhead bits, and performs framing on the incoming signal. The frame start inputs are ignored in this mode of operation. In DS3 payload only mode, the ORINOCO accepts the DS3 payload only on the data inputs. The frame start signal indicates the start of the payload (the first data bit following the X1 overhead bit). The ORINOCO maps the DS3 payload data into a full DS3 frame, prior to mapping into a SONET/SDH SPE. DS3/E3 Desynchronizer The ORINOCO provides for dense DS3/E3 integration by performing all functions related to DS3/E3 desynchronization. The clock smoother consists of a single, off-chip clock reference together with 12 independent on-chip digitally controlled modulators, digital filters and frequency detectors. This desynchronizer circuitry provides jitter and wander compliance to the ANSI T1105.03-1994 and ANSI T1-105.03b-1997 specifications. Packaging and Power The ORINOCO is packaged in a ceramic ball grid array totaling 474 pins (CBGA474). Two power sources, +3.3V and +2.5V, supplies the I/O and core voltages respectively. Empowering Intelligent Optical Networks ORINOCO Product Brief STS-12/STM-4 DS3/E3/STS-1E SONET/SDH Mapper Part Number S1204CBI21, Revision 1.5, Dec. 2002 Applications • Edge and MultiService Switches • Optical Transport Systems • WAN Aggregation Terminals • SONET/SDH Multiplexers and Digital Cross Connects Figure 2: Applications APPLICATION: - Universal DS3 Line Card for Multi-Service Applications - High Density ATM over DS3 Termination - High Density DS3 Aggregation for Synchronous X-Connects Microprocessor Control Control Data Addr 8 Addr 12 12 Data Control Control Addr TX_LS_[1:4][1:3]_DATA DS3/E3/STS-1 LIU RX_LS_[1:4][1:3]_DATA RX_LS_[1:4][1:3]_CLK ORINOCO S1204CBI 622 Mhz Interface S3037 TX_LS_[1:4][1:3]_CLK Data TX_CLK TX_SYS_DAT[15:0] U T O P I A 8-bit 78Mhz Interface 16 Utopia Level-2 System Interface RX_CLK RX_SYS_DAT[15:0] NILE S1202CBI ATM Switch OR IP ROUTER TX_DS3_[1:12]_DATA SYS_LS_REFCLK_IN TX_DS3_[1:12]_CLK RX_DS3_[1:12]_DATA DS3 DS3/E3/STS-1 Line Interfaces (up to 12) RX_DS3_[1:12]_GAP/SM_CLK RX_DS3_[1:12]_FIFO_[1:0] Ref Clk TOH Insertion and Extraction TOH Insertion and Extraction Transport Line Card (OC-12, OC-48, OC-192) STS-1 Cross-Connect Fractional DS3 Support Multi Channel HDLC Processor Switching/ Routing Logic DS3 Clear Channel for Packet over SONET Application High Density Data Termination Figure 3: Application OC-12 APPLICATION: OC-12 Aggregation using the Serial 622 Mbit/s Interface Microprocessor Control 12 STS-12 Line Interface SONET Line Side Interface Fiber Optic Transceiver Addr SerRxD± 622Mhz Clk Recovery AMCC S3024 Reference Clock RX_LOSEXT RX_SCLK_IN± RX_SDATA_IN± 16 Data TX_SCLK_OUT± TX_SDATA_OUT± HP HFCT5208 Sumitomo SDM7202 * Can be replaced by a backplane driver Control TX_LS_[1:4][1:3]_DATA TX_LS_[1:4][1:3]_CLK ORINOCO S1204CBI RX_LS_[1:4][1:3]_DATA DS3/E3/STS-1 LIU RX_LS_[1:4][1:3]_CLK SYS_REFCLK_IN DS3/E3/STS-1 Line Interfaces (up to 12) Ref Clk Empowering Intelligent Optical Networks 3 ORINOCO Product Brief STS-12/STM-4 DS3/E3/STS-1E SONET/SDH Mapper Part Number S1204CBI21, Revision 1.5, Dec. 2002 Figure 4: Application OC-12 APPLICATION: OC-12 Aggregation using the 8-bit, 78Mhz Interface Microprocessor Control Reference Clock Control Addr 12 Data 16 TX_PCLK_IN SONET Line Side Interface SerTxD± Fiber Optic Transceiver SerRxD± HP HFCT5208 Sumitomo SDM7202 P/S & S/P TX_PDATA_OUT[7:0] SONET XCVR RX_LOSEXT with RX_PCLK_IN Clk Recovery RX_PDATA_IN[7:0] AMCC S3037 TX_LS_[1:4][1:3]_DATA TX_LS_[1:4][1:3]_CLK DS3/E3/STS-1 LIU RX_LS_[1:4][1:3]_DATA ORINOCO S1204CBI RX_LS_[1:4][1:3]_CLK SYS_LS_REFCLK_IN STS-12 Line Interface DS3/E3/STS-1 Line Interfaces (up to 12) Ref Clk Figure 5: Application OC-48 Microprocessor Control APPLICATION: OC-48 Aggregation 12 Control Addr 16 Data TX_PCLK_OUT TX_LS_[1:4][1:3]_DATA TX_PDATA_OUT[7:0] TX_LS_[1:4][1:3]_CLK RX_LOSEXT Sumitomo SDT8008-T Fiber Optic Transmitter Fiber Optic Receiver Sumitomo SDT8908-R SerTxD± TxClk± SerRxD± RxClk± DS3/E3/STS-1 LIU RX_LS_[1:4][1:3]_DATA ORINOCO S1204CBI RX_PDATA_IN[7:0] AMCC S3041 RX_LS_[1:4][1:3]_CLK P/S SONET TX AMCC S3042 S/P SONET RX with Clk Recovery STS-48 <-> STS-12 De/Mux OC-48 Optical Interface RX_PCLK_IN DS3/E3/STS-1 Line Interfaces (up to 12) TX_PCLK_OUT TX_PDATA_OUT[7:0] RX_LOSEXT RX_PCLK_IN RX_PDATA_IN[7:0] Four(4) Parallel ORINOCOs Microprocessor Control Control Addr 12 Data 16 TX_PCLK_OUT Reference Clock TX_LS_[1:4][1:3]_DATA TX_PDATA_OUT[7:0] TX_LS_[1:4][1:3]_CLK RX_LOSEXT RX_PCLK_IN RX_PDATA_IN[7:0] ORINOCO S1204CBI RX_LS_[1:4][1:3]_DATA DS3/E3/STS-1 LIU RX_LS_[1:4][1:3]_CLK AMCC S3045 DS3/E3/STS-1 Line Interfaces (up to 12) AMCC reserves the right to make changes to its products, or to discontinue any product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied upon is current. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright © 2002 Applied Micro Circuits Corporation. All Rights Reserved. 200 Minuteman Road • Andover, MA 01810 • Tel: 978-247-8000 • Fax: 978-623-0024 • http:// 4 Empowering Intelligent Optical Networks