AMCC S3031

®
DEVICE
SPECIFICATION
E4/STM-1/OC-3
ATM TRANSCEIVER
S3031B
E4/STM-1/OC-3 ATM TRANSCEIVER
S3031B
GENERAL DESCRIPTION
FEATURES
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Complies with Bellcore and ITU-T
specifications
On-chip high-frequency PLLs for clock
generation and clock recovery
On-chip analog circuitry for transformer
driver and equalization
Supports 139.264 Mbps (E4) and 155.52
Mbps (OC-3) transmission rates
Supports 139.264 Mbps and 155.52 Mbps
Coded Mark Inversion (CMI) interfaces
TTL Reference frequencies of 19.44 and
38.88 MHz (OC-3) or 17.408 and 34.816
MHz (E4)
Interface to both PECL and TTL logic
Lock detect on clock recovery function —
monitors run length and frequency
Serial and 4 bit (nibble) system interfaces
Low jitter PECL interface
+5V operation
100 PQFP/TEP package
Supports both electrical and optical interfaces
APPLICATIONS
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ATM over SONET/SDH
OC-3/STM-1 or E4-based transmission
systems
OC-3/STM-1 or E4 modules
OC-3/STM-1 or E4 test equipment
Section repeaters
Add Drop Multiplexers (ADM)
Broadband cross-connects
Fiber optic terminators
Fiber optic test equipment
The S3031B transceiver chip is a fully integrated CMI
encoding transmitter and CMI decoding receiver. The
chip derives high speed timing and data signals for
SONET/SDH or PDH-based equipment. The circuit is
implemented using AMCC’s proven Phase Locked Loop
(PLL) technology. Figures 1a and 1b show typical
network applications.
The S3031B has two independent VCOs which are
synchronized to the local NRZ transmitted data and the
received CMI data respectively. The chip can be used
with either a 19.44 MHz or a 38.88 MHz reference clock
when operated in the SONET/SDH OC-3 mode. In E4
mode the chip can be operated with a 17.408 MHz or a
34.816 MHz reference in support of existing system
clocking schemes. On-chip coded-mark-inversion (CMI)
encoding and decoding is provided for 139.264 Mbps
and 155.52 Mbps interfaces.
The low jitter PECL interface for the serial data inputs
and the PECL nibble clock interface guarantee compliance with the bit-error rate requirements of the Bellcore
and ITU-T standards. The S3031B is packaged in a
0.65 mm pitch 100-pin PQFP/TEP.
The S3031B provides the major active components onchip for a coaxial cable interface, including analog
transformer driver circuitry and equalization interface
circuitry. Discrete controls permit separate selection of
CMI or NRZ operation and analog (coaxial copper) or
PECL (optical module) media interfaces. Both line
loopback and diagnostic local loopback operation are
supported.
Figure 1a. Electrical Interface
E4/STM-1/OC-3
OVERHEAD
PROCESSOR
139.264/155.52 Mbps NRZ
COAX
139.264/155.52 Mbps CMI
139.264/155.52 Mbps NRZ
XFMR
S3031B
XCVR
139.264/155.52 Mbps CMI
OSC
XFMR
COAX
17.408/19.44 MHz
Figure 1b. Optical Interface
E4/STM-1/OC-3
OVERHEAD
PROCESSOR
139.264/155.52 Mbps NRZ
139.264/155.52 Mbps
OTX
139.264/155.52 Mbps NRZ
S3031B
XCVR
139.264/155.52 Mbps
ORX
OSC
August 19, 1999 / Revision D
17.408/19.44 MHz
1
S3031B
E4/STM-1/OC-3 ATM TRANSCEIVER
SONET/SDH OVERVIEW
Synchronous Optical Network (SONET) is a standard
for connecting one fiber system to another at the optical level. SONET, together with the Synchronous
Digital Hierarchy (SDH) administered by the ITU-T,
form a single international standard for fiber interconnect between telephone networks of different countries. SONET is capable of accommodating a variety
of transmission rates and applications.
The SONET standard is a layered protocol with four
separate layers defined. These are:
• Photonic
• Section
• Line
• Path
Figure 2 shows the layers and their functions. Each
of the layers has overhead bandwidth dedicated to
administration and maintenance. The photonic layer
simply handles the conversion from electrical to optical and back with no overhead. It is responsible for
transmitting the electrical signals in optical form over
the physical media. The section layer handles the
transport of the framed electrical signals across the
optical cable from one end to the next. Key functions
of this layer are framing, scrambling, and error monitoring. The line layer is responsible for the reliable
transmission of the path layer information stream
carrying voice, data, and video signals. Its main functions are synchronization, multiplexing, and reliable
transport. The path layer is responsible for the actual
transport of services at the appropriate signaling rates.
Data Rates and Signal Hierarchy
Table 1 contains the data rates and signal designations of the SONET hierarchy. The lowest level is the
basic SONET signal referred to as the synchronous
transport signal level-1 (STS-1). An STS-N signal is
made up of N byte-interleaved STS-1 signals. The
optical counterpart of each STS-N signal is an optical
carrier level-N signal (OC-N). The S3031B supports
OC-3 rates (155.52 Mbps).
Frame and Byte Boundary Detection
Table 1. SONET Signal Hierarchy
Elec.
ITU-T
STS-1
STS-3
STS-12
STS-24
STS-48
STM-1
STM-4
STM-16
Optical Data Rate (Mbps)
OC-1
OC-3
OC-12
OC-24
OC-48
51.84
155.52
622.08
1244.16
2488.32
The SONET/SDH fundamental frame format for STS-3
consists of nine transport overhead bytes followed by
Synchronous Payload Envelope (SPE) bytes. This pattern of 9 overhead and 261 SPE bytes is repeated
nine times in each frame. Frame and byte boundaries
are detected using the A1 and A2 bytes found in the
transport overhead. (See Figure 3.)
For more details on SONET operations, refer to the
Bellcore SONET standard document.
Figure 2. SONET Structure
Figure 3. STS-3/OC Frame Format
Layer Overhead
(Embedded Ops
Channel)
Functions
Payload to
SPE mapping
Maintenance,
protection,
switching
Scrambling,
framing
Optical
transmission
Path layer
Path layer
Line layer
Line layer
Section layer
Section layer
Photonic layer
192 Kbps
Photonic layer 0 bps
9
Rows
A1
A1
A2
A2
A2
J0
Z0
Z0
B1
*
*
E1
*
*
F1
*
*
D1
*
*
D2
*
*
D3
*
*
H1
H1
H1
H2
H2
H2
H3
H3
H3
B2
B2
B2
K1
*
*
K2
*
*
D4
*
*
D5
*
*
D6
*
*
D7
*
*
D8
*
*
D9
*
*
D10
*
*
D11
*
*
D12
*
*
S1
Z1
Z1
Z2
Z2
M1
E2
*
*
Synchronous Payload
Envelope
9 Columns
261 Columns
End Equipment
125 µsec
▲
2
9 x 261 =
2349 bytes
Transport Overhead
Fiber Cable
▲
End Equipment
576 Kbps
A1
August 19, 1999 / Revision D
E4/STM-1/OC-3 ATM TRANSCEIVER
S3031B OVERVIEW
The S3031B transceiver can be used to implement the
front end of STS-3, OC-3 or E4 equipment. The block
diagram in Figure 9 shows the basic operation of the
chip.
When the S3031B is operating in the nibble parallel
mode, the transmitter VCO is synchronized to the 38.88
MHz nibble clock as both the reference clock and the
data transfer clock. If the serial input is selected as the
transmitter data source the VCO will be synchronized
directly to the incoming data. Serial operation of the
S3031B transmitter section is possible with either the
38.88 MHz or 19.44 MHz reference oscillator. In the
absence of incoming serial data the transmitter section
will operate as a clock synthesizer. The receiver section
performs clock recovery by synchronizing its on-chip
VCO directly to the incoming data stream.
In E4 operation, the 34.816 MHz REFCLK is used as the
nibble clock. Thus in Nibble parallel mode, the S3031B
transmitter section supports unscrambled E4 operation.
If serial mode is selected, the NRZ E4 data must be
scrambled to allow the PLL to lock onto the data transitions.
The S3031B provides a PECL output for an optical
interface and two transformer driver outputs for an
electrical interface. One of these drivers is a monitor
output. The S3031B provides a PECL input for an
optical interface and an analog input for an electrical
interface.
The transformer driver outputs are separately enabled.
Status outputs detect the disabled, stuck at 1, stuck at
0, and non-CMI states to qualify the transformer driver
outputs.
The CMI outputs, analog equalizer input section, and
PLL sections are independently powered for isolation
and for power savings when the device is used in single
function applications.
August 19, 1999 / Revision D
S3031B
S3031B TRANSMITTER
ARCHITECTURE/FUNCTIONAL DESIGN
Transmitter Operation
The S3031B chip’s transmitter section performs the last
stages of digital processing of a transmit SONET STS-3
or ITU-T E4 serial or 4-bit nibble parallel data stream.
Clock Recovery
If the serial input data has been selected, and serial
data is present at the TSDATIP/N inputs, the clock is
recovered from the serial data stream at 139.264 MHz
or 155.52 MHz and synthesized to 278.528 MHz or
311.04 MHz to CMI encode the incoming data.
In clock recovery mode, the transmitter PLL continues
to monitor the reference clock with respect to the VCO
and the activity of the serial data input. The transmitter
PLL will re-lock to the reference clock under the following conditions:
1. If the serial data inputs contains insufficient transition
density (run length greater than 100 to 200 bit times).
2. If the VCO drifts away from the local reference clock
by more than 1000 ppm.
If either XFRMENA or XFRMENB are enabled (logic
Low) the density or frequency error defined above will
set the appropriate status (XFRMSTATA and/or
XFRMSTATB) to the low or fault state.
The selected drive status bits will return to the High or
clear state and the PLL will again lock to the data if the
serial data contains sufficient transition density (less
than 100 to 200 bit times between rising edges), and the
serial clock is within 250 ppm of the reference clock
determined frequency.
Optical and Electrical Interfaces
The digital data outputs (TSDATOP/N) are the PECL
outputs for an optical interface and are to be connected to an electrical to optical converter, as shown
in Figure 17. This data is also routed to two on-chip
transformer drivers and sent out on XFRMDRVA and
XFRMDRVB to drive the transformers of the electrical interface, as shown in Figure 19. These outputs
are shut off when the reset is active, XFRMEN is active,
or when the chip is in NRZ mode and the data inputs
are in the logic zero state. The electrical characteristics
for the transformer drivers are shown in Table 9.
3
S3031B
Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 9 is
comprised of two 4-bit registers. The first register latches
the data from the PIN[3:0] bus on the rising edge of
REFCLK. The second register is a parallel loadable
shift register which takes its parallel input from the first
register.
The parallel data transfer between registers is accomplished on the falling edge of REFCLK. The serial data
is shifted out at the serial bit rate to the CMI encoder.
CMI Encoding
E4/STM-1/OC-3 ATM TRANSCEIVER
Figure 4. CMI Encoded Data
0
1
0
1
1
1
0
A2
A1
t
Figure 5. Jitter Generation Specifications
Compliant to G.823 and G.825
Coded Mark Inversion format (CMI) ensures at least
one data transition per 1.5 bit periods, thus aiding
the clock recovery process. Zeros are represented
by a Low state for one half a bit period, followed by a
High state for the rest of that bit period. Ones are
represented by a steady Low or High state for a full
bit period. The state of the ones bit period alternates
at each occurrence of a one. Figure 4 shows an
example of CMI-encoded data. The STS-3 electrical
interface and the E4 interface are specified to have
CMI-encoded data.
The CMI encoder on the S3031B accepts serial data
from TSDATIP/N at 139.264 or 155.52 Mb/s. The
data is then encoded into CMI format, and the result
is shifted out with transitions at twice the basic data
rate. The CMISEL input controls whether the CMI encoder is in the data path. A CMI code violation can be
inserted for diagnostic purposes by activating the
DLCV input. The DLCV input is sampled on every
cycle of the serial clock to allow the single or multiple
line code violations to be inserted. This violation is
either an inverted zero code or an inversion of the
alternating ones logic level, depending on the state of
the data. Subsequent one codes take into account the
induced violation to avoid error multiplication.
0
A1
A2
f2
f1
f3
f1(Hz) f2(kHz) f3(MHz)
A2
A1
OC-3
—
—
—
0.01
0.01(1)
STM-1
500
65
1.3
1.5(2)
0.15(2)
3.5
(2)
E4
200
10
(1)
1.5
0.075(2)
1. UI rms
2. UI p–p
Figure 6. S3031B Maximum Allowable Input Jitter
A1
Slope = +20 dB/decade
Jitter Generation
Jitter Generation is defined as the amount of jitter at
the OC-3 or E-4 output of equipment. Jitter generation for OC-3 shall not exceed 0.01 UI rms when
measured using a highpass filter with a 12 kHz cutoff
frequency.
For STM-1 and E4, the jitter generated shall not exceed the specifications shown in Figure 5.
In order to meet the SONET, STM-1 E4 jitter specifications as shown in Figure 5, the TSDATIP/N serial data
input must meet the jitter characteristics as shown in
Figure 6.
4
A2
500Hz
f2
f2(kHz)
225 kHz 1.3 MHz
A1
A2
OC-3
—
0.005(1) 0.005(1)
STM-1
65
1.45(2) 0.10(2)
E4
10
1.45(2) 0.025(2)
1. UI rms
2. UI p–p
August 19, 1999 / Revision D
E4/STM-1/OC-3 ATM TRANSCEIVER
S3031B
Figure 7. Mask of a pulse corresponding to a binary 0 Compliant to G.703
T=
7.18 ns for E4
6.43 ns for 155 CMI
Figure 8. Mask of a pulse corresponding to a binary 1 Compliant to G.703
t=
1.35 ns for E4
1.20 ns for 155 CMI
T=
7.18 ns for E4
6.43 ns for 155 CMI
Notes:
1. The maximum “steady state” amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to
fall into the dotted area, bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state
level by more than 0.05V. The possibility of relaxing the amount by which the overshoot may exceed the steady state level
is under study.
2. For the purpose of these masks, the rise time and decay time should be measured between -0.4V and 0.4V, and should not
exceed 2 ns.
3. The inverse pulse in Figure 8 will have the same characteristics, noting that the timing tolerances at the zero level of the
negative and positive transitions are ±0.1 ns and ±0.5 ns respectively.
August 19, 1999 / Revision D
5
S3031B
E4/STM-1/OC-3 ATM TRANSCEIVER
Figure 9. S3031B OC-3/STM-1/E4 Transceiver
CAP1
TX
VCO
LOOP
FILTER
CAP2
TREFCLKOUT
REFCLK
TSTCLKEN
TSCLKOP/N
CLOCK
DIVIDER
REFSEL
2
C
M
I
CMISEL
TXRSTB
XFRMSTATA/B
TRANSFORMER
DRIVERS
DLCV
XFRMDRVA
4
PIN[3:0]
XFRMDRVB
LLEB
(LINELOOP)*
4:1
PARALLEL
TO SERIAL
TX
PHASE DETECTOR
2:1
MUX
2:1
MUX
TSDATIP/N
TSDATOP/N
(LOOPDATA)*
2
XFRMENA/B
SERDATEN
CAP3
LOOP
FILTER
CAP4
RX
VCO
SERDSEL
POCLK
TSTCLKEN
RSCLKOP/N
CLOCK
DIVIDER
TESTCLK
RXRSTB
GIN
LCV
C
M
I
CMISEL
LOCK
DETECTOR
G
LOSOUT
GOUT
BUFINA, BUFINB
2
RX
PHASE DETECTOR
BUFOUT
LOSOPT
LOSIN
LOSREF
RSDATIP/N
ANDATIN
EQUALSEL
6
RSDATOP/N
2:1
MUX
(LINELOOP)*
2:1 (LOOPDATA)*
MUX
2:1
MUX
1:4
SERIAL TO
PARALLEL
4
POUT[3:0]
DLEB
* Internal Connections Only
August 19, 1999 / Revision D
E4/STM-1/OC-3 ATM TRANSCEIVER
S3031B
S3031B RECEIVER OPERATION
Optical and Electrical Interfaces
The S3031B transceiver chip provides the first stage of
the digital process of a receive SONET STS-3 or ITUT E4 serial bit stream. A Coded Mark Inversion (CMI)
decoder can be enabled for decoding STS-3 electrical
and E4 signal. The recovered and decoded signal is
output as both retimed bit-serial 155.52 or 139.264
Mbps NRZ data and as a 38.88 or 34.816 Mbyte/s 4-bit
nibble parallel outputs.
The digital data inputs (RSDATIP/N) are the PECL
inputs from an optical to electrical converter, as shown
in Figure 16. The data input for the coaxial interface is
ANDATIN, which is the serial data input from the equalizer circuit and should be connected as shown in Figure
19. The EQUALSEL input is used to select either
RSDATIP/N or ANDATIN.
Clock recovery is performed on the incoming scrambled
NRZ or CMI-coded data stream. A reference clock is
required for phase locked loop start-up and proper
operation under loss of signal conditions. An integral
prescaler and phase locked loop circuit is used to
multiply this reference frequency to the nominal bit rate.
CMI Decoding
The CMI decoder block on the S3031B accepts serial
data from the TSDATIP/N input at the rate of 139.264 or
155.52 Mbps. The incoming CMI data, which has transitions that represent this data rate (the clock associated with this data would be running at twice this rate),
is then decoded from CMI to NRZ format.
Clock Recovery
The clock recovery function, as shown in the block
diagram in Figure 9, generates a clock that is frequency matched to the incoming data baud rate at
the RSDATIP/N differential inputs. The clock is phase
aligned by a PLL so that it samples the data in the
center of the data eye pattern.
The phase relationship between the edge transitions
of the data and those of the generated clock are
compared by a phase/frequency discriminator. Output pulses from the discriminator indicate the required
direction of phase corrections. These pulses are
smoothed by an integral loop filter. The output of the
loop filter controls the frequency of the Voltage Controlled Oscillator (VCO), which generates the recovered clock. Frequency stability without incoming data
is guaranteed by an alternate reference input
(REFCLK) to which the PLL locks when data is lost.
When the Test Clock Enable (TSTCLKEN) input is
set high, the clock recovery block is disabled. The
Test Clock (TESTCLK) is used as the bit rate clock
input in place of the recovered clock. This feature is
used for functional testing of the device.
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET or
E4 data signal. This transfer function yields a typical
capture time of 16 µs for random incoming NRZ data.
The total loop dynamics of the clock recovery PLL yield
a jitter tolerance which exceeds the minimum tolerance
proposed for OC-3/STM-1/E4 equipment by the Bellcore
and ITU-T documents, shown in Figure 12.
August 19, 1999 / Revision D
Loss of Signal
The clock recovery circuit monitors the incoming data
stream for loss of signal. If the incoming encoded data
stream has had no transitions continuously for 100 to
200 recovered clock cycles, loss of signal is declared
and the PLL will switch from locking onto the incoming
data to locking onto the reference clock per the requirements of G.775. Alternatively, the loss-of signal (LOSIN)
input can force a loss-of-signal condition. This signal is
compared internally against the LOSREF input reference voltage. This input can be set to meet the conditions shown in Figure 10. If the zero to peak signal level
drops below the LOSREF/20 voltage level for more than
100 to 200 bit intervals, a loss of signal condition will be
indicated on the LOSOUT pin and the PLL will change
its reference from the serial data stream to the reference
clock. When the peak input voltage is greater than
LOSREF/10, the loss of signal condition will be
deasserted and the PLL will recover the clock from the
serial data inputs.
In clock recovery mode, the receiver PLL also monitors the reference clock with respect to the VCO. If the
VCO drifts away from the local reference clock by
more than 1000 ppm the PLL will re-lock to the reference clock and the LOSOUT will be set to the active
low condition.
The LOSOUT will return to the High or inactive state
and the PLL will again lock to the data if the serial data
contains sufficient transition density (less than 100 to
200 bit times between rising edges), and the serial
clock is within 250 ppm of the reference clock determined frequency.
7
S3031B
E4/STM-1/OC-3 ATM TRANSCEIVER
In NRZ mode, a logic Low level on the LOSOPT input
will cause the PLL to change its reference to the
reference clock. This pin should be driven by a PECL
compatible level signal detect signal from the fiber
optic receiver.
Serial Clock Output to Data Output Timing
The serial data is clocked out on the falling edge of
RSCLKOP. (See Figure 11.) This timing is valid in
both NRZ and CMI modes.
Reference Clock Input
The reference clock input seen in Figure 9 provides
backup reference clock signals to the clock recovery
block when the clock recovery block detects a loss of
signal condition. It contains a counter that divides the
clock output from the clock recovery block down to
the same frequency as the Reference Clock
(REFCLK).
Figure 11. S3031B Clock to Data Timing
Serial to Parallel Converter
The Serial to Parallel Converter consists of two 4-bit
registers. The first is a serial-in, parallel-out shift register, which performs serial to parallel conversion clocked
by the clock recovery block. The second is the output
holding register. On the falling edge of the free running
POCLK, the data in the serial-in, parallel-out register is
transferred to the output holding register which drives
POUT[3:0].
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to peak
amplitude of sinusoidal jitter applied on the input signal
that causes an equivalent 1 dB optical/electrical power
penalty. OC-3 and E-4 input jitter tolerance requirements are shown in Figure 12.
The S3031B PLL complies with the minimum jitter tolerance for clock recovery proposed for SONET/SDH
equipment defined by the Bellcore TA-NWT-000253
standard when used as shown in Figure 12. The
S3031B PLL also complies with the minimum jitter
tolerance for clock recovery as defined in the ITU-T E4
specification when used as shown in Figure 19.
RSDATOP
RSCLKOP/N
tPSER
Figure 12. Clock Recovery Jitter Tolerance
Compliant to G.823 and G.825
Sinusoidal
Input Jitter
Amplitude
(UI p-p)
A3
A4
f9
f9
f0
(Hz) (Hz)
OC-3
10
f0
f1
f2
f1
(Hz)
f2
(kHz)
f3
(kHz)
f3
f4
A2
f4
(MHz)
A3
A4
1.5 0.15
300
6.5
65
—
15
STM-1 (Optical) 0.125 19.3
500
6.5
65
1.3
391 1.5 0.15
STM-1 (Electrical) 0.125 19.3
500
6.5
65
1.3
391 1.5 0.15
200
0.5
10
3.5
15 1.5 0.075
E4
Figure 10. Criteria for Determination of Transition
Conditions. Compliant to G.775.
A2
30
TBD TBD
Note:
1. Only tested to 20 due to test equipment limitation.
nominal value
maximum
cable loss
3 dB
17
Tolerance range
“no transition condition” or “transition
condition” may be declared
35
Level below Nominal
“transition condition”
must be declared
“no transition condition”
must be declared
The signal level 17 is (maximum cable loss +3)
dB below nominal.
The signal level 35 is greater than the maximum
expected cross-talk level.
8
August 19, 1999 / Revision D
E4/STM-1/OC-3 ATM TRANSCEIVER
S3031B
Table 2. Transmitter Input Pin Assignment and Description
Pin Name
Level
I/O
Pin #
Description
TTL
I
26
Test Clock Enable. Active High. Enables the TESTCLK clock to
be used in place of the VCO for testing. Allows a means of testing
the functions of the chip without the use of the PLL.
Singleended
PECL
I
86
Diagnostic Line Code Violation. Set High to force a CMI line code
violation. DLCV is only active in CMI mode. DLCV is sampled on
the falling edge of TSCLKOP. DLCV does not affect XFRMSTATB
or XFRMSTATB.
CMISEL
TTL
I
27
CMI Select. Used to select a CMI or NRZ. A logic High selects
CMI mode. A logic Low selects NRZ mode. Both the TSDATOP/N
and the XFRMDRV outputs are controlled by CMISEL.
TXRSTB
TTL
I
97
Transmitter Reset. Active Low. Initializes the device to a known
state. Serial data outputs are held to zero, and the Transformer
Driver and Status outputs are forced Low.
I
21
22
Loop Filter Capacitor Network. The loop filter capacitor network is
connected to these pins. The capacitor value should be 1.0 µF
±10%, X7R dielectric. The resistors should be 100 Ω for serial
mode and 1000 Ω for nibble mode operation. See Figure 18.
TSTCLKEN
DLCV
CAP1
CAP2
XFRMENA
TTL
I
92
Transformer Driver Enable. Used to enable the transformer driver
output. A logic Low enables XFRMDRVA. A logic High turns off
the transformer driver output.
XFRMENB
TTL
I
94
Transformer Driver Enable.Used to enable the transformer driver
output. A logic Low enables XFRMDRVB. A logic High turns off
the transformer driver output.
SERDATEN
TTL
I
8
Serial Data Enable. Used to enable the transmit serial data
outputs. A logic Low enables TSDATOP/N. A logic High turns off
the serial data outputs.
PIN3
PIN2
PIN1
PIN0
TTL
I
1
100
99
98
Parallel Data Input. A 38.88 Mbyte/sec 4-bit wide Nibble aligned
to the REFCLK reference clock. REFSEL and SERDSEL must
both be at logic Low for transmitter operation with the nibble
inputs.
Diff.
PECL
I
15
16
Transmit Serial Data In. The transmit clock is derived from
transitions on these inputs when SERDSEL is High. No phase
relationship to REFCLK is required. Either 19.44 MHz or 38.88
MHz reference operation may be selected. SERDSEL must be at
logic High for transmitter operation with the serial data input.
TSDATIP
TSDATIN
August 19, 1999 / Revision D
9
S3031B
E4/STM-1/OC-3 ATM TRANSCEIVER
Table 3. Transmitter Output Pin Assignment and Description
Pin Name
Level
I/O
Pin #
Description
TSDATOP
TSDATON
Diff.
PECL
O
12
13
Transmit Serial Data Out. In NRZ mode, this signal is the delayed
version of the incoming data stream (TSDATIP/N) updated on the
falling edge of Serial Clock Out (TSCLKOP). In CMI mode, this
signal is the CMI-encoded version of TSDATIP/N.
TSCLKOP
TSCLKON
Diff.
PECL
O
9
10
Transmit Serial Clock Out. This signal is a 155.52 MHz clock that
is phase–aligned with Transmit Serial Data Out in NRZ mode. In
CMI mode, TSCLKOP/N cannot be used.
TTL
O
95
Transmit Reference Clock Out. Single-ended TTL reference clock
output.
XFRMDRVA
Analog
O
89
Transformer Driver A. Used to drive the transformer of the
electrical interface. For E4 operation this output should be
connected per Figure 19 to provide the correct G.703 compatible
output levels from the transformer when connected to the
specified 75Ω cable.
XFRMDRVB
Analog
O
88
Transformer Driver B. Used to drive the monitor transformer of the
electrical interface. This output should be connected per Figure
19 to provide the correct output levels from the transformer when
connected to the specified 75Ω cable.
XFRMSTATA
TTL
O
93
Transformer Drive A Status. When High, the XFRMDRVA output
is enabled, CMI mode is correctly selected, and the PLL is locked
to switching data at the TSDATIP/N or PIN[3:0] input. Logic Low
indicates deselection or code error.
XFRMSTATB
TTL
O
91
Transformer Drive B Status. When High, the XFRMDRVB output
is enabled, CMI mode is correctly selected, and the PLL is locked
to switching data at the TSDATIP/N or PIN[3:0] input. Logic Low
indicates deselection or code error.
TREFCLKOUT
10
August 19, 1999 / Revision D
E4/STM-1/OC-3 ATM TRANSCEIVER
S3031B
Table 4. Receiver Input Pin Assignment and Description
Pin Name
Level
I/O
Pin #
Description
BUFINA
BUFINB
Analog
I
30
31
Buffer Inputs. Inputs to the equalizer network buffer circuit. This
circuit provides a high impedance load to the transformer
termination network in order to comply with the required return
loss specifications. These pins should be connected as shown in
Figure 19. These pins are electrically equivalent.
ANDATIN
Analog
I
46
Analog Data In. This is the serial data input from the equalizer
circuit. It must be connected to the output of the equalizer circuit
as shown in Figure 19. When the S3031B is used with a fiber optic
receiver this input should be left open and the RSDATIP/N inputs
should be used.
TTL
I
51
Equalization Select Used to select RSDATIP/N or ANDATIN. A
logic High selects ANDATIN.
RSDATIP
RSDATIN
Diff.
PECL
I
66
65
Receive Serial Data In. Clock is recovered from transitions on
these inputs when selected by EQUALSEL.
RXRSTB
TTL
I
75
Receiver Reset. Active Low. Initializes the device to a known
state, shuts off RSCLKOP/N, and forces the PLL to acquire to the
reference clock. A reset of at least 16 ms should be applied at
power-up and whenever it is necessary to reacquire to the
reference clock. The S3031B will also reacquire to the reference
clock if the serial data is held quiescent (constant ones or constant
zeros), or LOSIN or LOSOPT are activated for at least 224 bit
intervals.
GIN
Analog
I
36
Input to 25dB gain block for internal equalizer function.
LOSIN
Analog
I
48
Loss of Signal In. A single-ended input that indicates a loss of
received signal. When the signal level at LOSIN drops below the
voltage level set by LOSREF for greater than 100 to 200 bit
intervals, the data on Serial Data Out (RSDATOP/N) will be forced
to a constant low, and the PLL will change its reference from the
serial data stream to the reference clock. This input is to be driven
by the external bandpass filter and peak detect circuit as shown
in Figure 19. This signal must be used to assure correct automatic
reaquisition to serial data following an interruption and subsequent
reconnection of the data path. This will assure that the PLL does
not “ wander” out of reaquisition range when no signal is applied.
When LOSIN is inactive, data on the RSDATIP/N pins will be
processed normally.
EQUALSEL
August 19, 1999 / Revision D
11
S3031B
E4/STM-1/OC-3 ATM TRANSCEIVER
Table 4. Receiver Input Pin Assignment and Description (Continued)
Pin Name
Level
I/O
Pin #
Description
LOSOPT
PECL
I
52
Loss of Optical Signal. Active Low. This input has the same
functionality as LOSIN, except that it is used in optical mode
instead of electrical. It should be driven by the external optical
receiver module to indicate a loss of received optical power.
LOSREF
Analog
I
49
Loss of Signal Reference. Sets the comparator levels for LOSIN.
(See Table 11.)
I
60
59
Loop Filter Capacitor Network. The loop filter capacitor network is
connected to these pins. The capacitor value should be 1.0µF ±
10% tolerance, X7R dielectric. The resistors should be 51 Ω. See
Figure 18.
CAP3
CAP4
12
August 19, 1999 / Revision D
E4/STM-1/OC-3 ATM TRANSCEIVER
S3031B
Table 5. Receiver Output Pin Assignment and Description
Pin Name
Level
I/ O
Pin #
TTL
O
74
Clock recovery indicator. Active Low. Set High when the internal
clock recovery has locked onto the incoming datastream.
LOSOUT is an asynchronous output. This output is deasserted
when there is no incoming serial data input or when the received
signal has dropped below the reference voltage set by LOSREF
for more than 100 to 200 bit intervals. In this case the PLL locks
to the reference clock. In clock recovery mode, the receiver PLL
also monitors the reference clock with respect to the VCO. If the
VCO drifts away from the local reference clock by more than 1000
ppm the PLL will re-lock to the reference clock and the LOSOUT
will be set to the active Low condition. The LOSOUT will return to
the High or inactive state and the PLL will again lock to the data
if the serial data contains sufficient transition density (less than
100 to 200 bit times between rising edges), and the serial clock is
within 250 ppm of the reference clock determined frequency.
RSDATOP
RSDATON
Diff.
PECL
O
69
68
Receive Serial Data Out. This signal is the NRZ data output. It can
be either a delayed version of the NRZ data input (NRZ mode) or
the decoded CMI data (CMI mode). RSDATOP/N is updated on
the falling edge of RSCLKOP as shown in Figure 11.
RSCLKOP
RSCLKON
Diff.
PECL
O
72
71
Receive Serial Clock Out. This signal is phase–aligned with Serial
Data Out (RSDATOP). (See Figure 11 and Table 7 for timing.)
LCV
SingleEnded
PECL
O
73
Line Code Violation. Set High to indicate that the current bit
contains a CMI line code violation in CMI mode. LCV is updated
on the falling edge of RSCLKOP/N. LCV output is undefined when
running in NRZ mode.
BUFOUT
Analog
O
33
Buffer Output to the equalizer network buffer circuit. This circuit
provides a low impedance driver to the equalizer circuit. This pin
should be connected as shown in Figure 19 to drive the equalizer
network.
POUT3
POUT2
POUT1
POUT0
TTL
O
79
80
81
82
Parallel 4-bit wide output data bus, aligned to the parallel output
clock (POCLK). POUT3 is the first bit transmitted, POUT0 is the
fourth bit transmitted. POUT[3:0] is updated on the falling edge of
POCLK.
POCLK
TTL
O
78
Parallel Output Clock. A 38.88 MHz nominally 50% duty cycle,
nibble rate output clock that is aligned to the POUT[3:0] nibble
serial output data.
GOUT
Analog
O
44
Output of 25dB gain block for the internal equalizer function. To
be AC coupled to ANDATIN. See Figure 19.
LOSOUT
August 19, 1999 / Revision D
Description
13
S3031B
E4/STM-1/OC-3 ATM TRANSCEIVER
Table 6. Common Pin Assignment and Description
Pin Name
Level
I/O
Pin #
REFCLK
TTL
I
6
Reference Clock. Input used as the reference for the receiver VCO
in the absence of received serial data. Used as the reference for
the transmitter VCO in the serial input mode and in the absence
of transmitter serial input data. In parallel transmit interface mode
REFCLK is used as the reference for the internal bit clock
frequency synthesizer and as the parallel load clock for the
PIN[3:0] data.
REFSEL
TTL
I
53
Reference Select. Used to select the reference clock frequency.
A logic Low selects 38.88 or 34.816 MHz reference, and logic High
selects 19.44 or 17.408 MHz.
SERDSEL
TTL
I
96
Serial Data Select. Active High. Used to select the Transmit Serial
Data inputs (TSDATIP/N) and enable the Receiver Serial Data
outputs (RSDATOP/N). In this mode the POUT[3:0] outputs are
held Low. When SERDSEL is held at logic Low, the parallel inputs
PIN[3:0] are selected and the the parallel outputs POUT[3:0] are
enabled.
DLEB
TTL
I
85
Diagnosatic Loopback Enable. Active High. Selects diagnostic
loopback. When DLEB is Low, the S3031B receiver section uses
the RSDATIP/N or ANDATIN data inputs. When High, the S3031B
receiver section uses the data from the transmitter section output.
LLEB
TTL
I
84
Line Loopback Enable. Active High. Selects Line Loopback. When
LLEB is High the S3031B will route the data from the selected
RSDATIP/N or ANDATIN inputs directly to the TSDATOP/N or
XFRMDRVA/B outputs as selected.
TESTCLK
TTL
I
28
Test Clock. Used during device testing to bypass the VCO of the
PLLs.
TXCRVEE
TSVEE
AVEE1
AVEE0
AVEE4
AVEE5
AVEE6
AVEE7
RXCRVEE
AVEE2
AVEE3
RSVEE
RXIOVEE
TXIOVEE
TXINVEE
GND
14
5
14
19
24
32
37, 38
39
50
54
57
62
64
76
90
2
Description
Ground 0V
August 19, 1999 / Revision D
E4/STM-1/OC-3 ATM TRANSCEIVER
S3031B
Table 6. Common Pin Assignment and Description (Continued)
Pin Name
Level
I/O
Pin #
Description
Power Supply (5V)
TXCRVCC
TSVCC
AVCC1
AVCC0
AVCC4
AVCC5
AVCC6
AVCC7
RXCRVCC
AVCC2
AVCC3
RSVCC
RXIOVCC
TXIOVCC
TXINVCC
VCC
4
11
18
25
29
34, 35
43
47
55
56
63
67
77
87
3
REFGND
GND
7
Ground (0V)
GND
GND
17
45
70
83
Gound (0V)
CGND
GND
20
23
58
61
Ground (0V)
40
41
42
Not Connected.
NC
August 19, 1999 / Revision D
15
S3031B
E4/STM-1/OC-3 ATM TRANSCEIVER
Figure 13. 100-Pin PQFP/TEP Package
SIDE VIEW
TOP VIEW
Thermal Management
Device
Power
Θja Still Air
w/DW0045-28
S3031
1.92W
19˚C/W
Max Still Air1
w/DW0045-28
85˚C
1. Max ambient temperature permitted in still air to maintain Tj < 130˚C.
16
August 19, 1999 / Revision D
E4/STM-1/OC-3 ATM TRANSCEIVER
S3031B
Figure 14. Heat Sink Drawing DW0045-28
August 19, 1999 / Revision D
17
S3031B
E4/STM-1/OC-3 ATM TRANSCEIVER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
S3031B
100 PQFP/TEP
TOP VIEW
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
POUT2
POUT3
POCLK
RXIOVCC
RXIOVEE
RXRSTB
LOSOUT
LCV
RSCLKOP
RSCLKON
GND
RSDATOP
RSDATON
RSVCC
RSDATIP
RSDATIN
RSVEE
AVCC3
AVEE3
CGND
CAP3
CAP4
CGND
AVEE2
AVCC2
RXCRVCC
RXCRVEE
REFSEL
LOSOPT
EQUALSEL
BUFINB
AVEE4
BUFOUT
AVCC5
AVCC5
GIN
AVEE5
AVEE5
AVEE6
NC
NC
NC
AVCC6
GOUT
GND
ANDATIN
AVCC7
LOSIN
LOSREF
AVEE7
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PIN3
TXINVEE
TXINVCC
TXCRVCC
TXCRVEE
REFCLK
REFGND
SERDATEN
TSCLKOP
TSCLKON
TSVCC
TSDATOP
TSDATON
TSVEE
TSDATIP
TSDATIN
GND
AVCC1
AVEE1
CGND
CAP1
CAP2
CGND
AVEE0
AVCC0
TSTCLKEN
CMISEL
TESTCLK
AVCC4
BUFINA
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
PIN2
PIN1
PIN0
TXRSTB
SERDSEL
TREFCLKOUT
XFRMENB
XFRMSTATA
XFRMENA
XFRMSTATB
TXIOVEE
XFRMDRVA
XFRMDRVB
TXIOVCC
DLCV
DLEB
LLEB
GND
POUT0
POUT1
Figure 15. S3031B Pinout
18
August 19, 1999 / Revision D
E4/STM-1/OC-3 ATM TRANSCEIVER
S3031B
Table 7. S3031B Clock Recovery Mode Performance Specifications
Parameter
Min
Typ
Max
Units
Nominal VCO
Center Frequency
622.08
MHz
OC–3/STS–3
+8, -12
%
Acquisition Lock Time1
Reference Clock
Input Duty Cycle
Reference Clock Rise &
Fall Times
PECL Output Rise & Fall
Times
Reference Clock
Frequency Tolerance
tPSER
RSCLKOP Falling to
RSDATO Valid Prop Delay
Condition
Given REFCLK = VCO ÷ 32
With respect to fixed reference
frequency.
With device already powered up
and valid REFCLK.
64
µsec
70
% of UI
5.0
ns
20% to 80% of amplitude.
850
ps
20% to 80%, 50Ω load,
5 pF cap.
-100
100
pp m
100
1000
ps
30
See Figure 11.
1. Specification based on design values. Not tested.
Table 8. S3031B Clock Synthesis Mode Performance Specifications
Parameter
Min
Typ
Max
Units
In CSU mode, Given
PECL Data Output Jitter
(RSDATOP/N)
OC-3/STS-3
64
ps (rms)
E4-STS-3 CMI
Reference Clock
Frequency Tolerance
Clock Synthesis
Condition
• 28 ps rms jitter on REFCLK in
12kHz to 1MHz band
32
-20
+20
• 56 ps rms jitter on REFCLK in
12kHz to 1MHz band
ppm
Required to meet SONET output
jitter generation specification.
Units
Condition
Table 9. Electrical Characteristics for Transformer Driver1
(VCC = +5V, TA = +25°C, input AC coupled unless otherwise noted.)
Parameter
Operating Frequency
VSWR
2
Min
Typ
Max
155.52
1.3:1
MHz
1.5:1
270Ω 11 3pF load.
75Ω AC Coupled Termination.
1. For output waveform characteristics, see Figures 7 and 8. The S3031B is compliant with these masks on an individual waveform basis. The
total cycle-to-cycle wideband jitter is less than 350 ps peak-to-peak. Total transmitted jitter per ITU G.825 is less than 0.075 UI peak-to-peak.
2. Up to 250 MHz.
August 19, 1999 / Revision D
19
S3031B
E4/STM-1/OC-3 ATM TRANSCEIVER
Table 10. Electrical Characteristics for ANDATIN Input
(VCC = +5V, TA = +25°C, input AC coupled unless otherwise noted.)
Parameter
Symbol
Peak-to-Peak Input Voltage
Range
Common-Mode Rejection
Ratio
Min
Typ
Viptp
Power-Supply Rejection Ratio
Input Sensitivity
Max
Units
1.3
V
CMRR1
40
dB
PSRR1
40
dB
SIN
110
mV
Vcc
-1V
DC Offset at Input 2
Conditions
TA = Min to Max
V
1. Up to 300 kHz.
2. Signal is undefined if left floating.
Table 11. Electrical Characteristics for LOSIN Input
(VCC = +5V, TA = +25°C, input AC coupled unless otherwise noted.)
Parameter
Symbol
Peak-to-Peak Input Voltage
Range
Common-Mode Rejection
Ratio
Min
Typ
Viptp
CMRR1
Power-Supply Rejection Ratio
Max
Units
1.1
V
40
PSRR1
dB
35
dB
LOSLOSLOSREF/30 REF/20 REF/10
LOSLOSLOSREF/15 REF/10 REF/5
Signal Level for LOS
Detected3
Signal Level for LOS Cleared3
Hysterisis between "Trans.
Cond." and "No Trans. Cond."2
4
Conditions
6
V/V
TA = Min to Max
V/V
TA = Min to Max
dB
1. Up to 300 kHz.
2. LOSREF >0.5 volts.
3. LOS detected and LOS cleared will maintain 2:1 ratio ±5%.
Table 12. Typical Operating Conditions
Voltage Applied at
LOSREF
20
Compare Voltage #1
Compare Voltage #2
Hysterisis
1.4 Volts
140 mV ± 0.6dB
70 mV ± 1dB
6dB +1.6 -1.4dB
0.7 Volts
70 mV ± 1dB
35 mV ± 1.6dB
6dB +2.7 -2.0dB
0.3 Volts
30 mV ± 1.6dB
15 mV ± 3.5dB
6dB +6.0 -3.7dB
August 19, 1999 / Revision D
E4/STM-1/OC-3 ATM TRANSCEIVER
S3031B
Table 13. Electrical Characteristics for BUFIN, BUFOUT
(At VCC = +5VDC, RLOAD = 75Ω AC coupled and TA = 25˚C unless otherwise noted.)
Parameter
Symbol
Output Characteristics
(BUFOUT)
Voltage Output:
Output Resistance:
Transfer Characteristics
Gain (BUFIN to BUFOUT)1
VSWR2
Min
Typ
Max
Units
±0.6
1
±0.8
3
8
V
Ω
0.85
0.93
1.1
V/V
1.3:1
1.5:1
VSWR
With 75Ω AC Coupled termination
40
35
30
dBc
DC Input Bias
Vcc -0.85
V
Input externally AC Coupled
DC Output Bias
Vcc -2.5
V
Output externally AC Coupled
Harmonic Distortion2
35
30
25
Conditions
HD
Input = 0.3V p-p
Input = 0.6V p-p
Input = 1.2V p-p
1. Up to 300 MHz.
2. Up to 250 MHz.
Table 14. Absolute Maximum Ratings
Parameter
Min
Typ
Max
Units
Storage Temperature
-65
150
˚C
Voltage on VCC with respect to Ground
-0.5
+7.0
V
Voltage on any TTL Input Pin
-0.5
+5.5
V
Voltage on any PECL Input Pin
Vcc
-3
Vcc
V
TTL Output Sink Current
20
mA
TTL Output Source Current
10
mA
High Speed PECL Output Source Current
50
mA
Static Discharge Voltage1
500
V
1. Human body model.
Table 15. Recommended Operating Conditions
Parameter
Min
Typ
Max
Units
Ambient Temperature Under Bias
-20
85
˚C
Junction Temperature Under Bias
-10
+130
˚C
Voltage on any VCC with respect to Ground
4.75
5.25
V
0
VCC
V
VCC
-2
VCC
V
365
mA
Voltage on any TTL Input Pin
Voltage on any PECL Input Pin
S3031B ICC
August 19, 1999 / Revision D
5.0
336
21
S3031B
E4/STM-1/OC-3 ATM TRANSCEIVER
Table 16. TTL Input/Output DC Characteristics
(TA = -20°C to +85°C, VCC = 5 V ±5%)
Parameter
Symbol
Min
Typ
Max
Units
Conditions
0.8
V
Guaranteed Input Low Voltage
Input Low Voltage
VIL1
Input High Voltage
VIH1
2.0
V
Guaranteed Input High Voltage
Input Low Current
IIL
-400.0
µA
VCC = MAX, VIN = 0.5 V
Input High Current
IIH
50.0
µA
VCC = MAX, VIN = 2.7 V
Input High Current at max VCC
II
1.0
mA
VCC = MAX, VIN = 5.5 V
-25.0
mA
VCC = MAX, VOUT = 0.5 V
V
VCC = MIN, IIN = -18 mA
V
VCC = MIN, IOL = 4 mA
V
VCC = MIN, IOH = -1 mA
Output Short Circuit Current
IOS
-100.0
Input Clamp Diode Voltage
VIK
-1.2
Output Low Voltage
VOL
Output High Voltage
VOH
0.5
2.7
1. These input levels provide zero noise immunity and should only be tested in a static, noise-free environment.
Table 17. PECL Input/Output DC Characteristics1,2
(TA = -20°C to +85°C, VCC = 5 V ±5%)
Parameter
Symbol
Min
Input Low Voltage
VIL
Input High Voltage
VIH
Input Low Voltage
VIL
Input High Voltage
VIH
VCC
-2.000
VCC
-1.225
VCC
-2.000
VCC
-1.750
Input Differential Voltage
VID
0.250
Input High Current
IIH
Input Low Current
IIL
Typ
Max
VCC
-1.441
VCC
-0.570
VCC
-0.700
VCC
-0.450
V
V
V
V
Conditions
Guaranteed Input Low Voltage for
single-ended inputs
Guaranteed Input High Voltage
for single-ended inputs
Guaranteed Input Low Voltage for
differential inputs
Guaranteed Input High Voltage
for differential inputs
1.400
V
Differential Input Voltage
-0.500
20.000
µA
VID = 500 mV
-0.500
20.000
µA
VID = 500 mV
VCC
-1.500
VCC
-0.670
V
50 Ω termination to VCC -2V
V
50 Ω termination to VCC -2V
1.330
V
Differential Output Voltage
Output Low Voltage
VOL
Output High Voltage
VOH
VCC
-2.000
VCC
-1.110
Output Differential Voltage
VOD
0.390
0.500
Units
1. These conditions will be met with no airflow.
2. When not used, tie the positive differential PECL pin to VCC and the negative
differential ECL pin to ground via a 3.9 kΩ resistor.
22
August 19, 1999 / Revision D
E4/STM-1/OC-3 ATM TRANSCEIVER
S3031B
Figure 16. Differential ECL Input Application
Zo=50Ω
Fiber Optic
Receiver
RSDATIP
100Ω
330Ω
330Ω
RSDATIN
Zo=50Ω
ECL driver to
RSDATIP/N input
Figure 17. S3031B Differential ECL Output Application
TSDATOP
Zo=50Ω
TSDATON
330Ω
330Ω
Electrical
to
Optical
100Ω
Zo=50Ω
Figure 18. Loop Filter Capacitor Connections
R
51Ω
CAP1
CAP3
CAP2
CAP4
1.0µF
1.0µF
R
51Ω
Note: R = 100Ω for serial mode, and R = 1000Ω for nibble mode.
August 19, 1999 / Revision D
23
S3031B
E4/STM-1/OC-3 ATM TRANSCEIVER
Figure 19. S3031B Transformer Input and Output Application
0.01 µF 30Ω
0.01 µF 30Ω
24Ω
24Ω
CABLE OUT
MONITOR OUT
10 kΩ
XFRMDRVB
XFRMDRVA
10 kΩ
220Ω
220Ω
0.01µF
LOSREF
LOSIN
ANDATIN
GOUT
GIN
BUFOUT
BUFINB
BUFINA
AMCC
S3031B
C1
0.01µF
100Ω
0.01µF
75pF
0Ω
0.01µF
VCC
430Ω
12pF
300Ω
24pF
RX
0.4V
INPUT
30Ω
75Ω
T
MMBD352
VCC
2.2 kΩ
910Ω
100pF
24
0.01µF
0.01µF
2.2 kΩ
100pF
August 19, 1999 / Revision D
E4/STM-1/OC-3 ATM TRANSCEIVER
S3031B
Figure 20. OC-3 Application
19.44 MHz
155.52 MHZ
TX_CLK_+/–
TSCLKOP/N
S3031B
SUNI
IGT
SYN155
REFCLK
155.52 MHZ
RX_CLK_+/–
RSCLKOP/N
RSDATOP/N
RX_DATA_+/–
LOSOPT
RSDATIP/N
O/E
E/O
TX_DATA_+/–
Figure 21. STM-1 CMI, E4 Application
19.44 MHz
REFCKIN
TX_DATA_+/–
TSDATIP/N
XFRMDRVA
Cable
Output
XFRMDRVB
Monitor
Output
SUNI-LITE
SUNI-PLUS
SABRE
S3031B
REFCLK
RX_CLK_+/–
RSCLKOP/N
RX_DATA_+/–
RSDATOP/N
BUFIN
BUFOUT
Cable
Input
Equalizer
ANDATIN
+5V
EQUALSEL
LOSIN
LOSREF
LOSIN
Compensator
0.01µF
August 19, 1999 / Revision D
25
S3031B
E4/STM-1/OC-3 ATM TRANSCEIVER
Table 18. Suggested Interface Devices
Processor Interface
PMC PM5345
SUNI
Saturn User Network Interface
PMC PM5346
SUNI-Lite
Saturn User Network Interface
PMC PM5347
SUNI-Plus
IGT WAC-013-A
Saturn User Network Interface
SONET LAN ATM Processor
TRANSWITCH SYN155
155 Mbps Synchronizer
TI SABRE TDC 1500
155 Mbps Processor
Electrical Interface
Motorola
MMBD352
Dual Diode
Mini-Circuits
MCL TXI-R5
Wideband RF Transformer (Surface Mount)
Mini-Circuits
MCL TO-75
Wideband RF Transformer (Through-Hole)
Optical Interface
HP HFBR-520x
155 Mbps
Fiber Optic Transceiver
CTS ODL-1408X
155 Mbps
Fiber Optic Transceiver
Sumitomo SDM4123-XC
155 Mbps
Fiber Optic Transceiver
AMP 269039-1
155 Mbps
Fiber Optic Transceiver
Ordering Information
3031
PACKAGE
B – 100 PQFP/TEP
w/DW0045-28 heatsink unattached
X
XXXX
/
Package
H0 – No Heatsink
XX
H0 for no heatsink (identifier not marked on part)
O 900
CE
RT
1
IS
Grade Part number
X
OPTION
D
S – industrial
RECEIVER
E
GRADE
IFI
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http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
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AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright ® 1999 Applied Micro Circuits Corporation
26
August 19, 1999 / Revision D