AMI X2P998

XPressArray-II 0.15mm Structured ASIC
Data Sheet
1.0 Key Features
• Next-generation 0.15mm hybrid structured ASIC
• Initializable distributed memory at speeds up to 210MHz
• Platform for high-performance 1.5V/1.2V ASICs and FPGAto-ASIC conversions
• Configurable signal, core and I/O power supply pin locations
• Supports LVTTL, LVCMOS, PCI33, PCI66, PCI-X 133, PCI-X
2.0, GTL/+, HSTL class 1, 2, 3, and 4, SSTL2 class 1 and 2,
LVPECL (input), LVDS I/O standards
• NRE and production cost savings
• Significant time-to-market advantages
• Drop-in replacement for cost-reducing Xilinx® Virtex-II and
Virtex-II Pro and Altera® APEX-II and Stratix designs
• 1.5V, 1.8V, 2.5V, and 3.3V capable I/O
• 417K to 3.9M ASIC gates
• Digital controlled impedance
• 210MHz system, 500MHz local clock speeds
• Built-in DDR support
• Low power consumption (0.055mW/MHz/gate @ 1.575V)
• LVDS data rates to 1Gbps
• 332Kbits to 4.8Mbits of block RAM memory
• Up to 1346 user I/Os
• Up to 5.6Mbits of memory when 50 percent of the logic sites
are used for distributed memory
• Comprehensive clock management circuitry
• 18Kbit initializable dual-port RAM blocks at speeds up to
330MHz
• Variety of package options
• True 3.3V tolerance with no external resistor necessary
• Up to eight DLLs and eight PLLs
• Integrated high-fault coverage scan-test, memory BIST and
JTAG
• Flexible I/O technology, any I/O standard assigned to any I/O
pin
2.0 Product Description
increases to 5.6Mbits of memory with the addition of
distributed configurable memory, assuming 50 percent of the
logic sites are used for memory. Individual memories may
be configured as single or dual port with asymmetrical port widths.
The architecture also supports memory initialization.
Targeted at medium-density, high-speed, 1.5V and 1.2V ASIC
applications and high-density FPGA-to-ASIC conversions, the
XPressArray™-II 0.15mm hybrid structured ASIC is an
innovative next-generation technology platform that reduces
time-to-market for system-on-chip (SoC) applications while
delivering significant NRE and unit cost savings.
Flexible I/O technology includes support for a comprehensive
array of common standards and compatibility with 1.5V, 1.8V,
2.5V, and 3.3V I/O schemes. I/O power supply banking
supports the operating voltage requirements of multiple I/O
standards on the same device. Each XPressArray-II I/O may
be configured to support LVTTL, LVCMOS, PCI33, PCI66,
PCI-X 133, PCI-X 2.0, GTL/+, HSTL class 1, 2, 3, and 4,
SSTL2 class 1 and 2, LVPECL input, and LVDS. I/Os support
digital controlled impedance (DCI) on-chip termination. Dual
data rate (DDR) support for high-speed memory interface is
built in.
XPressArray-II offers a true drop-in replacement for Xilinx
Virtex-II, Virtex-II Pro, Altera APEX-II, and Stratix FPGAs,
making it the industry's lowest cost ASIC conversion solution.
The result is a simplified route to cost reductions for OEMs
looking to combine the flexibility of FPGA prototyping with a
path to an ASIC for final production.
Table 1 shows the seven bases of the AMIS XPressArray-II
family. These bases offer between 417K and 3.9M gates.
Configurable memory ranges from 332Kbits to 4.8Mbits, which
Table 1: XPressArray-II 0.15mm Hybrid Structured ASIC Family
XPressArray-II Base
X2P376
X2P528
X2P680
X2P846
X2P998
X2P1148
X2P1346
18K RAM Blocks
18
40
57
101
145
189
264
No Distributed RAM
Bits(K)1
Gates(K)2
332
417
737
650
1051
1203
1862
1629
2673
2196
3484
2902
4866
3929
50% Distributed RAM
Bits(K)1
Gates(K)2
415
209
867
325
1291
602
2188
815
3112
1098
4064
1451
5652
1965
(1) Usable 2RW RAM bits
(2) Usable 2-NAND equivalent logic gates
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1
DLL
2
2
4
4
4
8
8
PLL
4
4
4
4
4
8
8
User I/Os
376
528
680
846
998
1148
1346
XPressArray-II 0.15mm Structured ASIC
Data Sheet
Package offerings include traditional plastic BGA and flip-chip
BGA in 1.00mm and 1.27mm pitches. Because XPressArrayII devices consume significantly less power than equivalent
FPGAs, lower cost plastic packaging can be used in most
cases. Table 2 shows the supported package configurations.
Packaging options exist to optimize individual conversions.
Comprehensive clock management circuitry features up to
eight all digital delay-locked loops (DLLs) and a maximum of
eight phase-locked loops (PLLs). High fault coverage is
provided through integrated scan-test, memory BIST and
JTAG support.
Table 2: XPressArray-II Package Options
Pins
256 FBGA
456 FBGA
484 FBGA
575 PBGA
672 FBGA
672 PBGA
672 FFBGA
676 FBGA
724 PBGA
728 PBGA
780 FBGA
896 FFBGA
956 PBGA
957 BFBGA
1020 FBGA
1148 FFBGA
1152 FFBGA
1508 FBGA
1517 FFBGA
1696 FFBGA
1704 FFBGA
Description
256 Fine Pitch Ball Grid Array
456 Fine Pitch Ball Grid Array
484 Fine Pitch Ball Grid Array
575 Standard Ball Grid Array
672 Fine Pitch Ball Grid Array
672 Standard Ball Grid Array
672 Flip-Chip Fine Pitch Ball Grid Array
676 Fine Pitch Ball Grid Array
724 Standard Ball Grid Array
728 Standard Ball Grid Array
780 Fine Pitch Ball Grid Array
896 Flip-Chip Fine Pitch Ball Grid Array
956 Standard Ball Grid Array
957 Flip-Chip Standard Pitch Ball Grid Array
1020 Fine Pitch Ball Grid Array
1148 Flip-Chip Fine Pitch Ball Grid Array
1152 Flip-Chip Fine Pitch Ball Grid Array
1508 Fine Pitch Ball Grid Array
1517 Flip-Chip Fine Pitch Ball Grid Array
1696 Flip-Chip Fine Pitch Ball Grid Array
1704 Flip-Chip Fine Pitch Ball Grid Array
Pitch (mm)
1.0
1.0
1.0
1.27
1.0
1.27
1.0
1.0
1.27
1.27
1.0
1.0
1.27
1.27
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Size (mm)
17x17
23x23
23x23
31x31
27x27
35x35
27x27
27x27
35x35
35x35
29x29
31x31
40x40
40x40
33x33
35x35
35x35
40x40
40x40
42.5x42.5
42.5x42.5
Max I/Os
187
344
369
423
521
514
459
500
564
531
675
639
747
699
859
819
839
1267
1123
1179
1131
commercial synthesizers allows conversion of FPGA designs
to an ASIC by simply re-targeting from an FPGA library to an
XPressArray-II library.
For FPGA conversions, rapid access to XPressArray-II
technology can be achieved via AMI Semiconductor's
NETRANS® conversion methodology. Alternatively, the
availability of XPressArray-II synthesis libraries for leading
3.0 The Advantages of XPressArray-II
reductions in terms of both NRE and unit cost through
manufacturing utilizing structured ASIC technology.
XPressArray-II technology is ideal for medium density ASIC
applications requiring high-performance and low power, with
1.5V/1.2V operation. XPressArray-II devices are fabricated
using a hybrid technology that integrates an established
0.15mm front-end process with a proven AMIS metal finishing
technology, which is used to produce a customized back-end.
The 0.15mm processing steps are common to multiple
applications, reducing costs by allowing existing tooling to be
utilized. At the same time, tooling and manufacturing costs are
significantly lower for the metal finishing process than for
traditional 0.15mm cell based processes. The result is that
XPressArray-II delivers reduced cycle times and significant
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The XPressArray-II architecture offers a unique solution to the
challenges of maintaining FPGA process compatibility while
delivering ASIC technology with reasonable NREs and low
piece price. Compared to equivalent FPGAs, XPressArray-II
devices operate at the same voltage, offer higher densities,
better performance and consume less power. Figure 1
compares volume pricing for FPGA, cell-based ASIC and
XPressArray-II devices. Figure 2 compares power
consumption of these devices.
2
Average ASP (with NRE)
XPressArray-II 0.15mm Structured ASIC
Data Sheet
$500
$400
XPressArray-II
$300
0.15mm SC
$200
XC2V1000
$100
$0
5K
1K
10K
25K
50K
100K
250K
Cost Volume Tradeoffs
Figure 1: Price vs. Volume (Amortized NRE)
50
0.13mm FPGA
Power
40
30
1M Gates: 12.5% Switching
2M Bits:
100% Switching
Vcc =
1.5V
20
XPressArray-II
10
0.15mm Standard Cell
0
0
100
200
300 MHz
Frequency
Figure 2: XPressArray Power Consumption
management, and frequency synthesis circuits round out the
offering. XPressArray-II devices can be fabricated as pin-forpin compatible FPGA drop-in replacements. Alternatively,
multiple FPGAs can be combined into one XPressArray-II
device, or die and package configurations can be optimized for
specific requirements.
XPressArray-II provides a FPGA conversion platform
combining advanced process capability with all of the key
features of the Xilinx Virtex-II and Virtex-II Pro and Altera
APEX-II and Stratix devices. Support for a comprehensive
array of I/O standards, abundant configurable memory, highdensity logic and advanced high-performance clock
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XPressArray-II 0.15mm Structured ASIC
Data Sheet
4.0 XPressArray-II Architecture
support for a full compliment of I/O standards.
Figure 3 shows the XPressArray-II device architecture with
embedded block RAMs, DCI, DDR support, DLLs, PLLs, and
I/Os
DCI
DCI
DDR
DLL
DLL
BRAM
I/Os
BRAM
DDR
Core
Core
PLL
PLL
DDR
BRAM
I/Os
BRAM
BRAM
DLL
DLL
DDR
DCI
DCI
I/Os
Figure 3: XPressArray-II Architecture
5.0 I/O Description
latch to limit noise on tri-stated signal busses. Dedicated dualdata rate (DDR) flip-flops facilitate high-speed communications
with I/O operating at up to 1Gbps using LVDS transceivers in
conjunction with DLL/PLL clock management circuits.
The XPressArray-II I/O ring is composed of uniform I/O cell sites
and each site may be customized to support any I/O standard.
The I/O power ring is divided into eight segments, making it
compatible with the FPGA products and power supply rings built
into the packages.
Digital controlled impedance is available on many I/O standards
to eliminate off-chip termination resistors. Figure 5 illustrates the
termination schemes available on all XPressArray-II I/O cells.
I/O cells are available for a wide variety of standards as listed in
Table 3. I/O cells operate at 1.5V, 1.8V, 2.5V, and 3.3V. 3.3V
tolerant I/Os are also available. Differential signaling standards
typically require two pad sites. Signaling standards requiring a
reference voltage typically share a common reference voltage
within an I/O power ring segment, with the reference voltage
being supplied through an I/O site from an off-chip source.
Designers can use the DDR and DCI features of the
XPressArray-II I/O cell for DDR SDRAM memory and parallel
high-speed point-to-point interfaces.
Figure 4 shows the architecture of the I/O cell. Included are
programmable pull-up, pull-down resistors as well as a bus-hold
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XPressArray-II 0.15mm Structured ASIC
Data Sheet
Table 3: Supported I/O Standards
I/O Standard
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
PCI66
PCI-X 133
PCI-X 2.0 Mode 1
PCI-X 2.0 Mode 2
GTL
GTL+
SSTL2 Class I
SSTL2 Class II
HSTL18 Class I
HSTL18 Class II
HSTL18 Class III
HSTL18 Class IV
HSTL15 Class I
HSTL15 Class II
HSTL15 Class III
HSTL15 Class IV
LVPECL (input)
LVDS33
LVDS25
VCCO
3.3V
3.3V
2.5V
1.8V
1.5V
3.3V
3.3V
3.3V
3.3V
1.5V
N/A
N/A
2.5V
2.5V
1.8V
1.8V
1.8V
1.8V
1.5V
1.5V
1.5V
1.5V
3.3V
3.3V
2.5V
VCCAUX
Output Termination
DCI Series Out 25W/50W
DCI Series Out 25W/50W
DCI Series Out 25W/50W
DCI Series Out 25W/50W
DCI Series Out 25W/50W
Input Termination
DCI Split Parallel in 114W
3.3V
DCI
DCI
DCI
DCI
Parallel
Parallel
Parallel
Parallel
Out
Out
Out
Out
50W
50W
25W
25W
DCI Split Parallel in 100W
DCI Split Parallel in 100W
DCI Split Parallel in 100W
DCI Split Parallel in 100W
DCI Parallel in 50W
DCI Parallel in 50W
DCI Split Parallel in 100W
DCI Split Parallel in 100W
DCI Parallel in 50W
DCI Parallel in 50W
100W Differential Input
100W Differential Input
100W Differential Input
3.3V
3.3V
Performance
125MHz
125MHz
125MHz
125MHz
125MHz
33MHz
66MHz
133MHz
133MHz
266/533Mbps
100MHz
200MHz
400Mbps
400Mbps
500Mbps
500Mbps
500Mbps
500Mbps
500Mbps
500Mbps
500Mbps
500Mbps
1Gbps
1Gbps
1Gbps
Notes
2-24mA
2-24mA
2-24mA, 3.3V Tolerant
2-16mA, 3.3V Tolerant
2-16mA, 3.3V Tolerant
Input DDR Block
VREF
Register
IN
VCC
Register
PullUp
Latch
OEN DDR Block
Bus
Hold
IN_DLY
Register
0
MUX
1
OEN
PAD
Register
ESD
DCI_CNTL
DCI
Output DDR Block
PullDn
Register
0
MUX
1
GND
OUT
Register
Figure 4: Dual Data Rate (DDR) I/O Architecture
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XPressArray-II 0.15mm Structured ASIC
Data Sheet
VCC
R=Z0
R=Z0
External
Termination
VCC/2
R=2Z0
R=Z0 or Z0/2
VCC
R=Z0 or Z0/2
Internal
Termination
R=Z0
VCC
R=2Z0
R=2Z0
Parallel
Termination
Series
Termination
Split
Parallel
Figure 5: Digital Controlled Impedence Termination Modes
6.0 Memory Description
The XPressArray-II logic fabric is specifically designed to
support distributed memories to replace FPGA memories
created from LUTs. Pre-designed distributed memories are
available in a range of sizes from 16x1 through 32x32 in 2-port
(1R1W) configurations as shown in Table 5. Additional sizes
and configurations, such as 2-read, 1-write (2R1W)
configurations can also be constructed. Fully synchronous
and synchronous-write, asynchronous read modes are
available. Like the block RAM, each bit is initializable by a late
metal mask option.
The XPressArray-II architecture supports abundant embedded
block RAM as well as distributed RAM constructed from the
structured ASIC logic fabric.
The XPressArray-II 18K embedded dual-port memory block
provides drop-in replacement features for FPGA memories.
Each memory is individually port configurable as 512x36,
1024x18, 2048x9, 4096x4, 8192x2, and 16384x1 as shown in
Table 4. This fully synchronous memory supports read before
write, write before read and write without read operational
modes. XPressArray-II embedded RAM blocks may be
configured as single-port (1RW), 2-port (1R1W) or true dualport (2RW). Each RAM bit is initializable by a late metal mask
option.
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XPressArray-II 0.15mm Structured ASIC
Table 5: Predefined Distributed RAMs
Table 4: Block RAM Configurations
Name
Depth
ra16_1_1_c
ra16_1_2_c
ra16_1_4_c
ra16_1_9_c
ra16_1_18_c
ra16_1_36_c
ra16_2_2_c
ra16_2_4_c
ra16_2_9_c
ra16_2_18_c
ra16_2_36_c
ra16_4_4_c
ra16_4_9_c
ra16_4_18_c
ra16_4_36_c
ra16_9_9_c
ra16_9_18_c
ra16_9_36_c
ra16_18_18_c
ra16_18_36_c
ra16_36_36_c
16,384
16,384
16,384
16,384
16,384
16,384
8,192
8,192
8,192
8,192
8,192
4,096
4,096
4,096
4,096
2,048
2,048
2,048
1,024
1,024
512
Port A
Data Parity
Width Width
1
N/A
1
N/A
1
N/A
1
N/A
1
N/A
1
N/A
2
N/A
2
N/A
2
N/A
2
N/A
2
N/A
4
N/A
4
N/A
4
N/A
4
N/A
8
1
8
1
8
1
16
2
16
2
32
4
Data Sheet
Port B
Depth
16,384
8,192
4,096
2,048
1,024
512
8,192
4,096
2,048
1,024
512
4,096
2,048
1,024
512
2,048
1,024
512
2,048
1,024
512
Name
xram16x1pc
xram16x2pc
xram16x4pc
xram16x8pc
xram16x10pc
xram16x16pc
xram16x18pc
xram16x32pc
xram32x1pc
xram32x2pc
xram32x4pc
xram32x8pc
xram32x10pc
xram32x16pc
xram32x18pc
xram32x32pc
Parity
Width
Width
1
N/A
2
N/A
4
N/A
8
1
16
2
32
4
2
N/A
4
N/A
8
1
16
2
32
4
4
N/A
8
1
16
2
32
4
8
1
16
2
32
4
8
2
16
4
32
4
Depth
16
16
16
16
16
16
16
16
32
32
32
32
32
32
32
32
Width
1
2
4
8
10
16
18
32
1
2
4
8
10
16
18
32
7.0 Delay-Locked Loop (DLL) Description
perform basic clock frequency synthesis and generate phase
shifts. The DLL provides both coarse and fine-grained phase
shifting with dynamic phase shift control. The quadrature clock
generation features deliver accurate clock phases at the load,
compensating for clock tree delays across the full range of
temperature and voltage. In clock divider and clock doubling
applications, duty cycle correction is available. A robust realtime lock detection circuit completes the DLL.
XPressArray-II devices employ clock tree synthesis, enabling
an unlimited number of clock and reset signals to be routed.
Synthesized clock trees deliver high speed clock signals with
minimal skew and power.
The XPressArray-II DLL (Figure 6) is an all digital clock
management function embedded into the XPressArray-II
bases. DLLs may be used to minimize clock insertion delay,
CLKREF
CLK360
Delay Line
FB360
CLK270
PD
Control
Clk Tree
Clk Tree
FB270
CLK180
Clk Tree
FB180
CLK90
FB90
CLKDV
CLK2X
DLL
Figure 6: DLL
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Clk Tree
XPressArray-II 0.15mm Structured ASIC
Data Sheet
8.0 Phased-Locked Loop (PLL) Description
in Figure 8, the PLL performs classical "M over N" frequency
synthesis application. When the output frequency is an integer
multiple or division of the input frequency precise phase control
allows fine adjustment of the phase relationship of the output
to the input. In this example, locations B and C are phase
controlled with respect to A. The phase relationship of A and D
is inferred.
PLLs are embedded into the XPressArray-II bases to perform
advanced clock frequency synthesis operations, minimize
clock insertion delay and generate phase taps. Each PLL can
be configured as a general purpose or LVDS PLL.
Figure 7 shows the general purpose PLL configuration. All
dividers have a range of 1 to 2049. In normal mode, as shown
REFCLK
+N
+A
FOUTA
+B
FOUTB
Phase
Shift
Phase
Compare
+M
FBFCLK
General Purpose PLL
LOCK
Figure 7: General Purpose PLL
DFF
PAD
+A
+N
Phase
Shift
Phase
Compare
A
+B
+M
General Purpose PLL
Figure 8: General Purpose PLL in Normal Mode
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D
B
8
C
PAD
XPressArray-II 0.15mm Structured ASIC
Data Sheet
Figure 9 shows the general purpose PLL used in zero delay
mode. This mode supports integer multiply or divide for both
outputs. Locations A and B are phased matched.
DFF
PAD
+A
+N
Phase
Shift
Phase
Compare
A
C
+B
PAD
B
+M
General Purpose PLL
Figure 9: General Purpose PLL in Zero Delay Mode
Figure 10 shows the general purpose PLL used in external
feedback mode. This mode supports integer multiply or divide
for both outputs. Locations A and B are phase matched.
DFF
PAD
+A
+N
Phase
Shift
Phase
Compare
A
C
PAD
+B
+M
General Purpose PLL
PAD B
Figure 10: General Purpose PLL in External Feedback Mode
Figure 11 shows the general purpose PLL used in clock tree
mode. This mode supports integer multiply or divide for both
outputs. Locations A and B are phase matched, C is phase
controlled with respect to D.
DFF
PAD
+A
+N
Phase
Shift
Phase
Compare
A
+B
+M
General Purpose PLL
Figure 11: General Purpose PLL in Clock Tree Mode
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D
C
XPressArray-II 0.15mm Structured ASIC
limited to a range of 1 to 33. The PLL contains integral test
hardware to facilitate silicon testing and in-circuit PLL tuning.
The PLL requires a dedicated power and ground pad pair.
Figure 12 shows the LVDS PLL configuration which supports
high-speed serial I/O applications. The reference divider
supports a range of 1 to 2049 while the feedback divider is
RFFCLK
Data Sheet
+N
FOUT90
FOUT180
FOUT270
FOUT360
Phase
Compare
+M
LVDS PLL
LOCK
Figure 12: LVDS PLL
9.0 RTL Hand-Off Flow
check, synthesize, layout, and achieve timing closure on your
design. Typically if Synplify Pro was used for the FPGA design,
then Synplify ASIC will be used for the ASIC design. Likewise
if FPGA DC was used, then Design Compiler is used for the
ASIC re-synthesis.
XPressArray-II synthesis libraries are available for leading
commercial synthesizers, including Synplicity® Synplify ASIC
and Synopsys® Design Compiler.
With the RTL hand-off flow, you can submit your RTL
description, scripts and timing constraints to AMIS. AMIS will
10.0 NETRANS® Conversion Flow
Inputs to the NETRANS flow include the netlist, test benches
and timing constraints. Over 70 different device types and
netlist formats are supported.
Mapping libraries are fully verified by a process which includes
formal verification of each primitive function.
XPressArray-II devices are fully supported by AMI
Semiconductor's proven NETRANS flow. AMIS has over 19
years experience using NETRANS to convert over 1700 FPGA
and third party ASIC designs to AMIS ASICs.
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XPressArray-II 0.15mm Structured ASIC
Data Sheet
11.0 Electrical Specifications
Table 6: Absolute Maximum Ratings
Symbol
VDD
Parameter
Internal Supply Voltage*
Min.
-0.4
Max.
1.7
Units
V
VCCO
I/O Supply Voltage
3.3V I/O
-0.4
3.7
V
2.5V I/O
-0.4
2.8
V
1.8V I/O
-0.4
2.0
V
1.5V I/O
-0.4
1.7
V
3.3V I/O
-0.4
3.7
V
2.5V I/O
-0.4
2.5
V
VIN, VOUT
DC Input, Output
-0.4
VCCO+0.4
V
TJ
Junction Temperature
-45
130
°C
Min.
1.425
Max.
1.575
Units
V
3.3V I/O
3.135
3.465
V
2.5V I/O
2.375
2.625
V
1.8V I/O
1.710
1.890
V
1.5V I/O
1.425
1.575
V
3.3V I/O
3.135
3.465
V
2.5V I/O
2.375
2.625
V
VIN, VOUT
DC Input, Output
-0.3
VCCO+0.3
V
TJ
Junction Temperature
-40
125
°C
VCCAUX
I/O Auxiliary Supply Voltage
* 1.2V characterization available upon request.
Table 7: Recommended Operating Conditions
Symbol
VDD
Parameter
Internal Supply Voltage*
VCCO
I/O Supply Voltage
VCCAUX
I/O Auxiliary Supply Voltage
* 1.2V characterization available upon request.
Table 8: DC Characteristics
Symbol
Parameter
IDD
Quiescent VDD Supply Voltage
IL
Input or Output Leadage Current
CIN
Input Pad Capacitance
IRPU
Pad Pull-up Current
IRPD
Pad Pull-down Current
AMI Semiconductor - Preliminary
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Min.
-10
Max.
Units
10
mA
10
mA
4
pF
-10
-250
mA
10
250
mA
11
XPressArray-II 0.15mm Structured ASIC
Table 9: DLL Specifications
Parameter
Operating Modes
Low/High Frequency Operation
Control Inputs
Available Outputs
Frequency Range
Clock Doubler Frequency Range
Clock Divider Range
Duty Cycle Correction Resolution
Fine Quadrature Phase Shift Range
Clock Tree Delay Compensation
Output Clock Jitter CLKO (Peak-to-Peak)
Output Clock Jitter CLK90, CLK180, CLK270 (Peak-to-Peak)
Output Clock Jitter CLK2X (Peak-to-Peak)
Output Clock Jitter CLKDV (Integer Division, Peak-to-Peak)
Output Clock Jitter CLKDV (Non-integer Division, Peak-to-Peak)
Output Clock Phase Offset (Between all Quadratures)
Lock Time
Value
• Clock Tree
• Zero Delay Buffer
• External Feedback
• Quadrature Shift
• Basic Frequency Shift
Combined
DCC (Duty Cycle Correction), TIMELOCK
CLK90, CLK180, CLK270, CLK360,
CLKDV, CLK2X, LOCK, VALIDCLK
25-300MHz
50-500MHz
1.6-16 in 0.5 steps, 16-32 in 1.0 steps
45-55%
+/- 64 taps (@ Typical 1 Tap = 70ps)
Yes
+/- 175ps
+/- 250ps
+/- 325ps
+/- 250ps
+/- 400ps
+/- 250ps
180us @ 20MHz
40us @ >60MHz
Table 10: PLL Specifications
Parameter
Operating Modes
Input Frequency Range
Input Duty Cycle
Input Jitter (Peak-to-Peak)
PFD Frequency Range
VCO Frequency Range
Output Frequency Range
Output Duty Cycle
Output Period Jitter (Peak-to-Peak)
Reference Divider
Feedback Divider
Post Dividers
Phase Shift Resolution
Phase Shift Range
Available Outputs
General Purpose Mode
• Normal with Phase Shift
• Zero Delay Buffer
• External Feedback
• Clock Tree
1.5-620MHz
40-60%
2% of input period
1-50MHz
200-500MHz
1-500MHz
45-55%
200ps
1-2049
1-2049
1-2049
1/[Fvco*5]
0-360°
FOUTA, FOUTB
LVDS Mode
• LVDS
1.5-620MHz
40-60%
2% of input period
1-50MHz
200-1000MHz
1-800MHz
45-55%
175ps
1-2049
1-33
N/A
1/[Fvco*5]
0-360°
FOUT90, FOUT180, FOUT270, FOUT360
Electrical specifications subject to change without notice.
AMI Semiconductor - Preliminary
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12
Data Sheet
XPressArray-II 0.15mm Structured ASIC
Data Sheet
12.0 FPGA Cross Reference
Table 11: Altera Stratix Cross Reference
Utilization
FPGA
Part
Package
EP1S10
EP1S10
EP1S10
EP1S10
EP1S20
EP1S20
EP1S20
EP1S20
EP1S25
EP1S25
EP1S25
EP1S25
EP1S30
EP1S30
EP1S30
EP1S40
EP1S40
EP1S40
EP1S40
EP1S60
EP1S60
EP1S60
EP1S80
EP1S80
EP1S80
F484
B672
F672
F780
F484
B672
F672
F780
B672
F672
F780
F1020
F780
B956
F1020
F780
B956
F1020
F1508
B956
F1020
F1508
B956
F1020
F1508
Table 12: Altera APEX-II Cross Reference
I/O
Base
100%
Logic
Base
50%
RAM
Base
100%
RAM
Base
X2P376
X2P528
X2P528
X2P528
X2P376
X2P528
X2P528
X2P680
X2P528
X2P528
X2P680
X2P846
X2P680
X2P846
X2P846
X2P680
X2P846
X2P846
X2P998
X2P846
X2P846
X2P1148
X2P846
X2P998
X2P1346
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P528
X2P528
X2P528
X2P528
X2P528
X2P528
X2P528
X2P680
X2P680
X2P680
X2P528
X2P528
X2P528
X2P528
X2P680
X2P680
X2P680
X2P680
X2P680
X2P680
X2P680
X2P680
X2P846
X2P846
X2P846
X2P846
X2P846
X2P846
X2P846
X2P998
X2P998
X2P998
X2P1346
X2P1346
X2P1346
X2P680
X2P680
X2P680
X2P680
X2P846
X2P846
X2P846
X2P846
X2P846
X2P846
X2P846
X2P846
X2P1148
X2P1148
X2P1148
X2P1148
X2P1148
X2P1148
X2P1148
X2P1346
X2P1346
X2P1346
NONE
NONE
NONE
Table 13: Altera Cyclone-II Cross Reference
FPGA
Part
Package
EP2C8
EP2C20
EP2C20
EP2C35
EP2C35
EP2C50
EP2C50
EP2C70
EP2C70
F256
F256
F484
F484
F672
F672
F896
F672
F896
Utilization
I/O
Base
100%
Logic
Base
50%
RAM
Base
100% RAM
Base
X2P376
X2P376
X2P376
X2P376
X2P528
X2P376
X2P528
X2P528
X2P680
X2P376
X2P376
X2P376
X2P376
X2P376
X2P680
X2P680
X2P680
X2P680
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P528
X2P528
X2P376
X2P376
X2P376
X2P528
X2P528
X2P680
X2P680
X2P846
X2P846
AMI Semiconductor - Preliminary
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13
FPGA
Part
Utilization
I/O
Package
Base
100%
Logic
Base
50%
RAM
Base
100%
RAM
Base
EP2A15
EP2A15
EP2A25
EP2A25
EP2A40
EP2A40
EP2A40
EP2A70
EP2A70
F672
B724
F672
B724
F672
B724
F1020
B724
F1508
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P680
X2P680
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P528
X2P528
X2P528
X2P680
X2P528
X2P680
X2P846
X2P680
X2P1148
XPressArray-II 0.15mm Structured ASIC
Table 14: Xilinx Virtex-II Cross Reference
Table 15: Xilinx Virtex-II Pro Cross Reference
FPGA
Part
Utilization
I/O
Package
Base
100%
Logic
Base
50%
RAM
Base
100%
RAM
Base
XC2V40
XC2V80
XC2V250
XC2V250
XC2V500
XC2V500
XC2V1000
XC2V1000
XC2V1000
XC2V1000
XC2V1500
XC2V1500
XC2V1500
XC2V2000
XC2V2000
XC2V2000
XC2V2000
XC2V3000
XC2V3000
XC2V3000
XC2V3000
XC2V4000
XC2V4000
XC2V4000
XC2V6000
XC2V6000
XC2V6000
XC2V8000
XC2V8000
FG256
FG256
FG256
FG456
FG256
FG456
FG256
FG456
BG575
FF896
BG575
FG676
FF896
BG575
FG676
FF896
BF957
FG676
BG728
BF957
FF1152
BF957
FF1152
FF1517
BF957
FF1152
FF1517
FF1152
FF1517
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P528
X2P528
X2P528
X2P680
X2P680
X2P680
X2P680
X2P680
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P528
X2P528
X2P528
X2P528
X2P528
X2P528
X2P528
X2P528
X2P528
X2P528
X2P528
X2P680
X2P680
X2P680
X2P680
X2P846
X2P846
X2P846
X2P846
X2P846
X2P846
X2P846
X2P846
X2P376
X2P376
X2P528
X2P528
X2P528
X2P528
X2P528
X2P528
X2P528
X2P528
X2P680
X2P680
X2P680
X2P680
X2P680
X2P680
X2P680
X2P846
X2P846
X2P846
X2P846
X2P998
X2P998
X2P998
X2P998
X2P998
X2P998
X2P998
X2P998
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P528
X2P528
X2P528
X2P680
X2P528
X2P528
X2P680
X2P680
X2P528
X2P680
X2P846
X2P846
X2P846
X2P846
X2P998
X2P846
X2P846
X2P1148
X2P846
X2P1148
Data Sheet
Utilization
FPGA
Part
Package
XC2VP2
XC2VP2
XC2VP2
XC2VP4
XC2VP4
XC2VP4
XC2VP7
XC2VP7
XC2VP7
XC2VP20
XC2VP20
XC2VP20
XC2VP30
XC2VP30
XC2VP30
XC2VP40
XC2VP40
XC2VP40
XC2VP50
XC2VP50
XC2VP50
XC2VP70
XC2VP70
XC2VP100
XC2VP105
XC2VP125
XC2VP125
FG256
FG456
FF672
FG256
FG456
FF672
FG456
FF672
FF896
FG676
FF896
FF1152
FG676
FF896
FF1152
FG676
FF1148
FF1152
FF1148
FF1152
FF1517
FF1517
FF1704
FF1696
FF1704
FF1696
FF1704
I/O
Base
100%
Logic
Base
50%
Logic
Base
100%
RAM
Base
X2P376
X2P376
X2P376
X2P376
X2P376
X2P528
X2P376
X2P528
X2P528
X2P528
X2P680
X2P680
X2P528
X2P680
X2P680
X2P528
X2P846
X2P680
X2P846
X2P846
X2P998
X2P998
X2P1148
X2P1346
X2P1148
X2P1346
X2P1148
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P528
X2P528
X2P528
X2P680
X2P680
X2P680
X2P680
X2P680
X2P680
X2P680
X2P680
X2P846
X2P846
X2P998
X2P998
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P528
X2P528
X2P528
X2P680
X2P680
X2P680
X2P846
X2P846
X2P846
X2P846
X2P846
X2P846
X2P998
X2P998
X2P998
X2P1148
X2P1148
X2P1346
X2P1346
None
None
X2P376
X2P376
X2P376
X2P528
X2P528
X2P528
X2P528
X2P528
X2P528
X2P846
X2P846
X2P846
X2P998
X2P998
X2P998
X2P1148
X2P1148
X2P1148
X2P1346
X2P1346
X2P1346
None
None
None
None
None
None
Table 16: Xilinx Spartan-3 Cross Reference
Utilization
FPGA
Part
Package
XC3S200
XC3S400
XC3S400
XC3S1000
XC3S1000
XC3S1000
XC3S1500
XC3S1500
XC3S2000
XC3S2000
XC3S4000
XC3S4000
XC3S5000
XC3S5000
FT256
FT256
FG456
FT256
FG456
FG676
FG456
FG676
FG900
FG676
FG900
FG1156
FG900
FG1156
I/O
Base
100%
Logic
Base
50%
RAM
Base
100%
RAM
Base
X2P376
X2P376
X2P376
X2P376
X2P376
X2P528
X2P376
X2P528
X2P680
X2P528
X2P680
X2P846
X2P680
X2P846
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P528
X2P528
X2P680
X2P680
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P376
X2P528
X2P528
X2P680
X2P680
X2P680
X2P680
X2P376
X2P376
X2P376
X2P528
X2P528
X2P528
X2P528
X2P528
X2P680
X2P680
X2P846
X2P846
X2P846
X2P846
AMI Semiconductor - Preliminary
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14
© 2004 AMI Semiconductor, Inc.
AMI Semiconductor makes no warranty for the use of its products, other than those expressly contained in the company’s standard warranty contained in AMI Semiconductor’s Terms and Conditions. The company
assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to
update the information contained herein. No licenses to patents or other intellectual property of AMI Semiconductor are granted by the company in connection with the sale of AMI Semiconductor products, expressly or
by implication. The foregoing names that are not registered trademarks of AMI Semiconductor constitute protected trade names, trademarks and/or service marks of their respective owners. HM