a u s t ri a m i c r o s y s t e m s D a ta S he e t AS 1156/AS1154 S i n g l e / D u a l LV D S D r i v e r 1 General Description 2 Key Features The AS1156/AS1154 is a Single/Dual Flow-Through LVDS (Low-Voltage Differential Signaling) Line Driver which accepts and converts LVTTL/LVCMOS input levels into LVDS output signals. The device is perfect for low-power low-noise applications requiring high signaling rates and reduced EMI emissions. The device is guaranteed to transmit data at speeds up to 800Mbps (400MHz) over controlled impedance media of approximately 100Ω. Supported transmission media are PCB traces, backplanes, and cables. The AS1156 is a single LVDS transmitter, and the AS1154 is a dual LVDS transmitter. Outputs conform to the ANSI TIA/EIA-644 LVDS standards. Flow-through pinout simplifies PC board layout and reduces crosstalk by separating the LVTTL/LVCMOS inputs and LVDS outputs. The AS1156/AS1154 operates from a single +3.3V supply and is specified for operation from -40 to +85°C. ! Flow-Through Pinout ! Guaranteed 800Mbps Data Rate ! 250ps Pulse Skew (Max) ! Conforms to ANSI TIA/EIA-644 LVDS Standards ! Single +3.3V Supply ! Operating Temperature Range: -40 to +85°C ! 8-Pin SOIC Package 3 Applications Digital Copiers, Laser Printers, Cellular Phone Base Stations, Add/Drop Muxes, Digital Cross-Connects, DSLAMs, Network Switches/Routers, Backplane Interconnect, Clock Distribution Computers, Intelligent Instruments, Controllers, Critical Microprocessors and Microcontrollers, Power Monitoring, and Portable/Battery-Powered Equipment. Figure 1. Block Diagram AS1156 VCC AS1154 VCC OUT1- OUT1Tx Tx IN1 OUT1+ IN1 N/C N/C IN2 OUT1+ OUT2+ Tx GND www.austriamicrosystems.com N/C GND Revision 1.00 OUT2- 1 - 15 austriam i c r o systems AS1156/AS1154 Data Sheet Pin Assignments 4 Pinout and Packaging Pin Assignments Figure 2. AS1156/AS1154 Pin Assignments (Top View) VCC 1 IN1 2 8 OUT1- VCC 1 7 OUT1+ IN1 2 8 OUT1- 7 OUT1+ AS1154 AS1156 N/C 3 6 N/C IN2 3 6 OUT2+ GND 4 5 N/C GND 4 5 OUT2- Pin Descriptions Table 1. AS1156/AS1154 Pin Descriptions Pin Number Pin Name Description 1 VCC Power Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors. 2 IN1 LVTTL/LVCMOS Driver Input IN2 LVTTL/LVCMOS Driver Input 4 GND AS1154 AS1156 1 2 3 4 Ground 5 OUT2- Inverting LVDS Driver Output 6 OUT2+ Noninverting LVDS Driver Output 7 7 OUT1+ Noninverting LVDS Driver Output 8 8 OUT1- Inverting LVDS Driver Output 3, 5, 6 N/C www.austriamicrosystems.com Not connected Revision 1.00 2 - 15 austriam i c r o systems AS1156/AS1154 Data Sheet Pin Descriptions 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter Limits Units VCC to GND -0.3 to +5.0 V INx, EN, ENn to GND -0.3 to (VCC + 0.3) V OUTx+, OUTx- to GND -0.3 to +5 V Short Circuit Duration (OUTx+, OUTx-) Continuous Continuous Power Dissipation (TA = +70°C) 755 mW Storage Temperature Range -65 to +150 ºC Maximum Junction Temperature +150 ºC Operating Temperature Range -40 to +85 ºC Notes Derate 9.4mW/°C Above +70°C Package Body Temperature 260 ºC The reflow peak soldering temperature (body temperature) specified is in compliance with IPC/JEDEC J-STD020C “Moisture/ Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. ESD Protection ±4 kV Human Body Model, INx, OUTx+, OUTx-- www.austriamicrosystems.com Revision 1.00 3 - 15 austriam i c r o systems AS1156/AS1154 Data Sheet DC Electrical Characteristics 6 Electrical Characteristics DC Electrical Characteristics (VCC = +3.0 to +3.6V, TA = -40 to +85°C , RL = 100Ω ±1% Typical values are at VCC = +3.3V, TA = +25°C, Unless Otherwise Noted.) 1 Table 3. DC Electrical Characteristics Parameter Symbol Conditions Min Typ Max Unit Differential Output Voltage VOD Figure 21 on page 11 250 355 450 mV Change in Magnitude of VOD Between Complementary Output States ΔVOD Figure 21 on page 11 1 35 mV Offset Voltage VOS Figure 21 on page 11 1.25 1.375 V Change in Magnitude of VOS Between Complementary Output States ΔVOS Figure 21 on page 11 4 25 mV Output High Voltage VOH 1.6 V Output Low Voltage VOL Differential Output Short-Circuit Current 2 IOSD VOD = 0V Output Short-Circuit Current IOS OUTx+ = 0V at INx = VCC or OUTx- = 0V at INx = 0V Power-Off Output Current IOFF VCC = 0V or open, OUTx+ = 0V or 3.6V OUTx- = 0V or 3.6V, RL = ∞ LVDS Output (OUtx+, OUTx-) 1.125 0.90 V -9 mA -9 mA -20 20 µA -3.7 Inputs (INx) High-Level Input Voltage VIH 2.0 VCC V Low-Level Input Voltage VIL GND 0.8 V Input Current IIN INx = 0V or VCC -20 20 µA ICC RL = ∞ , INx = VCC or 0V for all channels 2 3.5 mA RL = 100Ω, INx = VCC or 0V for all channels, AS1156 5.5 7.5 mA RL = 100Ω, INx = VCC or 0V for all channels, AS1154 8.5 12 mA Supply Current No-Load Supply Current Loaded Supply Current ICCL Notes: 1. Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except VOD. 2. Guaranteed by correlation data. www.austriamicrosystems.com Revision 1.00 4 - 15 austriam i c r o systems AS1156/AS1154 Data Sheet Switching Characteristics Switching Characteristics (VCC = +3.0 to +3.6V, RL = 100Ω ±1%, CL = 2.5pF (differential), TA = -40 to +85°C Typical values are at VCC = +3.3V, TA = +25ºC, Unless Otherwise Noted.) 1, 2, 3, 10 Table 4. Switching Characteristics Parameter Symbol Conditions Min Typ Max Unit Differential Propagation Delay, High-to-Low tPHLD Figure 20 on page 11 and Figure 21 on page 11 1.1 1.268 1.5 ns Differential Propagation Delay, Low-to-High tPLHD Figure 20 on page 11 and Figure 21 on page 11 1.1 1.267 1.5 ns Differential Pulse Skew 4 tSKD1 Figure 20 on page 11 and Figure 21 on page 11 90 200 ps Differential Channel-to-Channel Skew 5 tSKD2 Figure 20 on page 11 and Figure 21 on page 11 110 250 ps Differential Part-to-Part Skew 6 tSKD3 Figure 20 on page 11 and Figure 21 on page 11 750 ps Differential Part-to-Part Skew 7 tSKD4 Figure 20 on page 11 and Figure 21 on page 11 900 ps Rise Time tTLH Figure 20 on page 11 and Figure 21 on page 11 200 356 800 ps Fall Time tTHL Figure 20 on page 11 and Figure 21 on page 11 200 352 800 ps Maximum Operating Frequency 8, 9 fMAX 400 MHz Notes: 1. Parameters are guaranteed by design and characterization. 2. CL includes probe and jig capacitance. 3. Signal generator conditions for dynamic tests: VOL = 0, VOH = 2.4V, f = 100MHz, 50% duty cycle, RO = 50Ω, tR ≤ 1ns, tF ≤ 1ns (0 to 100%). 4. tSKD1 is the magnitude difference of differential propagation delay. tSKD1 = |tPHLD - tPLHD|. 5. tSKD2 is the magnitude difference of tPHLD or tPLHD of one channel to the tPHLD or tPLHD of another channel on the same device. 6. tSKD3 is the magnitude difference of any differential propagation delays between devices at the same VCC and within 5°C of each other. 7. tSKD4 is the magnitude difference of any differential propagation delays between devices operating over the rated supply and temperature ranges. 8. fMAX signal generator conditions: VOL = 0, VOH = 2.4V, 50% duty cycle, RO = 50Ω, tR ≤ 1ns, tF ≤ 1ns (0 to 100%). 9. Transmitter output criteria: duty cycle = 45 to 55%, VOD ≥ 250mV. 10. For optimum performance matched circuits should be used. www.austriamicrosystems.com Revision 1.00 5 - 15 austriam i c r o systems AS1156/AS1154 Data Sheet Switching Characteristics 7 Typical Operating Characteristics VCC = +3.3V, CLOAD = 2.5pF (differential), Freq = 20MHz, Tamb = +25ºC, unless otherwise noted Figure 4. Transition Time vs. Temperature Figure 3. Transition Time vs. VCC 270 350 . 300 tTHL 260 Transition Time (ps) Transition Time (ps) . tTHL 250 240 tTLH 250 150 100 50 230 3 3.1 3.2 tTLH 200 3.3 3.4 3.5 0 -50 3.6 -30 Supply Voltage(V) -10 10 30 50 70 90 Ambient Temperature(°C) Figure 5. Differential Pulse Skew vs. VCC Figure 6. Pulse Skew vs. Temperature 35 70 30 . 60 Pulse Skew (ps) Differential Pulse Skew (ps) . 80 50 40 30 20 25 20 15 10 5 10 0 3 3.1 3.2 3.3 3.4 3.5 0 -50 3.6 Supply Voltage(V) -30 -10 10 30 50 70 90 Ambient Temperature(°C) Figure 7. Differential Propagation Delay vs. VCC; Figure 8. Differential Propagation Delay vs. Temp. 1.14 . . 1.05 Diff. Propagation Delay (ns) Diff. Propagation Delay (ns) 1.12 1.03 tPHLD 1.01 0.99 0.97 tPLHD 0.95 3 3.1 3.2 3.3 3.4 3.5 3.6 1.1 1.08 tPLHD 1.04 1.02 1 0.98 -50 Supply Voltage(V) www.austriamicrosystems.com tPHLD 1.06 -30 -10 10 30 50 70 90 Ambient Temperature(°C) Revision 1.00 6 - 15 austriam i c r o systems AS1156/AS1154 Data Sheet Switching Characteristics Figure 10. Differential Output Voltage vs. Frequency . 350 Differential Output Voltage (mV) Differential Output Voltage (mV) . Figure 9. Differential Output Voltage vs. VCC 345 340 335 330 325 3 3.1 3.2 3.3 3.4 3.5 350 300 250 200 150 100 50 0 3.6 0 50 100 150 200 250 300 350 400 Supply Voltage (V) Frequency (MHz) Figure 11. Offset Voltage vs. VCC Figure 12. Offset Voltage vs. Frequency 1.35 Offset Voltage (V) . Offset Voltage (V) . 1.24 1.23 1.22 1.21 1.3 1.25 1.2 1.15 1.2 1.1 3 3.1 3.2 3.3 3.4 3.5 3.6 0 50 Supply Voltage (V) Figure 13. Output Voltage vs. VCC; 150 200 250 Figure 14. Output Voltage vs. Load Resistance; 1.45 1.45 VOUT+ 1.35 Output Voltage (V) . Output Voltage (V) . 100 Frequency (MHz) 1.25 1.15 VOUT- 1.05 0.95 1.35 VOUT+ 1.25 1.15 VOUT- 1.05 0.95 3 3.1 3.2 3.3 3.4 3.5 3.6 80 www.austriamicrosystems.com 90 100 110 120 130 140 150 Load Resistance (Ω ) Supply Voltage (V) Revision 1.00 7 - 15 austriam i c r o systems AS1156/AS1154 Data Sheet Switching Characteristics Figure 15. ICC vs. VCC Figure 16. ICC vs. Temperature; . 13 10.6 Supply Current (mA) Supply Current (mA) . 11 10.2 9.8 9.4 9 3 3.1 3.2 3.3 3.4 3.5 12 Freq = 100MHz 11 10 Freq = 20MHz 9 8 -50 3.6 Supply Voltage (V) -30 -10 10 30 50 70 90 Ambient Temperature(°C) Figure 17. Short Circuit Current vs. VCC Figure 18. ICC vs. Frequency 18 Output Short Circuit Current (mA) . 3.9 16 Supply Current (mA) . 3.85 3.8 3.75 3.7 3.65 14 Two Channels 12 One Channel 10 8 6 4 2 3.6 0 3 3.1 3.2 3.3 3.4 3.5 0 3.6 Supply Voltage(V) www.austriamicrosystems.com 50 100 150 200 250 Frequency (MHz) Revision 1.00 8 - 15 austriam i c r o systems AS1156/AS1154 Data Sheet LVDS Interface 8 Detailed Description LVDS Interface The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-impedance medium as defined by the ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The AS1156/AS1154 is an 800Mbps single/dual differential LVDS driver that is designed for high-speed, point-to-point, low-power applications. This device accepts LVTTL/LVCMOS input levels and translates them to LVDS output signals. The AS1156/AS1154 generates a 2.5mA to 4.5mA output current using a current-steering configuration. This current steering approach induces less ground bounce and no shoot-through current, enhancing noise margin and system speed performance. The driver outputs are short-circuit current limited, and enter a high-impedance state when the device is not powered or is disabled. The current-steering architecture of the AS1156/AS1154 requires a resistive load to terminate the signal and complete the transmission loop. Because the device switches current and not voltage, the actual output voltage swing is determined by the value of the termination resistor at the input of an LVDS receiver (AS1157, AS1158). Logic states are determined by the direction of current flow through the termination resistor. With a typical 3.7mA output current, the AS1156/AS1154 produces an output voltage of 370mV when driving a 100Ω load. Termination Because the AS1156/AS1154 is a current-steering device, no output voltage will be generated without a termination resistor. The termination resistors should match the differential impedance of the transmission line. Output voltage levels depend upon the value of the termination resistor. The AS1156/AS1154 is optimized for point-to-point interface with 100Ω termination resistors at the receiver inputs. Termination resistance values may range between 90 and132Ω, depending on the characteristic impedance of the transmission medium. www.austriamicrosystems.com Revision 1.00 9 - 15 austriam i c r o systems AS1156/AS1154 Data Sheet Power-Supply Bypassing 9 Applications Table 5. Function Table Input Output INx OUTx+ OUTx- L L H H H L 0.8V < VINx < 2.0V Undetermined Undetermined Figure 19. Typical Application Circuit +3.3V +3.3V 0.001µF 0.001µF 0.1µF 0.1µF LVDS Signals LVTTL/LVCMOS Data Inputs Tx 107Ω Rx LVTTL/LVCMOS Data Outputs AS1158 Single LVDS Receiver AS1156 100Ω Shielded Twisted Cable or Microstrip PC Board Traces Power-Supply Bypassing To bypass VCC, use high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to pin VCC. Differential Traces Input trace characteristics can adversely affect the performance of the AS1156/AS1154. ! Use controlled-impedance PC board traces to match the cable characteristic impedance. The termination resistor is also matched to this characteristic impedance. ! Eliminate reflections and ensure that noise couples as common mode by running the differential traces near each other. ! Reduce skew by using matched trace lengths. Tight skew control is required to minimize emissions and proper data recovery of the devices. ! Route each channel’s differential signals very close to each other for optimal cancellation of their respective external magnetic fields. Use a constant distance between the differential traces to avoid irregularities in differential impedance. ! Avoid 90° turns (use two 45° turns). ! Minimize the number of vias to further prevent impedance irregularities. Cables and Connectors Supported transmission media include printed circuit board traces, backplanes, and cables. ! Use cables and connectors with matched differential impedance (typically 100Ω) to minimize impedance mismatches. ! Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. ! Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable. www.austriamicrosystems.com Revision 1.00 10 - 15 austriam i c r o systems AS1156/AS1154 Data Sheet Board Layout The device should be placed as close to the interface connector as possible to minimize LVDS trace length. ! Keep the LVDS and any other digital signals separated from each other to reduce crosstalk. ! Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals. ! Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent coupling. ! Separate the input LVDS signals from the output signals planes with the power and ground planes for best results. Figure 20. Driver Propagation Delay and Transition Time Waveforms 1.5V 1.5V tPLHD tPHLD INx VOH OUTx0 Differential 0 OUTx+ VOL 80% 0 80% VDIFF = (VOUTx+) - (VOUTx-) 00 20% 20% tTLH tTHL Figure 21. Driver Propagation Delay and Transition Time Test Circuit OUTx+ Generator CL RL 50Ω OUTx- www.austriamicrosystems.com Revision 1.00 11 - 15 austriam i c r o systems AS1156/AS1154 Data Sheet Figure 22. Driver VOD and VOS Test Circuit OUTx+ RL/2 VCC INx VOS VOD GND RL/2 OUTx- www.austriamicrosystems.com Revision 1.00 12 - 15 austriam i c r o systems AS1156/AS1154 Data Sheet Board Layout 10 Package Drawings and Markings The AS1156/AS1154 is available in a 8-pin SOIC package. Figure 23. 8-pin SOIC Package Notes: 1. Lead coplanarity should be 0 to 0.10mm (.004”) max. 2. Package surface finishing: - Top, matte (charmilles #18-30) - All sides, matte (charmilles +18-30) - Bottom, smooth or matte (charmilles +18-30) 3. All dimensions excluding mold flashes and end flash from the package body shall not exceed 0.25mm (.010”) per side. 4. Details of pin #1 mark are optional but must be located within the area indicated. www.austriamicrosystems.com Revision 1.00 Symbol A A1 A2 B C D E e H h L α ZD Min Max 1.52 1.72 0.10 0.25 1.37 1.57 0.36 0.46 0.19 0.25 4.80 4.98 3.81 3.99 1.27BSC 5.80 6.20 0.25 0.50 0.41 1.27 0º 8º 0.53REF 13 - 15 austriam i c r o systems AS1156/AS1154 Data Sheet Board Layout 11 Ordering Information Part Number Description Delivery Form Package AS1156-BSOU Single Channel LVDS Line Driver Tubes SOIC-8 AS1156-BSOT Single Channel LVDS Line Driver Tape and Reel SOIC-8 AS1154-BSOU Dual Channel LVDS Line Driver Tubes SOIC-8 AS1154-BSOT Dual Channel LVDS Line Driver Tape and Reel SOIC-8 www.austriamicrosystems.com Revision 1.00 14 - 15 austriam i c r o systems AS1156/AS1154 Data Sheet Board Layout Copyrights Copyright © 1997-2006, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact austriamicrosystems www.austriamicrosystems.com Revision 1.00 – a leap ahead 15 - 15