Preliminary Datasheet AS3510 Analog Audio Front-End Analog Voice Codec AS3510 AS14889 General Description PRODUCT BRIEF PRELIMINARY DATA SHEET Key Features The AS3510 combines high flexibility and outstanding performance for analog audio front-end solutions. On chip DCDC Converter This codec-chip contains a high performance 18 bit digital to analog converter. The dynamic range exceeds 95dB for best audio quality, for multi media applications (audio playback) within battery or line operated equipment. 4 On-chip high performance voltage regulators - An additional audio power amplifier can directly drive - external headphones or small 4Ω speakers with a power of up to half a watt. The power-up is click- and pop-less due to a smooth start-up circuitry. The overall distortion level is always below 0.02%. 18 Bit stereo DAC The microphone input amplifier contains an automatic gain control (AGC) with a dynamic range of 40dB to generate an amplified and compressed signal for the ADC, which provides 14 Bit resolution at 8kHz sampling-rate. Furthermore all necessary power management is included such as bandgap reference and four voltage regulators. The two 2.9V regulators are used internally (analog and digital supply), but can also be used for external purposes as well. The third output is designed to supply the peripheral cells and an external digital core, and is programmable from 1.5V to 2.5V in 5 steps (default is 2.5V). They are all powered through a DCDC-Converter, which can work down to a voltage of 1V. So the whole chip can work from a single battery cell. The fourth regulator is only used for generating the supply voltage for the analog USB 1.1 interface circuit. It is supplied via the USB connector. The performance of the regulators is excellent (noise, line- and load-regulation) and allows the direct supply of sensitive analog circuits. - - - 1.0 to 5.5V input voltage range Digital Supply, 2.9V Analog Supply, 2.9V Core Supply, 1.5 to 2.5V USB Transceiver Supply, 3.2V Dynamic range >95 dB THD < -85dB De-emphasis for 32 kHz, 44.1 kHz and 48 kHz Stereo power audio amplifier - Max. 2x 0.5W @ 4Ω Analog volume control –39dB to +3dB, 3dB steps including mute) Click- and pop-less startup and power down Auxiliary inputs for additional audio sources Microphone input - - 14 Bit Σ∆−ADC , 8kHz sampling rate Automatic gain control (AGC) Low power consumption Wide battery supply range 1.0V – 5.5V Standard I2S interface Audio sampling rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, and 48 kHz I2C control interface USB 1.1 front-end 49 Pin BGA Package Because of the internal supply and signal filtering only few small external capacitors are required for de-coupling and stabilising and lead to very low output noise. Applications The current consumption is very low and makes the chip ideally for battery powered devices. - Rev. 1v2, June 2004 - Audio frontend for cellular phones Stand alone MP3 player CD and DVD player PDAs Page 1 of 2 - - SDI SDA - SCLK - - LRCK SCL - MCLK Control Interface (I2C Slave) Serial Audio Interface (I2S) & Clock Generation Digital I2S Synchronisation OEN RCV USB Connector X X AUXL Single Ended to Differental Converter X X AUXR DAC + SC LPF DAC + SC LPF UVDD µP USB Interface D+ D- VTRM Multibit SD Modulator with DWA USB 1.1 + LDO3.2V Interpolator *64 - - VM - SDO Dither Generation VP - - Multibit SD Modulator with DWA VMO - DVSS Interpolator *64 VPO - 2nd Order SD ADC 14Bit, 8kHz + Interpolator - - VTRM - Microphon Amplifier - Referenze Voltage & Current Generation - - AVSS - - VREF - - AGND - MICN - VSS BVDD BVSS DCDC Converter Gain Control +3...-39dB Left Power Amplifier BVDD BVSS Right Power Amplifier Gain Control +3...-39dB AVSS2 - MICP - 10u 1 to 5.5V Battery VBAT1V SW - 100n - 10u BVDD - Rev. 1v2, June 2004 AVSS BVDD ENDCDC LDO2 BGND Buffer - µP Digital Audio Interface AVSS BVDD AVSS BVDD Pop-less Startup ENLDO12 - Figure 1 LDO3 BVSS BVDD LDO1 - AVDD PLDO3 - 100n BVDD OUTR BVSS OUTL - - - - 2,2u / 6,3V Z5U V_REG3 2,2u with RL=150 Ohm, or 330u with RL=8 Ohm Headphone Jack c2,2u with RL=150 Ohm, or 330u with RL=8 Ohm QLDO3 PVDD QLDO2 DVDD - - 2,2u / 6,3V Z5U 2,9V, 50mA @ BVDD=3V V_REG2 2,2u / 6,3V Z5U 1,75V to 2.5V, 200mA @ BVDD=3V BGND - - QLDO1 V_REG1 2,9V, 50mA @ BVDD=3V Preliminary Datasheet AS3510 Block Diagram µP Control Interface Block Diagram of AS3510 Page 2 of 2