ANPEC APL5913-KAC-TR

APL5913
0.8V Reference Ultra Low Dropout ([email protected]) Linear Regulator
Features
General Description
•
The APL5913 is a 3A ultra low dropout linear regulator.
This product is specifically designed to provide well
supply volatage for front-side-bus termination on
motherboards and NB applications. The IC needs two
supply voltages, a control voltage for the circuitry and
a main supply voltage for power conversion, to reduce
power dissipation and provide extremely low dropout.
The APL5913 integrates many functions. A Power-OnReset (POR) circuit monitors both supply voltages to
prevent wrong operations. A thermal shutdown and
current limit functions protect the device against
thermal and current over-loads. A POK indicates the
output status with time delay which is set internally. It
can control other converter for power sequence. The
APL5913 can be enabled by other power system.
Pulling and holding the EN pin below 0.3V shuts off
the output.
The APL5913 is available in SOP-8-P package which
features small size as SOP-8 and an Exposed Pad to
reduce the junction-to-case resistance, being applicable
in 2~3W applications.
Ultra Low Dropout
- 0.25V(typical) at 3A Output Current
•
Low ESR Output Capacitor (Multi-layer Chip
Capacitors (MLCC)) Applicable
•
0.8V Reference Voltage
•
High Output Accuracy
- ±1.5% over Line, Load and Temperature
•
Fast Transient Response
•
Adjustable Output Voltage by External
Resistors
•
Power-On-Reset Monitoring on Both VCNTL
and VIN Pins
•
Internal Soft-Start
•
Current-Limit Protection
•
Under-Voltage Protection
•
Thermal Shutdown with Hysteresis
•
Power-OK Output with a Delay Time
•
Shutdown for Standby or Suspend Mode
•
Simple SOP-8-P Package with Exposed Pad
•
Lead Free Available (RoHS Compliant)
Pin Configuration
Applications
•
Front Side Bus VTT (1.2V/3A)
•
Note Book PC Applications
•
Motherboard Applications
GND
FB
VOUT
VOUT
1
8
2
7
3
4
VIN
6
5
EN
POK
VCNTL
VIN
SOP-8-P (Top View)
= Exposed Pad
(connected to VIN plane for better heat
dissipation)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - May., 2005
1
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APL5913
Ordering and Marking Information
Package Code
KA : SOP-8-P
Operating Ambient Temp. Range
C : 0 to 70°C
Handing Code
TU : Tube
TR : Tape & Reel
Lead Free Code
L : Lead Free Device
Blank : Original Device
APL5913 Lead Free Code
Handling Code
Temp. Range
Package Code
APL5913 KA :
APL5913
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate
termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering
operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C
for MSL classification at lead-free peak reflow temperature.
Block Diagram
EN
VCNTL
VIN
PowerOn-Reset
UV
Soft-Start
and
Control Logic
Thermal
Limit
0.4V
VREF
0.8V
EAMP
VOUT
Current
Limit
FB
POK
Delay
GND
90%
VREF
POK
Copyright  ANPEC Electronics Corp.
Rev. A.4 - May., 2005
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APL5913
Typical Application Circuit
1. Using an Output Capacitor with ESR≥18mΩ
VCNTL
+5V
C CNTL
1uF
6
R3
1k
VCNTL
7
POK
VIN
POK
VOUT
VOUT
5
3
4
C OUT
220 uF
APL5913
8
EN
EN
FB
2
GND
Enable
VIN
+1.5V
C IN
100uF
1
R2
2k
VOUT
+1.2V / 3A
R1
1k
C1
33nF (in the range of 12 ~ 48nF)
2. Using an MLCC as the Output Capacitor
VCNTL
+5V
C CNTL
1uF
6
R3
1k
C IN
22uF
VCNTL
7
POK
VIN
POK
VOUT
VOUT
5
3
4
COUT
APL5913
EN
8
EN
FB
VOUT
+1.2V / 3A
22uF
2
GND
Enable
VIN
+1.5V
1
R2
78k
R1
39k
C1
56pF
VOUT (V)
1.05
1.5
1.8
Copyright  ANPEC Electronics Corp.
Rev. A.4 - May., 2005
R1 (kΩ)
43
27
15
R2 (kΩ)
137.6
30.86
12
3
C1 (pF)
47
82
150
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APL5913
Absolute Maximum Ratings
Symbol
VCNTL
Parameter
VIN Supply Voltage (VIN to GND)
VI/O
EN and FB to GND
VPOK
POK to GND
PPEAK
TJ
TSTG
Unit
-0.3 ~ 7
V
-0.3 ~ 3.3
V
-0.3 ~ VCNTL+0.3
V
-0.3 ~ 7
V
3
W
VCNTL Supply Voltage (VCNTL to GND)
VIN
PD
Rating
Average Power Dissipation
Peak Power Dissipation (<20mS)
20
150
C
-65 ~ 150
o
C
300
o
C
Junction Temperature
Storage Temperature
TSDR
Soldering Temperature, 10 Seconds
VESD
Minimum ESD Rating (Human Body Mode)
W
o
±2
kV
Thermal Characteristics
Symbol
θJA
Parameter
Value
Junction-to-Ambient Thermal Resistance in Free Air (Note)
Unit
o
40
C/W
Note : θJA is measured with the component mounted on a high effective thermal conductivity test
board in free air. The exposed pad of SOP-8-P is soldered directly on the PCB.
Recommended Operating Conditions
Symbol
VCNTL
VIN
Parameter
Range
Unit
3.1 ~ 6
V
1.1 ~ 3.3
V
VCNTL=3.3±5%
0.8 ~ 1.2
V
VCNTL=5.0±5%
0.8 ~ VIN-0.2
VCNTL Supply Voltage
VIN Supply Voltage
Output Voltage
VOUT
IOUT
TJ
VOUT Output Current
0~4
Junction Temperature
A
o
-25 ~ 125
C
Electrical Characteristics
Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.5V, VOUT = 1.2V and TA = 0
to 70° C, unless otherwise specified. Typical values refer to T A = 25° C.
Parameter
Symbol
Test Conditions
APL5913
Unit
Min
Typ
Max
0.4
1
8
mA
180
300
µA
SUPPLY CURRENT
ICNTL
ISD
VCNTL Nominal Supply Current
EN = VCNTL
VCNTL Shuntdown Current
EN = GND
Copyright  ANPEC Electronics Corp.
Rev. A.4 - May., 2005
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APL5913
Electrical Characteristics (Cont.)
Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.5V, VOUT = 1.2V and TA = 0
to 70° C, unless otherwise specified. Typical values refer to T A = 25° C.
Parameter
Symbol
APL5913
Test Conditions
Min
Typ
Max
2.7
2.9
3.1
Unit
POWER-ON-RESET
VCNTL POR Threshold
VCNTL Rising
VCNTL POR Hysteresis
VIN POR Threshold
V
0.4
VIN Rising
0.8
VIN POR Hysteresis
0.9
V
1.0
0.5
V
0.8
V
OUTPUT VOLTAGE
VREF
Reference Voltage
FB =VOUT
o
Output Voltage Accuracy
IOUT=0A ~ 5A, TJ= -25 ~125 C
Line Regulation
Load Regulation
-1.5
+1.5
%
VCNTL=3.3 ~ 5V
0.06 0.15
%
IOUT=0A ~ 3A
0.06 0.15
%
0.17 0.25
V
0.3
V
6.2
A
DROPOUT VOLTAGE
o
Dropout Voltage
IOUT = 3A, VCNTL=5V, TJ= 25 C
o
IOUT = 3A, VCNTL=5V, TJ= -50~125 C
PROTECTION
o
VCNTL=5V, TJ= 25 C
3.8
o
ILIM
Current Limit
VCNTL=5V, TJ= -25 ~ 125 C
o
VCNTL=3.3V, TJ= 25 C
VCNTL=3.3V, TJ= -25 ~ 125 C
TSD
4
3.8
o
A
4.8
5.3
Thermal Shutdown Hysteresis
VFB Falling
A
A
3.8
Thermal Shutdown Temperature TJ Rising
Under-Voltage Threshold
5
150
o
50
o
C
C
V
0.4
ENABLE and SOFT-START
EN Logic High Threshold Voltage VEN Rising
0.3
EN Hysteresis
EN Pin Pull-Up Current
TSS
EN=GND
Soft-Start Interval
POWER OK and DELAY
POK Threshold Voltage for Power
VPOK
VFB Rising
OK
POK Threshold Voltage for Power
VPNOK
VFB Falling
Not OK
POK Low Voltage
POK sinks 5mA
TDELAY
POK Delay Time
Copyright  ANPEC Electronics Corp.
Rev. A.4 - May., 2005
0.5
V
30
mV
10
µA
2
mS
90% 92% 94% VREF
79% 81% 83% VREF
1
5
0.4
0.25
0.4
V
3
10
mS
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APL5913
Typical Operating Characteristics
Current-limit vs. Junction Temperature
5.5
1.0
0.9
5.4
VCNTL =5V
0.8
Current-limit, I LIM (A)
VCNTL Supply Current, ICNTL (mA)
VCNTL Supply Current vs. Junction Temperature
0.7
0.6
0.5
VCNTL=3.3V
0.4
0.3
5.3
5.2
VCNTL =5V
5.1
5
4.9
4.8
0.2
4.7
0.1
4.6
VCNTL=3.3V
4.5
-50
0.0
-50
-25
0
25
50
75
100
125
VOUT=1.2V
100
125
VOUT=1.2V
Dropout Voltage (mV)
Dropout Voltage (mV)
75
VCNTL =5V
TJ=125°C
TJ=75°C
TJ=25°C
300
50
250
VCNTL=3.3V
350
25
Dropout Voltage vs. Output Current
Dropout Voltage vs. Output Current
400
0
Junction Temperature (°C)
Junction Temperature (°C)
450
-25
250
TJ=0°C
200
150
TJ=-25°C
100
TJ=125°C
200
TJ=75°C
150
TJ=25°C
100
TJ=0°C
TJ=-25°C
50
50
0
0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
3.0
Output Current, lOUT(A)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - May., 2005
0.5
1.0
1.5
2.0
2.5
3.0
Output Current, lOUT(A)
6
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APL5913
Typical Operating Characteristics
Reference Voltage vs. Junction Temperature
POK Delay Time vs. Junction Temperature
4.5
4.3
0.806
4.1
0.804
POK Delay Time (ms)
Referemce Voltage, V REF (mV)
0.808
0.802
0.800
0.798
0.796
0.794
3.9
VCNTL =5V
3.7
3.5
3.3
VCNTL=3.3V
3.1
2.9
2.7
2.5
0.792
-50
-25
0
25
50
75
100
-50
125
Junction Temperature (°C)
-25
0
100
125
0
VCNTL = 4.5V~5.5V
VIN = 1.5V
VOUT = 1.2V
IOUT = 3A
CIN = 100µF
COUT = 330uF(ESR=30mΩ)
-10
-20
Amplitude (dB)
Ripple Rejection (dB)
75
VIN PSRR
0.00
-20.00
50
Junction Temperature (°C)
VCNTL PSRR
-10.00
25
-30.00
-40.00
-50.00
VCNTL = 5V
VIN = 1.5V(lower bound)
VINPK-PK = 100mV
CIN = 47µF
COUT = 330uF(30mΩ )
IOUT = 3A
VOUT = 1.2V
-30
-40
-50
-60
-70
-60.00
100
1000
10000
100000
100
1000000
Rev. A.4 - May., 2005
10000
100000
1000000
Frequency (Hz)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
1000
7
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APL5913
Operating Waveforms
R4
C2
1uF
L1
1uH
2.2
+5V
5
R8
8.2k
C8
470pF
VCC
BOOT
7
UGATE
PHASE
2
Q1
APM2014N L2
3.3uH
LGATE
POK
VCNTL
VIN
+1.5V
5
POK
VIN
CIN
100uF
C5
1000uFx2
Q2
APM2014N
4
FB
VCNTL
+5V
CVCNTL
1uF
8
U2
APW7057
6
C9
47uF
6
C6
0.1uF
Q3
C4
470uFx2
1
OCSET
Shutdown
C3
1uF
D1
1N4148
VOUT
VOUT
U1
APL5913
GND
3
R5
1.75k
EN
8
Enable
EN
FB
R3
1k
7
3
4
COUT
220uF
2
R1
1k
GND
1
R2
2k
R7
2k
C7
0.1uF
VOUT
+1.2V/3A
C1
33nF
R6
0
1. Load Transient Response :
1.1 Using an Output Capacitor with ESR≥18mΩ
- COUT = 220µF/6.3V (ESR = 30mΩ ), CIN = 100µF/6.3V
- IOUT = 10mA to 3A to 10mA, Rise time = Fall time = 1µS
IOUT = 10mA -> 3A
IOUT = 10mA -> 3A ->10mA
IOUT = 3A -> 10mA
R1=1kΩ, R2=2kΩ, C1=33nF
VOUT
VOUT
IOUT
IOUT
VOUT
1
IOUT
2
Ch1 : VOUT, 50mV/Div
Ch1 : VOUT, 50mV/Div
Ch1 : VOUT, 50mV/Div
Ch2 : IOUT, 1A/Div
Ch2 : IOUT, 1A/Div
Ch2 : IOUT, 1A/Div
Time : 20µS/Div
Time : 2µS/Div
Time : 2µS/Div
Copyright  ANPEC Electronics Corp.
Rev. A.4 - May., 2005
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APL5913
Operating Waveforms (Cont.)
1.2 Using an MLCC as the Output Capacitor
- COUT = 22µF/6.3V (ESR = 3mΩ ), CIN = 22µF/6.3V
- IOUT = 10mA to 3A to 10mA, Rise time = Fall time = 1µS
IOUT = 10mA -> 3A
IOUT = 3A -> 10mA
R1=39kΩ, R2=78kΩ
C1=56pF
VOUT
VOUT
1
IOUT = 10mA -> 3A ->10mA
VOUT
1
1
2
IOUT
IOUT
IOUT
2
2
Ch1 : VOUT, 100mV/Div
Ch1 : VOUT, 100mV/Div
Ch1 : VOUT, 100mV/Div
Ch2 : IOUT, 1A/Div
Ch2 : IOUT, 1A/Div
Ch2 : IOUT, 1A/Div
Time : 20µS/Div
Time : 2µS/Div
Time : 2µS/Div
2. Power ON / Power OFF :
- VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V
- COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL=1Ω
Power OFF
Power ON
VIN
Ch1
Ch1
VIN
VOUT
Ch2
VOUT
VCNTL
Ch2
VCNTL
VPOK
VPOK
Ch3
Ch3
Ch4
Ch4
Ch1 : VIN,1V/div
Ch1 : V IN,1V/div
Ch2 : VOUT,1V/div
Ch2 : V OUT,1V/div
Ch3 : VPOK,1V/div
Ch3 : V POK,1V/div
Ch4 : VCNTL ,2V/div
Ch4 : V CNTL,2V/div
Time : 10ms/div
Time : 10ms/div
Copyright  ANPEC Electronics Corp.
Rev. A.4 - May., 2005
9
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APL5913
Operating Waveforms (Cont.)
3. Shutdown and Enable :
- VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V
- COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL=1Ω
Enable
Shutdown
VEN
Ch1
VEN
Ch1
VOUT
VOUT
Ch2
Ch2
I OUT
I OUT
Ch3
Ch3
VPOK
VPOK
Ch4
Ch4
Ch1 : V EN ,5V/div
Ch1 : V EN ,5V/div
Ch2 : V OUT,1V/div
Ch2 : V OUT,1V/div
Ch3 : IOUT,1A/div
Ch3 : IOUT,1A/div
Ch4 : V POK,1V/div
Ch4 : V POK,1V/div
Time : 1ms/div
Time : 1ms/div
4. POK Delay :
- VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V
- COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL=1Ω
VIN
Ch1
POK Delay
VOUT
Ch2
VPOK
Ch3
Ch1 : V IN,1V/div
Ch2 : V OUT,1V/div
Ch3 : V POK,1V/div
Time : 1ms/div
Copyright  ANPEC Electronics Corp.
Rev. A.4 - May., 2005
10
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APL5913
Functional Pin Description
for the main supply voltage. Please tie the Exposed
Pad and VIN Pin (Pin 8) together to reduce the dropout
voltage. The voltage at this pins is monitored for PowerOn Reset purpose.
GND (Pin 1)
Ground pin of the circuitry. All voltage levels are
measured with respect to this pin.
FB (Pin 2)
VCNTL (Pin 6)
Connecting this pin to an external resistor divider
receives the feedback voltage of the regulator. The
output voltage set by the resistor divider is determined
by:
R1 

V OUT = 0.8 ⋅  1 +

(V)
 R2 
Power input pin of the control circuitry. Connecting
this pin to a +5V (recommended) supply voltage
provides the bias for the control circuitry. The voltage
at this pin is monitored for Power-On Reset purpose.
POK (Pin 7)
where R1 is connected from VOUT to FB with Kelvin
sensing and R2 is connected from FB to GND. A
bypass capacitor may be connected with R1in parallel
to improve load transient response. The recommended
Power-OK signal output pin. This pin is an open-drain
output used to indicate status of output voltage by
sensing FB voltage. This pin is pulled low when the
rising FB voltage is not above the VPOK threshold or
the falling FB voltage is below the VPNOK threshold,
indicating the output is not OK.
R2 and R1 are in the range of 100~10kΩ.
VOUT (Pin 3,4)
Output of the regulator. Please connect Pin 3 and 4
together using wide tracks. It is necessary to connect
a output capacitor with this pin for closed-loop
compensation and improving transient responses.
EN (Pin 8)
VIN (Pin 5) and Exposed Pad
an internal current source 10mA pulls this pin up to
Main supply input pins for power conversions. The
Exposed Pad provide a very low impedance input path
VCNTL voltage, enabling the regulator.
Enable control pin. Pulling and holding this pin below
0.3V shuts down the output. When re-enabled, the IC
undergoes a new soft-start cycle . Left this pin open,
Functional Description
Power-On-Reset
Internal Soft-Start
A Power-On-Reset (POR) circuit monitors both input
voltages at VCNTL and VIN pins to prevent wrong logic
controls. The POR function initiates a soft-start process
after the two supply voltages exceed their rising POR
threshold voltages during powering on. The POR
function also pulls low the POK pin regardless the
output voltage when the VCNTL voltage falls below it’s
falling POR threshold.
An internal soft-start function controls rise rate of the
output voltage to limit the current surge at start-up.
The typical soft-start interval is about 2mS.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - May., 2005
Output Voltage Regulation
An error amplifier working with a temperaturecompensated 0.8V reference and an output NMOS
regulates output to the preset voltage. The error
amplifier designed with high bandwidth and DC gain
11
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APL5913
Functional Description (Cont.)
with a 50oC hysteresis lowers the average junction
temperature during continuous thermal overload
conditions, extending life time of the device.
Output Voltage Regulation (Cont.)
provides very fast transient response and less load
regulation. It compares the reference with the feedback
voltage and amplifies the difference to drive the output
NMOS which provides load current from VIN to VOUT.
For normal operation, device power dissipation should
be externally limited so that junction temperatures will
not exceed +125°C.
Current-Limit
Enable Control
The APL5913 monitors the current via the output
NMOS and limits the maximum current to prevent load
and APL5913 from damages during overload or shortcircuit conditions.
The APL5913 has a dedicated enable pin (EN). A logic
low signal (VEN< 0.3V) applied to this pin shuts down
the output. Following a shutdown, a logic high signal
re-enables the output through initiation of a new
softstart cycle. Left open, this pin is pulled up by an
Under-Voltage Protection (UVP)
The APL5913 monitors the voltage on FB pin after
soft-start process is finished. Therefore the UVP is
disable during soft-start. When the voltage on FB pin
falls below the under-voltage threshold, the UVP
circuit shuts off the output immediately. After a while,
the APL5913 starts a new soft-start to regulate output.
internal current source (10µA typical) to enable
operation. It’s not necessary to use an external transistor
to save cost.
Power-OK and Delay
The APL5913 indicates the status of the output voltage
by monitoring the feedback voltage (VFB) on FB pin.
As the VFB rises and reaches the rising Power-OK
threshold (VPOK), an internal delay function starts to
perform a delay time. At the end of the delay time, the
IC turns off the internal NMOS of the POK to indicate
the output is OK. As the VFB falls and reaches the
falling Power-OK threshold (VPNOK), the IC immediately
turns on the NMOS of the POK to indicate the output
is not OK without a delay time.
Thermal Shutdown
A thermal shutdown circuit limits the junction temperature
of APL5913. When the junction temperature exceeds
+150°C, a thermal sensor turns off the output NMOS,
allowing the device to cool down. The regulator regulates
the output again through initiation of a new soft-start
cycle after the junction temperature cools by 50°C,
resulting in a pulsed output during continuous thermal
overload conditions. The thermal shutdown designed
Application Information
Output Capacitor
The APL5913 requires a proper output capacitor to
maintain stability and improve transient response over
temperature and current. The output capacitor selection
is to select proper ESR(equivalent series resistance)
and capacitance of the output capacitor for good stability
and load transient response.
Power Sequencing
The power sequencing of VIN and VCNTL is not necessary
to be concerned. But do not apply a voltage to VOUT
for a long time when the main voltage applied at VIN is
not present. The reason is the internal parasitic diode
from VOUT to VIN conducts and dissipates power
without protections due to the forward-voltage.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - May., 2005
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APL5913
Application Information (Cont.)
Output Capacitor (Cont.)
Feedback Network
The APL5913 is designed with a programmable
feedback compensation adjusted by an external
feedback network for the use of wide ranges of ESR
and capacitance in all applications. Ultra-low-ESR
capacitors (such as ceramic chip capacitors), low-ESR
bulk capacitors (such as solid Tantalum, POSCap, and
Aluminum electrolytic capacitors) all can be used as
an output capacitor. The value of the output capacitors
can be increased without limit.
Figure 1 shows the feedback network between VOUT,
GND and FB pins. It works with the internal error
amplifier to provide proper frequency response for the
linear regulator. The ESR is the equivalent series
resistance of the output capacitor. The COUT is ideal
capacitance in the output capacitor. The VOUT is the
setting of the output voltage.
APL5913
R1
ESR
C OUT
VFB
EAMP
VREF
R2
Figure 1
The feedback network selection depends on the values
of the ESR and COUT, which has been classified into
three conditions:
Input Capacitor
• Condition 1 : Large ESR ( ≥18mΩ )
- Select the R1 in the range of 400Ω ~ 2.4kΩ
- Calculate the R2 as the following :
The APL5913 requires proper input capacitors to supply current surge during stepping load transients to
prevent the input rail from dropping . Because the
parasitic inductor from the voltage sources or other
bulk capacitors to the VIN pin limit the slew rate of the
surge currents. More parasitic inductance needs more
input capacitance.
R2(kΩ ) = R1(kΩ) ⋅
0.8(V)
.......... (1)
VOUT(V) - 0.8(V)
- Calculate the C1 as the following :
10 ⋅
Ultra-low-ESR capacitors, such as ceramic chip
capacitors, are very good for the input capacitors An
aluminum electrolytic capacitor (>100mF, ESR
<300mW) is recommended as the input capacitor. It
is not necessary to use low-ESR capacitors. More
capacitance reduce the variations of the input voltage
of VIN pin.
Rev. A.4 - May., 2005
C1
FB
V ERR
Decoupling ceramic capacitors must be placed at the
load and ground pins as close as possible and the
impedance of the layout must be minimized.
Copyright  ANPEC Electronics Corp.
VOUT
VOUT
During load transients, the output capacitors,
depending on the stepping amplitude and slew rate of
load current, are used to reduce the slew rate of the
current seen by the APL5913 and help the device to
minimize the variations of output voltage for good
transient response. For the applications with large
stepping load current, the low-ESR bulk capacitors
are normally recommended.
VOUT(V)
VOUT(V)
...... (2)
≤ C1(nF) ≤ 40 ⋅
R1(kΩ )
R1(kΩ )
• Condition 2 : Middle ESR
- Calculate the R1 as the following:
R1(kΩ) =
13
2157
− 37.5 ⋅ VOUT(V) + 15 ......... (3)
ESR(mΩ)
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APL5913
Application Information (Cont.)
Feedback Network (Cont.)
If the C1 (calculated) can not meet the equation (8),
please use the Condition 2.
Select a proper R1(selected) to be a little larger
than the calculated R1.
- Calculate the C1 as the following :
- Use equation (2) to calculate the R2.
The reason to have three conditions described above
is to optimize the load transient responses for all kinds
of the output capacitor. For stability only, the Condition
2, regardless of equation (5), is enough for all kinds of
output capacitor.
COUT(uF)
C1(pF) = [0.71⋅ ESR(mΩ ) + 101] ⋅
........ (4)
R1(kΩ )
Where R1=R1(selected)
Select a proper C1(selected) to be a little smaller
than the calculated C1.
- The C1 calculated from equation (4) must meet
the following equation:
C1 (pF)
PCB Layout Considerations (See Figure 2)
1. Please solder the Exposed Pad and VIN together
on the PCB. The main current flow is through the
exposed pad. Refer Figure 3 to make a proximate
topology.
143  
37.5 ⋅ V OUT(V) 

⋅ 1 +
≥ 7.2 ⋅ 1 +

 .. (5)
R1 (k Ω )
 ESR (m Ω )  

Where R1=R1(calculated) from equation (3)
2. Please place the input capacitors for VIN and
VCNTL pins near pins as close as possible.
If the C1(calculated) can not meet the equation
(5), please use the Condition 3.
3. Ceramic decoupling capacitors for load must be
placed near the load as close as possible.
- Use equation (2) to calculate the R2.
• Condition 3 : Low ESR (eg. Ceramic Capacitors)
4. To place APL5913 and output capacitors near the
load is good for performance.
- Calculate the R1 as the following:
5. The negative pins of the input and output capacitors and the GND pin of the APL5913 are connected
to the ground plane of the load.
R1(kΩ) = (2.1⋅ ESR(mΩ) + 300)⋅ COUT(uF) − 37.5 ⋅ VOUT(V) .. (6)
Select a proper R1(selected) to be a little larger
than the calculated R1. The minimum selected
R1 is equal to 1kΩ when the calculated R1 is
smaller than 1k or negative.
- Calculate the C1 as the following :
6. Please connect PIN 3 and 4 together by a wide
track.
7. Large current paths must have wide tracks.
8. See the Typical Application
 37.5 ⋅ VOUT(V)
C1(pF) = (0.24⋅ ESR(mΩ) + 34.2)⋅ COUT(uF) ⋅ 1+
.. (7) (see next page Figure 2)
R1(kΩ) 

- Connect the one pin of the R2 to the GND of
APL5913
Where R1=R1(selected)
Select a proper C1(selected) to be a little smaller
than the calculated C1.
- The C1 calculated from equation (7) must meet
the following equation :
- Connect the one pin of R1 to the Pin 3 of APL5913
- Connect the one pin of C1 to the Pin 3 of APL5913
1.25 ⋅ V OUT(V) 

C1 (pF) ≥ 0.033 +
 ⋅ ESR (m Ω ) ⋅ C OUT(uF) .. (8)
R1 (k Ω )


Where R1=R1(calculated) from equation (6)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - May., 2005
14
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APL5913
Application Information (Cont.)
PCB Layout Considerations (Cont.)
VC N T L
C CNTL
CIN
VCNTL
VIN
VIN
A PL5913
VOUT
VOUT
C OUT
VOUT
C1
R1
FB
Load
GND
R2
Figure 2
Thermal Considerations
See Figure 3. The SOP-8-P is a cost-effective package
featuring a small size like a standard SOP-8 and a
bottom exposed pad to minimize the thermal resistance
of the package, being applicable to high current
applications. The exposed pad must be soldered to
the top VIN plane. The copper of the VIN plane on the
Top layer conducts heat into the PCB and air. Please
enlarge the area to reduce the case-to-ambient resistance
(θ CA).
10 2 m i l
118 mil
1
8
2
7
3
SOP-8-P
Top
VOUT
plane
6
5
4
Die
E xposed
Pad
Top
VIN
plane
Ambient
Air
PCB
Figure 43
Figure
Copyright  ANPEC Electronics Corp.
Rev. A.4 - May., 2005
15
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APL5913
Packaging Information
E
E1
0.015X45
SOP-8-P pin ( Reference JEDEC Registration MS-012)
H
D1
e1
e2
D
A1
A
L
0.004max.
Dim
1
Millimeters
Inches
Min.
Max.
Min.
Max.
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.004
0.010
D
4.80
5.00
0.189
3.00REF
D1
E
3.80
E1
0.197
0.118REF
4.00
0.150
2.60REF
0.157
0.102REF
H
5.80
6.20
0.228
0.244
L
0.40
1.27
0.016
0.050
e1
0.33
0.51
0.013
0.020
e2
1.27BSC
0.50BSC
φ 1
8°
8°
Copyright  ANPEC Electronics Corp.
Rev. A.4 - May., 2005
16
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APL5913
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
Critical Zone
T L to T P
Temperature
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25 °C to Peak
Time
Classificatin Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (T L)
- Time (tL)
Peak/Classificatioon Temperature (Tp)
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
217°C
60-150 seconds
See table 1
See table 2
10-30 seconds
20-40 seconds
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25°C to Peak Temperature
Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - May., 2005
17
(mm)
www.anpec.com.tw
APL5913
Classification Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process – Package Peak Reflow Temperature s
Package Thickness
Volume mm 3
Volume mm 3
<350
≥350
<2.5 mm
240 +0/-5°C
225 +0/-5°C
≥2.5 mm
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Package Thickness
Volume mm 3
Volume mm 3
Volume mm 3
<350
350-2000
>2000
<1.6 mm
260 +0°C*
260 +0°C*
260 +0°C*
1.6 mm – 2.5 mm
260 +0°C*
250 +0°C*
245 +0°C*
≥2.5 mm
250 +0°C*
245 +0°C*
245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and
including the stated classification temperature (this means Peak reflow temperature +0°C.
For example 260°C+0°C) at the rated MSL level.
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B,A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C, 5 SEC
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
Carrier Tape & Reel Dimensions
t
D
P
Po
E
P1
Bo
F
W
Ko
Ao
Copyright  ANPEC Electronics Corp.
Rev. A.4 - May., 2005
D1
18
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APL5913
Carrier Tape & Reel Dimensions(Cont.)
T2
J
C
A
B
T1
Application
SOP- 8/-P
A
B
C
J
330 ± 1
62 +1.5
12.75+ 0.15
2 ± 0.5
F
D
D1
Po
5.5± 1
1.55 +0.1
1.55+ 0.25
4.0 ± 0.1
T1
T2
12.4 ± 0.2 2 ± 0.2
P1
Ao
W
P
E
12± 0. 3
8± 0.1
1.75±0.1
Bo
Ko
t
2.0 ± 0.1 6.4 ± 0.1 5.2± 0. 1 2.1± 0.1 0.3±0.013
(mm)
Cover Tape Dimensions
Application
SOP- 8/-P
Carrier Width
12
Cover Tape Width
9.3
Devices Per Reel
2500
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright  ANPEC Electronics Corp.
Rev. A.4 - May., 2005
19
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