APU0065 PRELIMINARY 40 CH Driver for Dot Matrix LCD FEATURES APPLICATIONS • Display driving bias ; static-1/5 • • Power supply voltage ; VDD= +5V ± 10% Dot matrix LCD driver with 40 channel output. • VDD= +3V ± 10% Selectable function to use Common / Segment • Supply voltage range for display : ≤ 10V • Negative display voltage : • Input / Output signal 0 ≥ VEE ≥ VDD - 10V • Output ; 20 × 2 channel waveform for LCD • drivers simultaneously. Interface driving Driver (cascade connection) Other APU0065 • Controller APU0066 Input ; - Serial display data and control pulse from the controller LSI . GENERAL DESCRIPTION • Bias voltage (V1 - V6) • QFP64 and bare chip available The APU0065 is a LCD driver LSI that is fabricated by low power CMOS technology. Basically this LSI consists of 20 × 2bit bi-directional shift register, 20 × 2bit data latch and 20 × 2bit driver. This LSI can be CMOS Process used a Common or Segment driver. ORDERING INFORMATION APU0065 E Package Type Q : QFP Y : Chip Handling Code Handling Code TY : Tray Package Type ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 1 www.anpec.com.tw APU0065 PRELIMINARY SC1~SC20 V3 V 1S End Stage Output Voltage Multiplexor Part1 V4 V1 V2 Pre-Stage Output Voltage Multiplexor Part1 V 2S SC21~SC40 V6 V 3S Pre-Stage Output Voltage Multiplexor Part2 M_1_20 PART 1 V5 End Stage Output Voltage Multiplexor Part2 V 4S M_21_40 PART 2 latch clock_1_20 LATCH Part1 register clock_1_20 SHIFT Part 1 CL1 DR1 CL2 M LATCH Part 2 register clock_21_40 Common/Segment Mode Control Signal Convert Part DL1 SHL1 latch clock_21_40 DR2 SHIFT Part 2 SHL2 DL2 FCS Figure 1. Block diagram of APU0065 SC40 52 SC39 53 SC38 54 SC37 55 SC36 56 SC35 57 V6 V5 V4 V3 V2 V1 FCS 51 50 49 48 47 46 45 58 SC30 59 SC31 60 SC32 61 SC33 62 SC34 63 SHL2 SHL1 44 M 43 42 DR2 DL2 DR1 DL1 V SS CL2 CL1 VEE 40 39 38 37 36 35 34 33 41 APU0065 32 SC1 31 SC2 30 SC3 29 SC4 28 SC5 27 SC6 26 25 V DD 24 SC7 23 SC8 22 SC11 21 SC10 20 SC9 64 1 2 SC29 3 4 5 6 7 8 9 10 SC28 SC27 SC26 SC25 SC24 SC23 SC22 SC21 11 12 13 14 15 16 17 18 19 SC20 SC19 SC18 SC17 SC16 SC15 SC14 SC13 SC12 Figure 2. QFP 64 Top View Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 2 www.anpec.com.tw APU0065 PRELIMINARY PIN DESCRIPTION-QFP100 PAD (NO.) INPUT/ OUTPUT V EE (33) Power Negative Supply Voltage V D D (25) Power V SS (36) V 1 ~ V6 (46 ~ 51) NAME DESCRIPTION INTERFACE For LCD driver circuit(0 ≥ VEE Operating Voltage ≥ V DD - 1 0 V) For logical circuit (+5V ± 10%, +3V± 10%) Power Supply Power Operating Voltage 0V (GND) Power Supply Input Bias Voltage Bias Voltage level for LCD drive Power Supply M (42) Input Altemated signal for LCD driver output This is the signal for LCD twisting Controller CL1, CL2 (34, 35) Input Data shift / latch clock These signal control the shift and latch of driver. More detail scription in next lineF C S. Controller Power Supply If FCS equals to VSS , Part1 and Part2 both are segment mode. If FCS equals to VDD , Part1 is segment mode but Part2 is common mode . FCS (45) Input Mode selection Mode CL1 CL2 M Segment latch shift M Common shift latch M Controller Selection of the shift directon of Part 1 shift register SHL1 (43) Input Shifting direction control signal of Part1 SHL1 DL1 DR1 VDD output input V SS input output DL1, DR1 (37, 38) Input Output Data interface Data input / output of Part1 shift register SC1 ~ SC20 Output LCD driver LCD driver output of Part1 Controller Controller or APU0063 LCD Selection of the shift directon of Part 2 shift register SHL2 (44) Input Shifting direction control signal of Part2 SHL2 DL2 DR2 VDD output Input V SS Input output DL2, DR2 (39, 40) Input Output Data interface Data input / output of Part 2 shift register SC21 ~ SC40 Output LCD driver LCD driver output of Part2 Controller Controller or APU0063 LCD Note : Input pin can not be floated, or it will cause large leakage current. Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 3 www.anpec.com.tw APU0065 PRELIMINARY SEGMENT MODE COMMON MODE When Part1 or Part2 be selected to work in segment mode (FCS pin = VSS), these are the liquid crystal segment drive outputs. A signal of driving pin in segment mode is the one of V1, V2, V3 or V4. These selecting are following. Only Part2 can be selected to work in common mode (FCS pin = VDD). These are the liquid crystal common drive outputs signal of driving pin in segment mode is the one of V1, V2,, V5 or V6. These selecting are following. Data of latch High High Low Low M High Low High Low Output voltage V1 V2 V3 V4 Data of latch High High Low Low M High Low High Low Output voltage V2 V1 V6 V5 SHIFT DIRECTION SPECIFICATION Part1 Part2 When Part1 shift direction control signal, SHL1, is set to VSS. Now the Part1 register shift direction is DL1 → SC1 → SC2 → . . . → SC19 → SC20 → DR1 Otherwise,when SHL1 is set to VDD.Its direction is DL1 ← SC1 ← SC2 ← . . . ← SC19 ← SC20 ← DR1 When Part2 shift direction control signal, SHL2, is set to VSS. Now the Part1 register shift direction is DL2 → SC21 → SC22 → . . . → SC39 → SC40 → DR2 Otherwise,when SHL2 is set to VDD.Its direction is DL2 ← SC21 ← SC22 ← . . . ← SC39 ← SC40 ← DR2 MAXIMUM ABSOLUTE LIMIT (Ta = 25 °C) Symbol Value Unit Operating Voltage VDD -0.3 ~ +7.0 V Driver Supply Voltage V LCD Input Voltage 1 V IN1 -0.3 ~ VD D +0.3 V Input Voltage 2 (V1 ~ V 6 ) V IN2 V D D +0.3 ~ VE E -0.3 V Operating Temperature T OPR -30 ~ +85 o C Storage Temperature T STG -55 ~ +125 o C Characteristic Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 V D D -13.5 ~ VD D +0.3 4 V www.anpec.com.tw APU0065 PRELIMINARY ELECTRICAL CHARACTERISTICS DC characteristics (VDD = 2.7 ~ 5.5V, 0 ≥ VEE ≥ VDD - 10V, VSS = 0V, Ta = -30 ~ +85 °C) Characteristic Symbol Test condition Min Max Unit Operating Current* IDD f CL2 = 4 0 0 K H z _ 1 mA Supply Current* I EE f CL1 = 1KHz _ 10 µA Input High Voltage V IH 0.7 V D D V DD 0 0.2 V D D Input Low Voltage V IL Input Leakage Current I LKC _ V IN = 0 - V D D -5 5 _ 0.4 Output High Voltage V OH I OH = -0.4mA V DD - 0.4 Output Low Voltage V OL I OL = +0.4mA _ V D1 I O N = 0.1mA for one of SC1 ~ SC40 V D2 IO N = 0.05mA for each SC1 ~ SC40 IV V IN = V DD ~ V EE (Output SC1 ~ SC40 : floating) Voltage Descending Leakage Current V µA Applicable pin _ CL1, CL2, DR1, DR2, DR1, DR2, SHL1, SHL2, M, FCS DL1, DL2, DR1, DR2 V _ 1.1 _ 1.5 -10 10 V ( V1 ~ V6 ) SC ( SC1 ~ SC40 ) µA V 1 ~ V6 AC characteristics (VDD = 2.7 ~ 5.5V, 0 ≥ VEE ≥ VDD - 10V, VSS = 0V, Ta = -30 ~ +85 °C) Characteristic Symbol Test condition Min Max Unit Applicable pin _ 400 KHz CL2 f CL _ Clock High Level Width tW C K H _ 800 _ Clock Low Level Width tWCKL _ 800 _ t SL from CL2 to CL1 500 _ t LS from CL1 to CL2 500 _ Data shift Frequency Clock Set-up Time tR / tF _ 200 Data Set-up Time t SU _ 300 _ Data Hold Time tDH _ Data Delay Time tD Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 300 _ 5 CL2 CL1,CL2 ns _ Clock Rise / Fall Time CL1,CL2 _ 600 DL1,DL2,DR1,DR2,FLM DL1,DL2,DR1,DR2 www.anpec.com.tw APU0065 PRELIMINARY TIMING CHARACTERISTICS V IH V IH tWCKL CL2 V IL V IL tW C K H tR tF tD H tS U Data in (DL1,DL2) (DR1,DR2) V IH V IL tSL tD Data out (DR1,DR2) (DL1,DL2) tLS tLS V OH V OL V IH V IL CL1 tR tW C K H tSU tF V IH FLM V IL Figure 3. Timing diagram of signals Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 6 www.anpec.com.tw APU0065 PRELIMINARY FUNCTIONAL DESCRIPTION 1) Segent mode M CL1 Latch Shift CL2 DL1 / DR1 DL2 / DR2 SC1 SC2 SC39 SC40 OUTPUT OF LATCH (SC) SC1~SC40 When the FCS is connected to VSS, APU0065 (SC1 ~ SC40) is operated as segment driver. (refer to figure 5) Figure 4. timing diagram of Segment mode 2) Common mode DL2 / DR2 M Shift CL1 Latch CL2 OUTPUT OF LATCH (SC) SC21~SC40 When the FCS is connected to VDD, only part2 (SC21 ~ SC40) of APU0065is operated as common driver. (refer to figure 6.) Figure 5. timing diagram of Common mode Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 7 www.anpec.com.tw APU0065 PRELIMINARY FCS OUTPUT OF LATCH (DATA) M V2 V2 V4 V4 V3 V3 PART 1 (SC1 ~ SC20) V1 V1 V2 V2 V5 V5 PART 2 (SC21 ~ SC40) V6 V6 V1 V1 Note : When fcs equals to high voltage, PART 2 (SC21 ~ SC40) is operated as LCD Common driver. PART 1 (SC1 ~ SC20) always be operated as LCD segment driver, no matter fcs equals to high or low Figure 6. SC1 ~ SC40 output waveform Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 8 www.anpec.com.tw APU0065 PRELIMINARY APPLICATION CIRCUIT 1. Segment driver COM1 ~ COM16 APU0066 (controller) M CLK2 LCD common signal CLK1 SHL1 SHL2 FCS D DL1 DR1 DL2 SC1~SC40 APU0065 (Seg driver) CL1 CL2 SHL1 SHL2 FCS DR2 DL1 DR1 M DL2 SC1~SC40 APU0065 (Seg driver) CL1 CL2 DR2 M OPEN 2. Segment / Common driver Common signal LCD Segment signal Controller SC21~SC40 D FLM M CL1 DL1 DL2 CL2 V DD SC1~SC20 APU0065 (Seg / Com driver) FCS SHL1 SHL2 CL2 CL1 FCS SHL1 SHL2 DR1 DL1 DR1 M DL2 SC1~SC40 DR2 OPEN APU0065 (Seg driver) CL2 CL1 M Figure 7. Connection between APU0065 and Controller Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 9 www.anpec.com.tw PRELIMINARY APU0065 SC9 19 SC12 13 12 11 10 9 8 7 6 5 4 SC13 SC14 SC15 SC16 SC17 SC18 SC19 SC20 SC21 SC22 SC23 SC24 SC25 SC26 14 3 SC27 2 SC28 SC34 15 60 SC33 16 59 SC32 17 58 SC31 18 57 SC30 SC29 56 SC35 1 22 55 SC36 S C 1 0 20 SC8 23 54 SC37 new pad coordinate of SC7 24 53 SC38 SC3 SC4 SC5 29 28 27 S C 1 1 21 V DD 25 52 SC39 SC2 30 Chip size : Pad size : Pitch length Unit : 34 DL1 35 DR1 36 DL2 37 DR2 38 M 40 (0.0) 2010 × 1670 80 × 80 : 100 µm 41 42 SHL1 SHL2 FCS 43 V1 44 V2 45 V3 46 V4 47 V5 48 V6 49 (0.0) is the center of the chip 33 VSS www.anpec.com.tw 10 Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 APU0065 SC6 26 51 SC40 SC1 31 32 CL2 V6 50 V EE CL1 Figure 8. Chip pad arrangement APU0065 PRELIMINARY PAD LOCATION PAD NUMBER PAD NAME COORDINATE X Y PAD NUMBER PAD NAME COORDINATE X Y 1 SC29 902.5 630.0 31 V EE -902.5 -630.0 2 SC28 850.0 732.5 32 CL1 -800.0 -722.5 3 SC27 725.0 732.5 33 CL2 -700.0 -732.5 4 SC26 600.0 732.5 34 V SS -600.0 -732.5 5 SC25 500.0 732.5 35 DL1 -500.0 -732.5 6 SC24 400.0 732.5 36 DR1 -400.0 -732.5 7 SC23 300.0 732.5 37 DL2 -300.0 -732.5 8 SC22 200.0 732.5 38 DR2 -200.0 -732.5 9 SC21 100.0 732.5 40 M -100.0 -732.5 10 SC20 0.0 732.5 41 SHL1 0.0 -732.5 11 SC19 -100.0 732.5 42 SHL2 100.0 -732.5 12 SC18 -200.0 732.5 43 FCS 200.0 -732.5 13 SC17 -300.0 732.5 44 V1 315.0 -732.5 14 SC16 -400.0 732.5 45 V2 430.0 -732.5 15 SC15 -500.0 732.5 46 V3 545.0 -732.5 16 SC14 -600.0 732.5 47 V4 660.0 -732.5 17 SC13 -725.0 732.5 48 V5 775.0 -732.5 18 SC12 -850.0 732.5 49 V6 905.0 -632.5 19 SC9 -902.5 630.0 50 SC40 902.5 -525.0 20 SC10 -902.5 525.0 51 SC39 902.5 -420.0 21 SC11 -902.5 420.0 52 SC38 902.5 -315.0 22 SC8 -902.5 315.0 53 SC37 902.5 -210.0 23 SC7 -902.5 210.0. 54 SC36 902.5 -105.0 24 V DD -902.5 105.0 55 SC35 902.5 0.0 25 SC6 -902.5 0.0 56 SC30 902.5 105.0 26 SC5 -902.5 -105.0 57 SC31 902.5 210.0 27 SC4 -902.5 -210.0 58 SC32 902.5 315.0 28 SC3 -902.5 -315.0 59 SC33 902.5 420.0 29 SC2 -902.5 -420.0 60 SC34 902.5 525.0 30 SC1 -902.5 -525.0 Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 11 www.anpec.com.tw