APW6021 Advanced PWM and Triple Linear Power Controllers Functional Applications • • Motherboard Power Regulation for Computers 4 Regulated Voltages are provided • Microprocessor Core (1.3V to 3.5V) General Description • AGP Bus (1.5V or 3.3V) • Memory (1.8V) The APW6021 provides the power control and protection for four output voltages in high-performance, graphics intensive microprocessor and computer applications. The IC integrates voltage-mode PWM controller and three linear controllers, as well as the monitoring and protection functions into a 28-pin SOIC package. The PWM controller regulates the microprocessor core voltage with a synchronous-rectified buck converter. The linear controllers regulate the computer system’s AGP 1.5V or 3.3V bus power, the 1.5V GTL bus power, and the 1.8V power for the North/South Bridge core voltage and/or cache memory circuits. The APW6021 includes an Intelcompatible, TTL 5-input digital-to-analog converter (DAC) that adjusts the core PWM output voltage from 1.3 VDC to 2.05 VDC in 0.05V steps and from 2.1 VDC to 3.5 VDC in 0.1V increments. The precision reference and voltage-mode control provide ±1% static regulation. The AGP bus power linear controller’s output (VOUT2 ) is user-selectable, through a TTL-compatible signal applied at the SELECT pin, for levels of 1.5V or 3.3V with ±3% accuracy. Based on the status of the FIX pin, the other two linear regulators provide either fixed output voltages of 1.5V± 3% (VOUT3 ) and 1.8V±3% (VOUT4 ), or user-adjustable by means of an external resistor divider. All linear controllers can employ either N-channel MOSFETs or bipolar NPNs for the pass transistor. • GTL Bus (1.5V) • Linear Controllers Drives with both MOSFET and Bipolar Series Pass Transistors • Fixed or Externally Resistor-Adjustable Linear Outputs (FIX Pin) • Simple Single-Loop Control Design • Voltage-Mode PWM Control • Fast PWM Converter Transient Response • High-Bandwidth Error Amplifier • Full 0% to 100% Duty Ratio • Excellent Output Voltage Regulation • Core PWM Output: ± 1% Over Temperature • Other Outputs: ± 3% Over Temperature • TTL-Compatible 5- Bit DAC Microprocessor Core Output Voltage Selection • Wide Range - 1.3VDC to 3.5 VDC • • Power-Good Output Voltage Monitor Over-Voltage and Over-Current Fault Monitors • Switching Regulator Does Not Require Extra Current Sensing Element, Uses The APW6021 monitors all the output voltages. A single Power Good signal is issued when the core is within ±10% of the DAC setting and all other outputs are above their under-voltage levels. Additional builtin over-voltage protection for the core output uses the lower MOSFET to prevent output voltages above 115% of the DAC setting. The PWM controller’s overcurrent function monitors the output current by using the voltage drop across the upper MOSFET’s rDS(ON) . MOSFET’s r DS(ON) • Small Converter Size • Constant Frequency Operation • 200kHz Free-Running Oscillator; Programmable From 50kHz to Over 1MHz ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. P.4 - Mar., 2001 1 www.anpec.com.tw APW6021 Pin Description DRIVE2 FIX VID4 VID3 VID2 VID1 VID0 PGOOD SD VSEN2 SELECT SS FAULT/ RT VSEN4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC UGATE PHASE LGATE PGND OCSET VSEN1 FB COMP VSEN3 DRIVE3 GND VAUX DRIVE4 Ordering Information Package Code K : SO P - 28 Tem p. Range C : 0 to 7 0 ° C H a n d lin g C o d e TU : Tube TR : Tape & Reel L e a d F re e C o d e L : L e a d F re e D e v ic e B la n k : O rig in a l D e v ic e APW 6021 L e a d F re e C o d e H a n d lin g C o d e Tem p. Range Package Code Absolute Maximum Ratings Symbol VCC VBOOT –VPHASE VI , VO Parameter Rating Unit Supply Voltage 15 V Boot Voltage 15 V GND -0.3 V to VCC +0.3 V Input , Output or I/O Voltage TA Operating Ambient Temperature Range 0 to 70 °C TJ Junction Temperature Range 0 to 125 °C TSTG Storage Temperature Range -65 to +150 °C 300 ,10 seconds °C TS Soldering Temperature Copyright ANPEC Electronics Corp. Rev. P.4 - Mar., 2001 2 www.anpec.com.tw APW6021 Thermal Characteristics Symbol Parameter Thermal Resistance in Free Air SOIC SOIC (with 3in2 of Copper) R θJA Value Unit 75 65 °C/W Block Diagram VSEN3 FIX VSEN1 SD VCC OCSET VAUX DRIVE 4 + - DRIVE3 + - - 200 µA + - × 0.75 + Power-on Reset (POR) × 1.10 + × 0.90 VAUX + LUV - + PGOOD 1.26V LINEAR UNDERVOLTAGE VSEN 4 × 1.15 + VCC OV DRIVE2 - + + - DRIVER1 INHIBIT SOFT START & FAULT LOGIC FAULT + × 0.75 - GATE CONTROL + - - PWM COMP1 OSCILLATOR TTL D/A CONVERTER (DAC) 28µA VCC PWM1 VCC DACOUT SELECT PHASE INHIBIT ERROR AMP1 1.5V or 3.3v + - VSEN2 + UGATE OC1 SYNCH DRIVE LGATE PGND GND 4.5V FAULT/ RT Copyright ANPEC Electronics Corp. Rev. P.4 - Mar., 2001 SS FB 3 COMP VID0 VID1 VID2 VID3 VID4 www.anpec.com.tw APW6021 Electrical Characteristics (Recommended operating conditions, Unless otherwise noted) Refer to Block and Simplified Power System Diagrams, and Typical Application Schematic APW6021 Symbol Parameter Test Conditions Min. Typ. Max. Unit VCC Supply Current ICC Nominal Supply Current UGATE, LGATE, DRIVE2, DRIVE3, and DRIVE4 open 9 mA Power-on Reset Rising VCC Threshold Vocset=4.5V Falling VCC Threshold Vocset=4.5V 10.4 Rising VAUX Threshold Vocset=4.5V 2.5 V VAUX Threshold Hysteresis Vocset=4.5V 0.5 V 1.26 V 8.2 Rising VOCSET Threshold V V Oscillator FOCS ∆VOSC Free Running Frequency RT= Open Ramp Amplitude RT= Open DAC and Bandgap Reference DAC(VID0-VID4) Input Low Voltage DAC(VID0-VID4) Input High Voltage DACOUT Voltage accuracy VBG 185 200 215 1.9 VP-P 0.8 V 2.0 0.8 V -1.0 +1.0 % +2.5 % Bandgap Reference Voltage 1.265 Bandgap Reference Tolerance kHz -2.5 V Linear Regulators (OUT2, OUT3, and OUT4) Regulation (All Linears) 3 % VREG2 VSEN2 Regulation Voltage Select < 0.8V 1.5 V VREG2 VSEN2 Regulation Voltage Select > 2.0V 3.3 V VREG3 VSEN3 Regulation Voltage 1.5 V VREG4 VSEN4 Regulation Voltage Under-Voltage Level (VSEN/ VSEN Rising VRENUV VREG) Under-Voltage Hysteresis (VSEN/ VSEN Falling VREG) Output Drive Current (All Liners) VAUX-VDRIVE >0.6V 1.8 V 75 % 7 % 40 mA Copyright ANPEC Electronics Corp. Rev. P.4 - Mar., 2001 4 20 www.anpec.com.tw APW6021 Electrical Characteristics Cont. APW6021 Symbol Parameter Test Conditions Min. Typ. Max. Unit Synchronous PWM Controller Error Amplifier DC Gain 88 dB 15 MHz COMP=10pF 6 V/µs VCC=12V, VUGATE =6V 1 A GBWP Gain-Bandwidth Product SR Slew Rate PWM Controller Gate Driver IUGATE UGATE Source RUGATE UGATE Sink VUGATE1-PHASE =1V ILGATE LGATE Source VCC=12V, VLGATE =1V RLGATE LGATE Sink VLGATE= 1V Protection VSEN1 Over-Voltage (VSEN1/DACOUT) IOVP FAULT Souring Current IOCSET ISS OCSET1 Current Source 115 VFAULT/RT=2.0V 8.5 170 Soft Start Current Power Good VSEN1 Upper Threshold (VSEN1/DACOUT) VSEN1 Under Voltage (VSEN1/DACOUT) VSEN1 Hysteresis (VSEN1 /DACOUT) VPGOOD PGOOD Voltage Low Ω A 3 Ω 120 % 1 VSEN1 Rising VOCSET= 4.5VDC 3.5 200 mA 230 µA µA 28 VSEN1 Rising 108 110 % VSEN1 Rising 92 94 % Upper /Lower Threshold 2 IPGOOD= -4mA % 0.8 V Functional Pin Description DRIVE2 (Pin 1) nal resistor divider connected at the corresponding VSEN pin. The new output voltage set by the external resistor divider can be determined using the following formula: Connect this pin to the gate of an external MOSFET. This pin provides the drive for the AGP regulator’s pass transistor. VOUT =1.265V × [1+ROUT/ RGND ] FIX (Pin 2) where R OUT is the resistor connected from VSEN to the output of the regulator, and RGND is the resistor connected from VSEN to ground. Left open, the FIX pin is pulled high, enabling fixed output voltage operation. Grounding this pin bypasses the internal resistor dividers that set the output voltage of the 1.5V and 1. 8V linear regulators. This way, the output voltage of the two regulators can be adjusted from 1.26V up to the input voltage (+3.3V or +5V) by way of an exter- Copyright ANPEC Electronics Corp. Rev. P.4 - Mar., 2001 5 www.anpec.com.tw APW6021 Functional Pin Description Cont. VID4, VID3, VID2, VID1, VID0 (Pins 3, 4, 5, 6 and 7) SS (Pin 12) VID0-4 are the TTL-compatible input pins to the 5-bit DAC. The logic states of these five pins program the internal voltage reference (DACOUT). The level of DACOUT sets the microprocessor core converter output voltage, as well as the corresponding PGOOD and OVP thresholds. Connect a capacitor from this pin to ground. This capacitor, along with an internal 28µA current source, sets the soft-start interval of the converter. FAULT / RT (Pin 13) This pin provides oscillator switching frequency adjustment. By placing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased according to the following equation: PGOOD (Pin 8) PGOOD is an open collector output used to indicate the status of the output voltages. This pin is pulled low when the synchronous regulator output is not Fs =200kHz + 5 × 10 6 / RT (kΩ) (RT to GND) within ±10% of the DACOUT reference voltage or when any of the other outputs are below their undervoltage thresholds. Conversely, connecting a resistor from this pin to VCC reduces the switching frequency according to the following equation: Fs =200kHz + 4 × 10 7 / RT (kΩ) (RT to 12V) The PGOOD output is open for“11111” VID code. Nominally, the voltage at this pin is 1.26V. In the event of an over-voltage or over-current condition, this pin is internally pulled to VCC. SD (Pin 9) This pin shuts down all the outputs. A TTLcompatible, logic level high signal applied at this pin immediately discharges the soft-start capacitor, disabling all the outputs. Dedicated internal circuitry insures the core output voltage does not go negative during this process. When re-enabled, the IC undergoes a new soft-start cycle. Left open, this pin is pulled low by an internal pull-down resistor, enabling operation. VSEN4 (Pin 14) Connect this pin to the output of the linear 1.8V regulator. This pin is monitored for undervoltage events. DRIVE4 (Pin 15) Connect this pin to the gate of an external MOSFET. This pin provides the drive for the 1.8V regulator’s pass transistor. VSEN2 (Pin 10) Connect this pin to the output of the AGP linear regulator. The voltage at this pin is regulated to the level predetermined by the logic-level status of the SELECT pin. This pin is also monitored for undervoltage events. VAUX (Pin 16) This pin provides boost current for the linear regulators’ output drives in the event bipolar NPN transistors (instead of N-channel MOSFETs) are employed as pass elements. The voltage at this pin is monitored for power-on reset (POR) purposes. SELECT (Pin 11) This pin determines the output voltage of the AGP bus linear regulator. A low TTL input sets the output voltage to 1.5V, while a high input sets the output voltage to 3.3V. Copyright ANPEC Electronics Corp. Rev. P.4 - Mar., 2001 GND (Pin 17) Signal ground for the IC. All voltage levels are measured with respect to this pin. 6 www.anpec.com.tw APW6021 Functional Pin Description Cont. DRIVE3 (Pin 18) LGATE (Pin 25) Connect this pin to the gate of an external MOSFET. This pin provides the drive for the 1.5V regulator’s pass transistor. Connect LGATE to the PWM converter’s lower MOSFET gate. This pin provides the gate drive for the lower MOSFET. VSEN3 (Pin 19) PHASE (Pin 26) Connect this pin to the output of the 1.5V linear regulator. This pin is monitored for under-voltage events. Connect the PHASE pin to the PWM converter’s upper MOSFET source. This pin represents the gate drive return current path and is used to monitor the voltage drop across the upper MOSFET for over-current protection. COMP and FB (Pin 20, and 21) COMP and FB are the available external pins of the PWM converter error amplifier. The FB pin is the inverting input of the error amplifier. Similarly, the COMP pin is the error amplifier output. These pins are used to compensate the voltage-mode control feedback loop of the synchronous PWM converter. UGATE (Pin 27) Connect UGATE pin to the PWM converter’s upper MOSFET gate. This pin provides the gate drive for the upper MOSFET. VCC (Pin 28) VSEN1 (Pin 22) Provide a 12V bias supply for the IC to this pin. This pin also provides the gate bias charge for all the MOSFETs controlled by the IC. The voltage at this pin is monitored for Power-On Reset (POR) purposes. This pin is connected to the PWM converter’s output voltage. The PGOOD and OVP comparator circuits use this signal to report output voltage status and for over- voltage protection. OCSET (Pin 23) Connect a resistor from this pin to the drain of the respective upper MOSFET. This resistor, an internal 200µA current source, and the upper MOSFET’s onresistance set the converter over-current trip point. An over-current trip cycles the soft-start function. The voltage at this pin is monitored for power-on reset (POR) purposes and pulling this pin low with an open drain device will shutdown the IC. PGND (Pin 24) This is the power ground connection. Tie the synchronous PWM converter’s lower MOSFET source to this pin. Copyright ANPEC Electronics Corp. Rev. P.4 - Mar., 2001 7 www.anpec.com.tw APW6021 Table 1 Output Voltage Program Pin Name Pin Name VID4 VID3 VID2 VID1 VID0 Nominal Output Voltage Dacout VID4 VID3 VID2 VID1 VID0 Nominal Output Voltage Dacout 0 1 1 1 1 1.3 1 1 1 1 1 0 0 1 1 1 0 1.35 1 1 1 1 0 2.1 0 0 1 1 1 1 0 0 1 0 1.4 1.45 1 1 1 1 1 1 0 0 1 0 2.2 2.3 0 1 0 1 1 1.5 1 1 0 1 1 2.4 0 1 0 1 0 1.55 1 1 0 1 0 2.5 0 1 0 0 1 1.6 1 1 0 0 1 2.6 0 0 1 0 0 1 0 1 0 1 1.65 1.7 1 1 1 0 0 1 0 1 0 1 2.7 2.8 0 0 1 1 0 1.75 1 0 1 1 0 2.9 0 0 0 0 1 1 0 0 1 0 1.8 1.85 1 1 0 0 1 1 0 0 1 0 3.0 3.1 0 0 0 1 1 1.90 1 0 0 1 1 3.2 0 0 0 1 0 1.95 1 0 0 1 0 3.3 0 0 0 0 0 0 0 0 1 0 2.00 2.05 1 1 0 0 0 0 0 0 1 0 3.4 3.5 Simplified Power System Diagram + 5 V IN Q1 + 3 . 3 V IN Q3 Linear Controller V OUT2 PWM Controller V OUT1 Q2 APW6021 Q4 V OUT3 Linear Controller Linear Controller Q5 V OUT4 Copyright ANPEC Electronics Corp. Rev. P.4 - Mar., 2001 8 www.anpec.com.tw APW6021 Typical Application +12V IN +5V IN L IN C IN VCC OCSET +3.3V IN POWER GOOD PGOOD Q3 V OUT2 1.5V or 3.3V DRIVE2 UGATE VSEN2 PHASE LGATE SELECT APW6021 VAUX V OUT1 Q2 C OUT1 PGND VSEN1 FB DRIVE3 Q4 LOUT1 1.3V to 3.5V C OUT2 TYPEDET Q1 COMP V OUT3 1.5V VSEN3 C OUT3 FIX Q5 FAULT/ RT VID0 VID1 VID2 VID3 VID4 DRIVE4 V OUT4 1.8V VSEN4 SS C OUT4 C SS Copyright ANPEC Electronics Corp. Rev. P.4 - Mar., 2001 GND 9 www.anpec.com.tw APW6021 Package Information SO – 300mil ( Reference JEDEC Registration MS-013) D N H GAUGE PLANE E 1 2 3 A Millimeters 1 A1 B e L Variations- D Inches Variations- D Dim Min. Max. Variations Min. Max. Dim Min. Max. Variations Min. Max. A 2.35 2.65 SO-16 10.10 10.50 A 0.093 0.1043 SO-16 0.398 0.413 A1 0.10 0.30 SO-18 11.35 11.76 A1 0.004 0.0120 SO-18 0.447 0.463 B 0.33 0.51 SO-20 12.60 13 B 0.013 0.020 SO-20 0.496 0.512 D See variations SO-24 15.20 15.60 D See variations SO-24 0.599 0.614 E 7.40 SO-28 17.70 18.11 E SO-28 0.697 0.713 SO-14 8.80 9.20 e SO-14 0.347 0.362 e 7.60 1.27BSC 0.2914 0.2992 0.050BSC H 10 10.65 H 0.394 0.419 L 0.40 1.27 L 0.016 0.050 N See variations N See variations 0° φ1 φ1 8° Copyright ANPEC Electronics Corp. Rev. P.4 - Mar., 2001 10 0° 8° www.anpec.com.tw APW6021 Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Reflow Condition (IR/Convection or VPR Reflow) tp TP C ritical Z one T L to T P T e m p e ra tu re R am p-up TL tL T sm ax T sm in R am p-down ts Preheat 25 t 25 °C to Peak T im e Classificatin Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Large Body Small Body Average ramp-up rate 3°C/second max. (TL to TP) Preheat - Temperature Min (Tsmin) 100°C - Temperature Mix (Tsmax) 150°C - Time (min to max)(ts) 60-120 seconds Tsmax to TL - Ramp-up Rate Tsmax to TL - Temperature(TL) 183°C - Time (tL) 60-150 seconds Peak Temperature(Tp) 225 +0/-5°C 240 +0/-5°C Time within 5°C of actual Peak 10-30 seconds 10-30 seconds Temperature(tp) Ramp-down Rate 6°C/second max. 6 minutes max. Time 25°C to Peak Temperature Pb-Free Assembly Large Body Small Body 3°C/second max. 150°C 200°C 60-180 seconds 3°C/second max 217°C 60-150 seconds 245 +0/-5°C 250 +0/-5°C 10-30 seconds 20-40 seconds 6°C/second max. 8 minutes max. Note: All temperatures refer to topside of the package. Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. P.4 - Mar., 2001 11 www.anpec.com.tw APW6021 Reliability test program Test item Method Description SOLDERABILITY MIL-STD-883D-2003 245°C , 5 SEC HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @ 125 °C PCT JESD-22-B, A102 168 Hrs, 100 % RH , 121°C TST MIL-STD-883D-1011.9 -65°C ~ 150°C, 200 Cycles ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V Latch-Up JESD 78 10ms , Itr > 100mA Tape & Reel Dimensions t D P Po E P1 Bo F W Ko Ao D1 T2 J C A B T1 Application A B C J T1 T2 W P E SOP- 28 330±1 62 ±1.5 12.75 ± 0. 5 2 ± 0.6 24.4 ± 0.2 2± 0.2 24 ± 0.3 12 ± 0.1 1.75± 0.1 Application F D D1 Po P1 Ao Bo Ko t 1.5+ 0.25 4.0 ± 0.1 SOP- 28 11.5 ± 0.1 1.5 +0.1 2.0 ± 0.1 10.85 ± 0.1 18.34± 0.1 2.97± 0.1 0.35±0.01 (mm) Copyright ANPEC Electronics Corp. Rev. P.4 - Mar., 2001 12 www.anpec.com.tw APW6021 Cover Tape Dimensions Application SOP- 28 Carrier Width 24 Cover Tape Width 21.3 Devices Per Reel 1000 Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright ANPEC Electronics Corp. Rev. P.4 - Mar., 2001 13 www.anpec.com.tw