APW7066 Dual Synchronous Buck PWM Controllers and One Linear Controller Features General Description • The APW7066 has two synchronous buck PWM controllers and one linear controller with high precision internal references voltage to offer accurate outputs. The PWM controllers are designed to drive two N-channel MOSFETs in synchronous buck topology, and the linear controller drives an external N-channel MOSFET. The device requires 12V and 5V power supplies, if the 5V supply is not available, VCC12 can offer an optional shunt regulator 5.8V for 5V supply. • • • • • • • • • • • • • • Two Synchronous Buck Converters and a Linear Regulator VIN range up to 12V Input Power Supplies Require 12V and 5V or use 12V to generate a Shunt Regulator 5.8V 0.6V Reference for VOUT1 and VOUT3 with 0.8% accurate 3.3V Reference for VOUT2 with 0.8% accurate Buffered VTT Reference Output Three Outputs have Independent Soft-Start and Enable Internal 300kHz Oscillator and Programmable Frequency range from 70 kHz to 800kHz Synchronous Switching Frequency DDR mode or Independent Mode Selection Phase Shift Selection Power Good Function Short-Circuit Protection for VOUT1 and VOUT2 Thermally Enhanced TSSOP-24 and QFN-32 Package Lead Free Available (RoHS Compliant) All outputs have independent soft-start and enable functions by SS/EN pins to control. Connect a capacitor from each SS/EN pin to the ground for setting the soft-start time, and pulling the SS/EN pin below 1V to disable regulator. Pull the SS2/EN2 to VCC, enter the DDR mode, the SS1/EN1 controls both VOUT1 and VOUT2, and allows VOUT2 to track VOUT1. It also offers the phase shift function by REFOUT pin to select the phase shift between VOUT1 and VOUT2 in DDR mode or Independent mode. When all SS/EN pins exceed 3.3V and no faults are detected, the PGOOD pin goes high to indicate the regulators are ready. If any of the SS/EN pins goes below 3.2V or any of the outputs has a fault condition, the PGOOD pin will be pulled low. Applications • • • Graphic Cards DDR memory Power Supplies Low-Voltage Distributed Power Supplies The internal oscillator is nominally 300kHz (keep the FS/SYNC pin open or short to GND), and it offers the programmable frequency function from 70kHz to 800kHz; connecting a resistor from FS/SYNC to VCC to decrease the frequency, conversely, connect a resistor from FS/SYNC to GND to increase the frequency. The IC also provides the synchronous frequency function. Connect the LGATE signal of another converter to FS/SYNC pin; forcing the switching frequency to follow ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 1 www.anpec.com.tw APW7066 General Description (Cont.) NC BOOT1 NC VCC FB1 COMP1 32 FB2 Pin Description COMP2 the external clock. The possible synchronous frequency is from 150kHz to 800kHz. There is no Rds(on) sensing or under-voltage sensing on APW7066. However, it provides a simple short-circuit protection by monitoring the COMP1 and COMP2 for over-voltage. When any of two pins exceeds their trip point and the condition persists for 1-2 internal clock cycle (3-6us at 300kHz), then it will shut down all regulators. 25 1 VCC BOOT1 UGATE1 PGND_1 VCC12_1 REFOUT VCC12 LGATE1 19 LGATE2 18 PGND 17 UGATE2 16 BOOT2 GND BOTTOM SIDE PAD SS1/EN1 SS2/EN2 LGATE1 LGATE2 SS3/EN3 VCC12_2 VREF 15 GND 14 PGOOD 13 FS/SYNC PGND_2 DRIVE3 NC 8 BOOT2 NC UGATE2 GND 9 TSSOP-24 TOP VIEW PGOOD 17 FS/SYNC GND BOTTOM SIDE PAD NC NC 6 7 SS2/EN2 8 SS3/EN3 9 VREF 10 DRIVE3 11 FB3 12 24 23 22 21 20 UGATE1 FB3 FB1 1 2 3 4 5 COMP1 COMP2 FB2 REFIN REFOUT SS1/EN1 24 REFIN 16 32 LD 5x5 QFN32 Top View Ordering and Marking Information APW7066 Pa c k a g e C o d e R : TSSOP-P * QA : Q F N - 3 2 Operating Ambient Temp. Range C : 0 to 70 ° C Handling Code TU : Tube TR : Tape & Reel TY : T r a y ( f o r Q F N o n l y ) Lead Free Code L : Lead Free Device Blank : Original Device Lead Free Code Handling Code Temp. Range Pa c k a g e C o d e A PW7066 R : A PW7066 QA : A PW 7 0 6 6 XXXXX XXXXX - Date Code XXXXX - Date Code A PW 7 0 6 6 XXXXX Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature. Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 2 www.anpec.com.tw APW7066 Block Diagram VCC VREF VCC12 5.8V 30uA Power On Reset and Control SS1/EN1 BOOT1 30uA 3.3V Bias Current SS2/EN2 0.6V 3.3V Gate Control Logic 1 UGATE1 30uA LGATE1 SS3/EN3 3.3V BOOT2 Gate Control Logic 2 UGATE2 Oscillator LGATE2 PGOOD Monitor COMP Pins for Short Protection FS/SYNC COMP1 0.6V 3.3V 1-2 Clock Cycle Filter FB1 REFOUT If short, Filter shut down all outputs REFIN VCC12 FB3 FB2 0.6V COMP2 DRIVE3 GND Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 PGND 3 www.anpec.com.tw APW7066 Absolute Maximum Ratings Symbol VCC12 Parameter Rating Unit -0.3 to 15 V -0.3 to 5.5 V -0.3 to 6 V VCC12 to GND VCC, separate supply VCC, separate supply VCC, shunt regulator VCC, shunt regulator to GND UGATE1, UGATE2, BOOT1, BOOT2 UGATE1, UGATE2, BOOT1, BOOT2 to GND -0.3 to 30 V LGATE1, LGATE2, DRIVE3 LGATE1, LGATE2, DRIVE3 to GND -0.3 to 15 V FS/SYNC to GND -0.3 to 15 V FS/SYNC REFIN, REFOUT, PGOOD, VREF REFIN, REFOUT, PGOOD, VREF to GND -0.3 to VCC V FB1, COMP1, FB2, COMP2, FB3 FB1, COMP1, FB2, COMP2, FB3 to GND -0.3 to VCC V SS1/EN1, SS2/EN2, SS3/EN3 SS1/EN, SS2/EN2, SS3/EN3 to GND -0.3 to VCC V PGND to GND -0.3 to +0.3 V 0 to +70 °C +150 °C -65 to +150 °C 260 °C PGND TA Operating Temperature Range TJ Maximum Junction Temperature TSTG TL Storage Temperature Range Lead Temperature (Soldering, 10sec) Electrical Characteristics Operating Conditions: VCC = 5V, VCC12 = 12V, TA = 0 to 70°C, Unless Otherwise Specified. Parameter INPUT SUPPLY POWER Input Supply Current (Quiescent) Test Conditions Typ. Max. Units VCC; outputs disabled 4 mA VCC12; outputs disabled 6 mA 50 mA 7 mA VCC12; UGATEs, LGATEs CL = 1nF, 300KHz Input Supply Current (Dynamic) VCC; UGATEs, LGATEs CL = 1nF, 300KHz 20mA current; ~Equivalent to 300Ω Shunt Regulator Output Voltage resistor VCC to 12V Shunt Regulator Current 300Ω resistor VCC to 12V Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 Min. 4 5.6 5.8 6.0 V 20 60 mA www.anpec.com.tw APW7066 Electrical Characteristics (Cont.) Operating Conditions: VCC = 5V, VCC12 = 12V, TA = 0 to 70°C, Unless Otherwise Specified. Parameter Test Conditions Min. Typ. VCC Rising 4.15 VCC Falling VCC12 Rising VCC12 Falling 3.9 7.55 7.1 Max. Units 4.23 4.4 V 4.0 7.8 7.3 4.15 8 7.55 V V V INPUT SUPPLY POWER Power-On Reset Threshold SYSTEM ACCURACY Outputs 1 and 3 Reference Voltage Output 2 Reference Voltage Outputs 1 and 2 System Accuracy Output 3 System Accuracy OSCILLATOR 0.6 3.3V Accuracy Frequency Adjustment Range FS/SYNC pin open FS/SYNC pin: resistor to GND; resistor to VCC12 Sawtooth Amplitude Duty-Cycle Range ERROR AMPLIFIER (OUT1 and OUT2) Open-Loop Gain RL = 10kΩ to ground Open-Loop Bandwidth CL = 100pF, RL = 10kΩ to ground Slew Rate CL = 100pF, RL = 10kΩ to ground EA Offset COMP1/2 to FB1/2; compare to internal VREF/REFIN Maximum Output Voltage RL = 10kΩ to ground; (may trip short-circuit) Output High Source Current COMP1/2, VCOMP=2V Output Low Sink Current COMP1/2, VCOMP=2V PROTECTION AND MONITOR Under-Voltage Threshold Causes PGOOD to go low; if there (COMP1 and COMP2) for a filter time, implies the COMP pin(s) is out-of-range, and shuts down IC Based on internal oscillator clock UV filter time frequency (nominal 300kHz = 3.3µs clock period) PGOOD Low Voltage IPGOOD = 2mA LINEAR REGULATOR (OUT3) DRIVE3 to FB3; compare to internal EA Offset VREF DRIVE3 High Output Voltage Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 V 5 -0.8 -0.8 0.8 0.8 % % -20 20 % 360 KHz 800 KHz 85 V % 240 300 70 2.1 0 85 15 4 2 dB MHz V/µs mV VCC V -50 45 mA mA 3.3 V 1 0.1 2 2 Clock pulses 0.3 V mV VCC12 www.anpec.com.tw APW7066 Electrical Characteristics (Cont.) Operating Conditions: VCC = 5V, VCC12 = 12V, TA = 0 to 70°C, Unless Otherwise Specified. Parameter Test Conditions Min. LINEAR REGULATOR (OUT3) DRIVE3 High Output Source Current DRIVE3 Low Output Sink Current VREF Output Voltage 1.1µF max capacitance Output Accuracy Typ. mA 2.5 mA 3.3 V -0.8 Determined by REFIN voltage Units 1.5 Source Current REFOUT (VTTREF) Output Voltage Max. +0.8 % 2.0 mA 0.6 3.3 V Offset Voltage -10 +10 mV Source Current 0.2 20 mA 0.48 mA Sink Current Output Capacitance Output High Voltage Minimum µF 0.1 To select 0 degree phase; see Table 1 3.8 ENABLE/SOFTSTART (SS/EN 1,2,3) EN Rising Enable Threshold EN falling 1.05 Soft-Start Current Soft-Start High Voltage Output High Voltage -30 3.5 3.8 VCC V V 0.95 End of ramp To select DDR mod; see Table 1 VCC µA V V 800 KHz 12 V FS/SYNC PLL Frequency range of Lock-in High Voltage 150 ( from LG pin of another IC, for example) GATE DRIVERS Output1 GATE Driver Source Output2 GATE Driver Source UGATE1, LGATE1=3V, BOOT=12V UGATE2, LGATE2=3V, BOOT=12V 1.8 1 A A Output1 GATE Driver Sink UGATE1, LGATE1=3V, BOOT=12V 2.5 Ω Output2 GATE Driver Sink UGATE2, UGATE2=3V, BOOT=12V 4 Ω Output Voltage UGATE1, UGATE2 Output Voltage LGATE1, LGATE2 Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 6 30 12 V V www.anpec.com.tw APW7066 Typical Application Circuit APW7066 DDR MODE VCC VCC12 Optional for shunt regulator COMP1 VOUT1 VIN1 BOOT1 FB1 UGATE1 COMP2 VOUT2 VOUT1 LGATE1 VCC12 FB2 BOOT2 VOUT1(DDR) VIN2=VOUT1(DDR) REFIN PHASE SHIFT 0 APW7066 VCC12 VCC PHASE SHIFT 90 VTTREF UGATE2 VOUT2 LGATE2 REFOUT VREF PGOOD SYNCHRONOUS FREQUENCY VIN3 FS/SYNC SS1/EN1 DRIVE3 SS2/EN2 FB3 SS3/EN3 GND Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 7 VOUT3 PGND www.anpec.com.tw APW7066 Typical Application Circuit (Cont.) APW7066 INDEPENDENT MODE VCC VCC12 Optional for shunt regulator COMP1 VOUT1 VIN1 BOOT1 FB1 UGATE1 COMP2 VOUT2 PHASE SHIFT 0 LGATE1 VCC12 FB2 BOOT2 VREF VOUT1 VIN2 REFIN APW7066 VCC12 VCC PHASE SHIFT 180 VTTREF UGATE2 VOUT2 LGATE2 REFOUT VREF PGOOD SYNCHRONOUS FREQUENCY VIN3 FS/SYNC SS1/EN1 DRIVE3 SS2/EN2 VOUT3 FB3 SS3/EN3 GND Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 8 PGND www.anpec.com.tw APW7066 Function Pin Descriptions VCC BOOT1, BOOT2 Power supply input pin. Connect a nominal 5V power supply to this pin for the control circuit, or connect a resistor (nominally 300Ω) to VCC12 for a shunt regulator function (typical 5.8V). It is recommended that a decoupling capacitor (1 to 10uF) is connected to the GND for noise decoupling. These pins provide the bootstrap voltage to the gate driver for driving the upper MOSFETs. It can be connected to a power voltage directly, but the difference voltage between the BOOT and VIN must be high enough to drive the upper MOSFETs. REFIN GND This pin is the reference input voltage of error amplifier of the VOUT2. It also provides the voltage into a buffer, which is out on the REFOUT pin. This pin is the signal ground pin. The metal thermal pad under the package is the IC substrate; connects the GND pin and metal thermal pad together on the board, and ties to the good GND plane for electrical and thermal conduction. REFOUT This pin provides a buffed voltage, which is from REFIN pin. In Independent mode, it can be used by other ICs. In DDR mode, it is from the VOUT1, and can be used as the VTT buffer. VCC12 Power supply input pin. Connect a nominal 12V power supply to this pin for the gate driver. It is recommended that a decoupling capacitor (1 to 10uF) is connected to the GND for noise decoupling. This pin also uses to select the phase shift (see table1). When this pin pulls to VCC, the buffer is disabled and the REFOUT is not available for use. It is recommended that a 0.1uF capacitor is connected to the ground for stability. PGND This pin is the power ground pin for the gate driver and linear driver circuit. It should be tied to the GND. VREF FB1, FB2, FB3 This pin provides a 3.3V reference voltage, which can be used by the REFIN pin or other ICs as a voltage reference. It is recommended that a 1uF capacitor is connected to ground for stability. These pins are the inverting inputs of the error amplifiers of their respective regulators. They are used to set the output v oltage and the compensation components. DRIVE3 SS1/EN1, SS2/EN2, SS3/EN3 This pin drives the gate of an external N-channel MOSFET for linear regulator. These pins provide two functions. Connect a capacitor to the GND for setting the soft-start time. Use an open drain logic signal to pull the SS/EN pin low to disable the respective output, leave open to enable the respective output. PGOOD This pin is an open drain device; connect a pull up resistor to the VCC for PGOOD function. FS/SYNC COMP1, COMP2 This pin is used to adjust the switching frequency. Connecting a resistor from FS/SYNC pin to the ground increases the switching frequency. Conversely, connecting a resistor from this pin to the VCC12 reduces the switching frequency. In addition, this pin also provides synchronous frequency function. An external clock can be fed into this pin, and force the switching frequency to follow the external clock. These pins are the outputs of error amplifiers of their respective regulators. They are used to set the compensation components. UGATE1, UGATE2 These pins provide the gate driver for the upper MOSFETs of VOUT1 and VOUT2. LGATE1, LGATE2 These pins provide the gate driver for the lower MOSFETs of VOUT1 and VOUT2. Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 9 www.anpec.com.tw APW7066 Typical Characteristics VOUT2 Power Up VOUT1 Power Up VCC12(5V/div) VCC12(5V/div) VCC(2V/div) VCC(2V/div) VOUT2(2V/div) VOUT1(1V/div) SS2(2V/div) SS1(2V/div) Time(5ms/div) Time(5ms/div) VOUT3 Power Up VREF Power Up VCC12(5V/div) VCC12(5V/div) VCC(2V/div) VCC(2V/div) VOUT3(1V/div) VREF(2V/div) SS3(2V/div) SS2(2V/div) Time(5ms/div) Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 Time(5ms/div) 10 www.anpec.com.tw APW7066 Typical Characteristics (Cont.) VOUT2 Power Up VOUT1 Power Up UGATE1(20V/div) UGATE2(20V/div) LGATE2(10V/div) LGATE1(10V/div) VOUT1(1V/div) VOUT2(5V/div) SS1(2V/div) SS2(2V/div) Time(2ms/div) Time(2ms/div) DDR Mode Power Up Phase Shift 0 degrees SS2=VCC VOUT1=REFIN VREF(2V/div) LG1(10V/div) VOUT2(2V/div) LG2(10V/div) VOUT1(1V/div) SS1(2V/div) Time(1us/div) Time(2ms/div) Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 11 www.anpec.com.tw APW7066 Typical Characteristics (Cont.) Phase Shift 180 degrees Phase Shift 90 degrees LG1(10V/div) LG1(10V/div) LG2(10V/div) LG2(10V/div) Time(1us/div) Time(1us/div) PGOOD High PGOOD Low SS1(2V/div) SS1(2V/div) SS2(2V/div) SS2(2V/div) SS3(2V/div) SS3(2V/div) PGOOD(5V/div) PGOOD(5V/div) Time(5ms/div) Time(5ms/div) Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 12 www.anpec.com.tw APW7066 Typical Characteristics (Cont.) VOUT1 Short Circuit Protection VOUT2 Short Circuit Protection Comp1 (2V/div) Comp2 (2V/div) SS1 (2V/div) SS2 (2V/div) UG1 (20V/div) UG2 (20V/div) PGOOD (5V/div) PGOOD (5V/div) Time(5us/div) Time(5us/div) VOUT2 Load Transient VOUT1 Load Transient VOUT1=VIN3 VOUT1 (0.1V/div) VOUT1=VIN3 VOUT1 (0.2V/div) VOUT2 (0.1V/div) VOUT2 (0.1V/div) VOUT3 (0.1V/div) VOUT3 (0.05V/div) IOUT2 (5A/div) IOUT1 (10A/div) Time(20us/div) Time(20us/div) Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 13 www.anpec.com.tw APW7066 Typical Characteristics (Cont.) VOUT3 Load Transient UG1 Rising VOUT1=VIN3 VOUT1 (0.1V/div) UG1 (10V/div) VOUT2 (0.1V/div) Phase1 (10V/div) VOUT3 (0.1V/div) LG1 (10V/div) IOUT3 (2A/div) Time(20us/div) Time(50ns/div) UG1 Falling UG2 Rising UG1 (10V/div) UG2 (10V/div) Phase1 (10V/div) Phase2 (10V/ LG1 (10V/div) LG2 (10V/div) Time(50ns/div) Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 Time(50ns/div) 14 www.anpec.com.tw APW7066 Typical Characteristics (Cont.) PGOOD Sink Current vs. PGOOD Voltage UG2 Falling 3 2.5 Sink Current (mA) UG2 (10V/div) Phase2 (10V/div) 2 1.5 1 0.5 LG2 (10V/div) 0 0 10 Time(50ns/div) 20 30 40 PGOOD Voltage (mV) REFOUT Voltage vs. Source Current VREF Voltage vs. Source Current 3.32 3.35 3.34 3.31 3.32 VREF Voltage (V) REFOUT Voltage (V) 3.33 3.31 3.3 3.29 3.28 3.27 3.3 3.29 3.26 3.25 3.28 0 5 10 15 20 0 Source Current (mA) Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 0.5 1 1.5 2 Source Current (mA) 15 www.anpec.com.tw APW7066 Typical Characteristics (Cont.) UG1 Source Current vs. Voltage 2.4 2.2 2.4 2.2 2 1.8 2 1.8 Source Current (A) Sink Current (A) UG1 Sink Current vs. Voltage 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 0 2 4 6 8 10 12 0 2 UG1 Voltage (V) 6 8 10 12 UG1 Voltage (V) LG1 Sink Current vs. Voltage LG1 Source Current vs. Voltage 2.4 2.4 2.2 2.2 2 2 1.8 1.8 1.6 1.4 Source Current (A) Sink Current (A) 4 1.2 1 0.8 0.6 0.4 0.2 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 0 2 4 6 8 10 12 0 LG1 Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 2 4 6 8 10 12 LG1 Voltage (V) 16 www.anpec.com.tw APW7066 Typical Characteristics (Cont.) UG2 Sink Current vs. Voltage UG2 Source Current vs. Voltage 1.4 1.6 BOOT=12V BOOT=12V 1.4 1.2 Source Current (A) Sink Current (A) 1.2 1 0.8 0.6 0.4 0.2 1 0.8 0.6 0.4 0.2 0 0 0 2 4 6 8 10 0 12 2 4 8 10 12 UG2 Voltage UG2 Voltage (V) LG2 Source Current vs. Voltage LG2 Sink Current vs. Voltage 1.6 1.4 1.4 1.2 1.2 1 Source Current (A) Sink Current (A) 6 1 0.8 0.6 0.4 0.2 0.8 0.6 0.4 0.2 0 0 0 2 4 6 8 10 0 12 LG2 Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 2 4 6 8 10 12 LG2 Voltage (V) 17 www.anpec.com.tw APW7066 Typical Characteristics (Cont.) DRIVE3 Sink Current vs. Voltage DRIVE3 Source Current vs. Voltage 3.5 2 3 Source Current (mA) Sink Current (mA) 2.5 2 1.5 1 0.5 1.5 1 0.5 0 0 0 2 4 6 8 10 12 0 2 DRIVE3 Voltage (V) 6 8 10 12 DRIVE3 Voltage (V) Shunt Regulator Sink Current vs. Voltage FS Resistance vs. Switching Frequency 60 1000 FS to VCC12 900 50 Sink Current (mA) 800 FS Resistance (kΩ) 4 700 600 500 400 300 200 40 30 20 10 FS to GND 100 0 0 0 100 200 300 400 500 600 700 800 3 Switching Frequency (kHz) Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 3.5 4 4.5 5 5.5 6 6.5 7 Shunt Regulator Voltage (V) 18 www.anpec.com.tw APW7066 Typical Characteristics (Cont.) Comp Source Current vs. Voltage 70 50 60 Source Current (mA) Sink Current (mA) Comp Sink Current vs. Voltage 60 40 30 20 10 0 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 0 1 3 4 VREF Voltage vs. Temperature FB Voltage vs. Temperature 3.35 608 3.34 606 3.33 VREF Voltage (V) 610 604 FB Voltage (V) 2 Comp Voltage (V) Comp Voltage (V) 602 600 598 596 3.32 3.31 3.3 3.29 3.28 594 3.27 592 3.26 3.25 590 0 25 50 75 100 125 150 0 Rev. A.4 - Jun., 2005 50 75 100 125 150 Temperature (°C) Temperature (°C) Copyright ANPEC Electronics Corp. 25 19 www.anpec.com.tw APW7066 Function Descriptions Operational Modes Phase Shift The APW7066 has two independent synchronous buck converters, and it also has DDR mode operation to allow VOUT2 to track VOUT1. The APW7066 has phase shift function, use the REFOUT pin to select the phase shift between Independent mode and DDR mode. Connect the REFOUT to VCC to get the 0 degrees in either mode. In this case, the buffer of the REFOUT is disabled. Leave the REFOUT open shifts the phase 90 degrees in DDR mode, or 180 degrees in Independent mode, REFOUT can be used in this case ( see Table 1.). In independent mode operation, connect a capacitor from each SS/EN pin to the ground to set each regulator’s soft-start time. The 3.3V reference VREF can be used directly, or divided by two resistors for REFIN, since the VREF is controlled by the SS2/EN2. MODE DDR DDR mode is chosen by connecting the SS2/EN2 pin to VCC(5V). In this mode, SS2/EN2 function will be disabled, SS1/EN1 is used to control soft start and enable both VOUT1 and VOUT2. The VOUT1 is used as the REFIN for the VOUT2, that makes VOUT2 to track VOUT1. SS2/EN2 REFOUT REFIN PHASE SHIFT CH1/CH2 VCC VCC VOUT1 0 deg SS1/EN1 for CH1 and CH2 DDR VCC Open VOUT1 90 deg Independent Independent SS2 cap SS2 cap VCC Open VREF VREF 0 deg 180 deg SS1/EN1 for CH1 SS2/EN2 for CH2 Table1.Mode and Phase Selection VREF The advantage of Phase shift is to avoid overlapping the switching current spikes of the two channels, or interaction between the channels; it also reduces the RMS current of the input capacitors, allowing fewer caps to be employed. However, the phase shift between the rising edge of LGATE1 and LGATE2 (See figure 3.), depending on the duty cycles, the falling edges of the two channels might overlap; so the user should check it. REFIN SS1/EN1 SS2/EN2 SS3/EN3 GND Figure 1. Independent Mode Circuit LG1 VOUT1 REFIN LG2 (0deg) VCC LG2 (90deg) SS1/EN1 SS2/EN2 SS3/EN3 GND LG2 (180deg) 0 Rev. A.4 - Jun., 2005 180 0 Figure 3. Phase of LG2 with respect to rising edge of LG1 Figure 2.DDR Mode Circuit Copyright ANPEC Electronics Corp. 90 20 www.anpec.com.tw APW7066 Function Descriptions (Cont.) Soft-Start/Enable PGOOD The three SS/EN pins control the soft-start and enable or disable the controller. In Independent mode, the three regulators all have independent soft-start and enable functions. Connect a soft-start capacitor from each SS/EN pin to the GND to set the soft-start interval, and an open drain logic signal for each SS/EN pin will enable or disable the respective output. The PGOOD output is an open-drain device, when the VCC is present; the gate of open-drain device will be high, forcing the PGOOD pin to go low. The three SS/EN pins and the SCP signals control the PGOOD signal (see block diagram), after the three SS/EN signals are over threshold high 3.3V and three outputs have no short-circuit, the PGOOD goes high to indicate all regulators are ready. If any of the SS/EN pins goes below threshold low 3.2V, the PGOOD will go low. Also, if any of the outputs has a short, the PGOOD pull low and if short-circuit condition continues for 1-2 clock pulses, all regulators will shut down. If the short-circuit is not long enough to shut down, it may still cause PGOOD to go low momentarily. Figure 4. Shows the soft-start interval. When both VCC and VCC12 reach their Power-On-Reset threshold 4.23V and 7.8V, a 30uA current source starts to charge the capacitor. When the SS reaches the enabled threshold about 1V, the internal 0.6V reference starts to rise and follows the SS; the error amplifier output (COMP) suddenly raises to 1.1V, which is the valley of the oscillator’s triangle wave, leads the VOUT to start up. Until the SS reaches about 3.0V, the internal reference completes the soft-start interval and reaches to 0.6V; then VOUT1 is in regulation. The SS1 still rises to 3.5V and then stops. Because the PGOOD is an open-drain device, the typical range of the value to connect a pull high resistor to VCC will be 1kΩ to 10kΩ; if PGOOD is not used, leave it open. Shunt Regulator VOLTAGE The APW7066 must have two power supplies VCC (5V) and VCC12 (12V) to drive the IC; VCC (5V) is for the control circuit and VCC12 (12V) is for the drivers of outputs. But it can also operate only VCC12, because the shunt regulator 5.8V was designed for VCC (5V); the range of the shunt regulator was designed over the usual range 4.5V to 5.5V of typical 5V power supplies. V SS 3V V OUT 1V t0 t1 t2 Connect a resistor from VCC12 to VCC for shunt regulator and for the supply current. The input supply current of VCC is 7mA; minimum shunt regulator current is about 7mA, and therefore the 20mA shunt regulator current is enough; thus, the typical value, 300Ω of the resistor is recommended. The relation among minimun shunt regulator current, required shunt regulator current and supply current is: TIME Figure 4. Soft-Start Interval TSoft - Start = t2 − t1 = CSS ⋅ 2V ISS Where: CSS = external Soft-Start capacitor ISS = Soft-Start current = 30µA Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 21 www.anpec.com.tw APW7066 Function Descriptions (Cont.) PGOOD (Cont.) ISHUNT = ICC + ISHUNT(MIN) Where: ISHUNT = Required Shunt Regulator Current ICC = Supply Current ISHUNT(MIN) = Minimum Shunt Regulator Current OPTIONAL R VCC (5.8V) FOR SHUNT REGULATOR SYNC The switching frequency also can be synchronized to an external frequency. If there are two switching converters on the same board, taking the LGATE signal from another switching converter, go through a 10kΩ resistor, and connecting to the FS/SYNC pin. The APW7066 will read another converter’s frequency and after several milliseconds, the APW7066 will change to new frequency. If another converter’s signal is lost, the APW7066 will return to internal oscillator. This allows the two switching converters for operating at the same frequency to avoid the interference from the independent frequencies between them. The acceptable frequency is a range of 150kHz to 800kHz. VCC12 Oscillator The APW 7066 provides the oscillator switching frequency adjustment. Connect a resistor from FS/SYNC pin to the ground, the nominally 300kHz oscillator switching frequency is increased according to the value of the resistor. The adjustment range of the switching frequency is 300kHz to 800kHz. Short-Circuit Protection The APW7066 has a simple short-circuit protection to monitor COMP1 and COMP2 for VOUT1/2. When output voltage has a short, the FB pin should start to follow output, since it is a resistor divider from the output. The FB is the inverting input of Error-Amp, when FB pin is lower than the Error-Amp reference, then the COMP will rise to increase the duty-cycle of the upper MOSFET gate driver, this allows output to get higher voltage. If the short-circuit condition is long enough, the COMP pin will exceed the trip point 3.3V, and the duty circle will hit the maximum. This means that either Over-Current or Under-Voltage condition is detected. If any of the COMP1 and COMP2 exceeds their trip points, and holds over a filter time (1-2 clock cycle of switching frequency), then all regulators will shut down, and require a POR on either of VCC or VCC12 to restart. Note that the linear regulator has no short-circuit protection. Conversely, connecting a resistor from FS/SYNC pin to the VCC12 reduces the switching frequency.The adjustment range of the switching frequency is 70kHz to 300kHz. 1000 FS to VCC12 900 FS Resistance (kO) 800 700 600 500 400 300 FS to GND 200 100 0 0 100 200 300 400 500 600 700 800 Switching Frequency (kHz) Figure 5. FS/SYNC Resistance vs. Frequency Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 22 www.anpec.com.tw APW7066 Application Information Output Voltage Setting Linear Regulator Input/Output MOSFET Selection The output voltage can be adjusted with a resistive divider, from output voltage to FB pin to the ground. Use 1% or better resistors for these resistor dividers is recommended. The reference voltages of VOUT1 and VOUT3 are 0.6V, the reference voltage of VOUT2 is REFIN voltage. The VREF voltage is for REFIN in independent mode. The following equations can be used to calculate the output voltage: The maximum DRIVE3 voltage is determined by the VCC12. Since this pin drives an external N-channel MOSFET, therefore the maximum output voltage of the linear regulator is dependent upon the VGS. VOUT1 = (1 + VOUT3MAX = VCC12 - VGS Another criteria is its efficiency of heat removal. The power dissipated by the MOSFET is given by: Pdiss = Iout x (VIN - VOUT3) R1 ) x 0.6V R2 where Iout is the maximum load current VOUT3 is the nominal output voltage R1 VOUT2 = ( 1 + ) x REFIN R2 In some applications, heatsink might be required to help maintain the junction temperature of the MOSFET below its maximum rating. R1 VOUT3 = ( 1 + ) x 0.6V R2 R3 ) x VOUT1 (DDR Mode) R4 R3 REFIN = (1 + ) x VREF (Independe nt Mode) R4 REFIN = (1 + Linear Regulator Compensation Selection The linear regulator is stable over all load current. However, the transient response can be further enhanced by connecting a RC network between the FB3 and DRIVE3 pin. Depending on the output capacitance and load current of the application, the value of this RC network is then varied. A good starting point for the resistor value is 6.8kΩ and 470pF for the capacitor. Where: R1 = resistor from VOUT to FB R2 = resistor from FB to GND R3 = resistor from VREF or VOUT1 to REFIN R4 = resistor from REFIN to GND Note that the R1 is part of the compensation. It should be conformed to the feedback compensation. PWM Compensation Linear Regulator Input/Output Capacitor Selection The output LC filter of a step down converter introduces a double pole, which contributes with –40dB/decade gain slope and 180 degrees phase shift in the control loop. A compensation network between COMP, FB and VOUT should be added. The compensation network is shown in Fig. 9. The input capacitor is chosen based on its voltage rating. Under load transient condition, the input capacitor will momentarily supply the required transient current. The output capacitor for the linear regulator is chosen to minimize any droop during load transient condition. In addition, the capacitor is chosen based on its voltage rating. The output LC filter consists of the output inductor and output capacitors. The transfer function of the LC filter is given by: GAINLC = Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 23 1+ s × ESR × COUT s × L × COUT + s × ESR × COUT + 1 2 www.anpec.com.tw APW7066 Application Information (Cont.) PWM Compensation (Cont.) VIN The poles and zero of this transfer function are: Driver 1 FLC = PWM Comparator 2 × π × L × COUT VOSC 1 FESR = 2 × π × ESR × C OUT Output of Error Amplifier The FLC is the double poles of the LC filter, and FESR is the zero introduced by the ESR of the output capacitor. L PHASE Driver Output COUT Figure 8. The PWM Modulator ESR The compensation circuit is shown in Figure 9. It provide a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. The transfer function of error amplifier is given by: Figure 6. The Output LC Filter V COMP GAINAMP = V OUT FLC -40dB/dec FESR The poles and zeros of the transfer function are: 1 FZ1 = 2 × π × R2× C2 Frequency Figure 7. The LC Filter Gain & Frequency FZ2 = The PWM modulator is shown in Figure. 8. The input is the output of the error amplifier and the output is the PHASE node. The transfer function of the PWM FP1 = modulator is given by: V IN Rev. A.4 - Jun., 2005 FP2 = ∆ V OSC Copyright ANPEC Electronics Corp. = 1 1 // R2 + sC1 sC2 1 R1 // R3 + sC3 1 1 s + × s + R1+ R3 R2× C2 (R1+ R3)× C3 × = C1+ C2 1 R1× R3× C1 s s + × s + × × R3 × C3 R2 C1 C2 -20dB/dec GAINPWM = PHASE 24 1 2× π× (R1+ R3) ×C3 1 C1 × C2 2 × π × R2 × C1 + C2 1 2 × π × R3 × C3 www.anpec.com.tw APW7066 Application Information (Cont.) PWM Compensation (Cont.) C1 R3 C3 R2 C2 VOUT R1 FB VCOMP + VREF Figure 9. Compensation Network The closed loop gain of the converter can be written as: GAINLC x GAINPWM x GAINAMP Figure 10. shows the asymptotic plot of the closed loop converter gain and the following guidelines will help to design the compensation network. Using the below guidelines should give a compensation similar to the curve plotted. A stable closed loop has a -20dB/ decade slope and a phase margin greater than 45 degree. 1.Choose a value for R1, uaually between 1K and 5K. 2.Select the desired zero crossover frequency FO: (1/5 ~ 1/10) x FS >FO>FESR Use the following equation to calculate R2: R2 = Open Loop Error Amp Gain Gain 20log (R2/R1) FLC PWM & Filter Gain Converter Gain Frequency Figure 10. Converter Gain & Frequency Output Inductor Selection The inductor value determines the inductor ripple current and affects the load transient response. Higher inductor value reduces the inductor’s ripple current and induces lower output ripple voltage. The ripple current and ripple voltage can be approximated by: 1 2 × π × R2 × FLC × 0.75 IRIPPLE = C2 VIN − VOUT VOUT × FS × L VIN ∆VOUT = IRIPPLE x ESR 2 × π × R2× C2× FESR − 1 Rev. A.4 - Jun., 2005 FO FESR ∆ V OSC FO × × R1 V IN F LC Copyright ANPEC Electronics Corp. FP2=0.5FS 20log (VIN / VOSC) Compensation Gain 0 4.Set the pole at the ESR zero frequency FESR: FP1 = FESR Calculate the C1 by the equation: C1 = FZ1=0.75FLC FP1=FESR FZ2=FLC 3.Place the first zero FZ1 before the output LC filter double pole frequency FLC. FZ1 = 0.75 x FLC Calculate the C2 by the equation: C2 = 5.Set the second pole F P2 at half the switching frequency and also set the second zero FZ2 at the output LC filter double pole FLC. The compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at FP2 with the capabilities of the error amplifier. FP2 = 0.5xFO FZ2 = FLC Combine the two equations will get the following component calculations: R1 1 R3 = C3 = FS π × R3 × FS −1 2xFLC 25 www.anpec.com.tw APW7066 Application Information (Cont.) Output Inductor Selection (Cont.) rating and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2, where IOUT is the load current. During power up, the input capacitors have to handle large amount of surge current. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. For high frequency decoupling, a ceramic capacitor 1uF can be connected between the drain of upper MOSFET and the source of lower MOSFET. where Fs is the switching frequency of the regulator. Although increase the inductor value and frequency reduce the ripple current and voltage, but there is a tradeoff exists between the inductor’s ripple current and the regulator load transient response time. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. Increasing the switching frequency (FS) also reduces the ripple current and voltage, but it will increase the switching loss of the MOSFET and the power dissipation of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. MOSFET Selection The selection of the N-channel power MOSFETs are determined by the RDS(ON), reverse transfer capacitance (CRSS) and maximum output current requirement.The losses in the MOSFETs have two components: conduction loss and transition loss. For the upper and lower MOSFET, the losses are approximately given by the following : Once the inductance value has been chosen, select an inductor that is capable of carrying the required peak current without going into saturation. In some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. This will result in a larger output ripple voltage. PUPPER = Iout (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS Output Capacitor Selection PLOWER = Iout (1+ TC)(RDS(ON))(1-D) Higher Capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore select high performance low ESR capacitors that are intended for switching regulator applications. In some applications, multiple capacitors have to be parallel to achieve the desired ESR value. A small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors are also must be considered. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. where IOUT is the load current TC is the temperature dependency of RDS(ON) FS is the switching frequency tsw is the switching interval D is the duty cycle Note that both MOSFETs have conduction losses while the upper MOSFET include an additional transition loss.The switching internal, tsw, is a function of the reverse transfer capacitance CRSS. The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET. Input Capacitor Selection The input capacitor is chosen based on the voltage Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 26 www.anpec.com.tw APW7066 Application Information (Cont.) Connecting One Input from Another Output short; the COMP pin will have a sharp rise. However, if the current rises too fast, it may cause a false trip. The output capacitance and its ESR can affect the rising time of the current during short. It can be connected one of the 3 outputs as the input voltage to the 2nd. In these cases the output current of the first output includes its own load current and the 2nd output’s load current. Therefore, the components of the first output must be designed and sized for the both outputs. The soft-start of first output must be faster than the 2nd output. If the first output is not present when the 2nd output tries to start up, the 2nd output cannot get smooth and controlled output voltage rise, Layout Considerations In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. In general, interconnecting impedances should be minimized by using short, wide printed circuit traces. Signal and power grounds are to be kept separate and finally combined using ground plane construction or single point grounding. Figure 10. illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. Components along the bold lines should be placed lose together. Below is a checklist for your layout : even cause short-circuit protection. Short Circuit Protection The APW 7066 prov ides a simple short circuit protection function, and it is not easy to predict its performance, since many factors can affect how well it works. Therefore, the limitations and suggestions of this method must be provided for users to understand how to work it well. • The metal plate of the bottom of the packages (TSSOP-24 and QFN-32) must be soldered to the PCB and connected to the GND plane on the backside through several thermal vias. • The short circuit protection was not designed to work for the output in initial short condition. In this case, the short circuit protection may not work, and damage the MOSFETs. If the circuit still works, remove the short can cause an inductive kick on the phase pin, and it may damage the IC and MOSFETs. • Keep the switching nodes (UGATE, LGATE and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible. • If the resistance of the short is not low enough to • The traces from the gate drivers to the MOSFETs cause protection, the regulator will work as the load has increased, and continue to regulate up until the MOSFETs is damaged. The resistance of the short should include wiring, PCB traces, contact resistances, and all of the return paths. (UG1, LG1, UG2, LG2, DRIVE3) should be short and wide. • Decoupling capacitor, compensation component, • The higher duty cycle will give a higher COMP • The input capacitor should be near the drain of the voltage level, and it is easy to touch the trip point. The compensation components also affect the response of COMP voltage; smaller caps may give a faster response. upper MOSFET; the output capacitor should be near the loads. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND. the resistor dividers, boot capacitors, and SS capacitors should be close their pins. • The output current has faster rising time during • The drain of the MOSFETs (VIN and phase nodes) should be a large plane for heat sinking. Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 27 www.anpec.com.tw APW7066 Application Information (Cont.) VIN APW7066 UG C BOOT FB BOOT L1 Q2 REFOUT C REFOUT LG PGND VCC VCC12 VREF C VREF SS C SS VOUT Q1 CVCC12 COUT CIN L O A D C VCC GND Figure 11. Layout Guidelines Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 28 www.anpec.com.tw APW7066 Packaging Information TSSOP/ TSSOP-P (Reference JEDEC Registration MO-153) e N D 2x E/2 A2 E1 A E A1 b 1 2 3 e/2 D1 ( 2) GAUGE PLANE S EXPOSED THERMAL PAD ZONE E2 0.25 L 1 (L1) BOTTOM VIEW ( 3) (THERMALLY ENHANCED VARIATIONDS ONLY) Dim A A1 A2 b D D1 e E E1 E2 L L1 R R1 S φ1 φ2 φ3 Millimeters Max. 1.2 0.00 0.15 0.80 1.05 0.19 0.30 6.6 (N=20PIN) 6.4 (N=20PIN) 7.9 (N=24PIN) 7.7 (N=24PIN) 9.8 (N=28PIN) 9.6 (N=28PIN) 4.2 BSC (N=20PIN) 4.7 BSC (N=24PIN) 3.8 BSC (N=28PIN) 0.65 BSC 6.40 BSC 4.30 4.50 3.0 BSC (N=20PIN) 3.2 BSC (N=24PIN) 2.8 BSC (N=28PIN) 0.45 0.75 1.0 REF 0.09 0.09 0.2 0° 8° 12° REF 12° REF Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 Inches Min. 29 Min. Max. 0.047 0.000 0.006 0.031 0.041 0.007 0.012 0.260 (N=20PIN) 0.252 (N=20PIN) 0.303 (N=24PIN) 0.311 (N=24PIN) 0.378 (N=28PIN) 0.386 (N=28PIN) 0.165 BSC (N=20PIN) 0.188 BSC (N=24PIN) 0.150 BSC (N=28PIN) 0.026 BSC 0.252 BSC 0.169 0.177 0.118 BSC (N=20PIN) 0.127 BSC (N=24PIN) 0.110 BSC (N=28PIN) 0.018 0.030 0.039REF 0.004 0.004 0.008 0° 8° 12° REF 12° REF www.anpec.com.tw APW7066 Packaging Information QFN-32 D 32 31 30 29 28 27 26 D2 25 1 24 2 L 31 32 1 23 2 3 22 4 21 E E2 5 20 6 19 7 18 8 17 9 10 11 12 13 14 15 16 e b A A3 A1 Dim Millimeters Inches Min. Max. Min. Max. A - 0.84 - 0.033 A1 0.00 0.04 0.00 0.0015 A3 0.20 REF. 0.008 REF. D 4.90 5.10 0.192 0.200 E 4.90 5.10 0.192 0.200 b 0.18 0.28 0.007 0.011 D2 3.50 3.60 0.138 0.142 E2 3.50 3.60 0.138 0.142 0.500 BSC e L 0.35 Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 0.020 BSC 0.45 0.014 30 0.018 www.anpec.com.tw APW7066 Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone T L to T P Temperature Ramp-up TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25 °C to Peak Time Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface. (mm) Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 31 www.anpec.com.tw APW7066 Classification Reflow Profiles(Cont.) Table 1. SnPb Entectic Process – Package Peak Reflow Temperature s 3 3 Package Thickness Volume mm Volume mm <350 ≥350 <2.5 mm 240 +0/-5°C 225 +0/-5°C ≥2.5 mm 225 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0°C* 260 +0°C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 SEC 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA Carrier Tape & Reel Dimensions t D P Po E P1 Bo F W Ko Ao Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 D1 32 www.anpec.com.tw APW7066 Carrier Tape & Reel Dimensions(Cont.) T2 J C A B T1 Application TSSOP- 24 A B C J T1 T2 W P E 330 ±1 100 ref 13 ±0.5 2 ±0.5 16.4 ±0.2 2 ±0.2 16 ±0.3 12 ±0.1 1.75±0.1 F D D1 Po P1 Ao Bo Ko t 7.5 ±0.1 1.5 +0.1 1.5 min 4.0 ±0.1 2.0 ±0.1 6.9 ±0.1 8.3 ±0.1 1.5 ±0.1 0.3±0.05 (mm) 5x5 Shipping Tray Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 33 www.anpec.com.tw APW7066 5x5 Shipping Tray(Cont.) Cover Tape Dimensions Application TSSOP- 24 Carrier Width 16 Cover Tape Width 21.3 Devices Per Reel 2000 Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2005 34 www.anpec.com.tw