ASIX AX88172L

AX88172 L
USB to Fast Ethernet/HomePNA Controller
USB to Fast Ethernet/HomePNA Controller
Document No.: AX172-4/ V1.4 / DEC, 20/02
Features
•
Single chip USB to 10/100Mbps Fast Ethernet and
1/10Mbps HomePNA and HomePlug Network
Controller
• Compliant with USB specification 1.0 and 1.1 and
2.0
• Full/High Speed USB Device with bus power
capability
• Support 4 endpoints on USB
• IEEE 802.3u 100BASE-T, TX, and T4 Compatible
• Embedded 7K*16 bit SRAM, 256*16 bit SRAM
and 8 FIFOs
• Support both full-duplex or half-duplex operation
on Fast Ethernet
• Provides a MII port for both Ethernet and
HomePNA/ HomePlug PHY interface
•
•
•
•
•
•
•
Supports suspended mode and remote wakeup
(link_up or magic packet or external pin)
Optional PHY power down mode for power saving
Support (94c56/93c66) 256/512 bytes serial
EEPROM (used for saving USB Descriptors)
Support automatic loading of Ethernet ID, USB
Descriptors and Adapter Configuration from
EEPROM on power-on initialization
External PHY loop-back diagnostic capability
Small form factor with 80-pin LQFP package
Single 12MHz clock input, pure 3.3V operation
*IEEE is a registered trademark of the Institute of Electrical and
Electronic Engineers, Inc.
*All other trademarks and registered trademark are the property of their
respective holders.
Product description
The AX88172 USB to Fast Ethernet/HomePNA/HomePlug Controller is a high performance and highly integrated
Controller with embedded 7K*16 bit SRAM. The AX88172 contains a USB interface to host CPU and compliant with
USB Standard V1.0, V1.1 and V2.0. The AX88172 could be used for both 10M/100Mbps Fast Ethernet function based on
IEEE802.3 / IEEE802.3u LAN standard and 1M/10M HomePNA standard. The AX88172 supports media-independent
interface (MII) to simplify the design on implementing Fast Ethernet and HomePNA functions.
System Block Diagram
RJ45
RJ11
MAGNETIC
10/100 Mbps Ethernet
PHY/TxRx
AX88172
MAGNETIC
1/10 Mbps
Home LAN PHY
EEPROM
USB I/F
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No
liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
Frist Released Date: Dec/20/2001
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
FAX: 886-3-579-9558
TEL: 886-3-579-9500
http://www.asix.com.tw
AX88172
PRELIMINARY
CONTENTS
1.0 INTRODUCTION....................................................................................................................... 4
1.1 GENERAL DESCRIPTION:............................................................................................................. 4
1.2 AX88172 BLOCK DIAGRAM:...................................................................................................... 4
1.3 AX88172 PIN CONNECTION DIAGRAM....................................................................................... 5
2.0 SIGNAL DESCRIPTION........................................................................................................... 6
3.0 EEPROM MEMORY MAPPING............................................................................................ 9
4.0 USB COMMANDS ................................................................................................................... 11
4.1 USB STANDARD COMMANDS .................................................................................................... 11
4.2 USB VENDOR COMMANDS ....................................................................................................... 12
5.0 USB CONFIGURATION STRUCTURE .............................................................................. 14
5.1 USB CONFIGURATION. ............................................................................................................. 14
5.2 USB INTERFACE....................................................................................................................... 14
5.3 USB ENDPOINTS. ..................................................................................................................... 14
6.0 ELECTRICAL SPECIFICATION AND TIMINGS ............................................................ 15
6.1 ABSOLUTE MAXIMUM RATINGS ............................................................................................... 15
6.2 GENERAL OPERATION CONDITIONS .......................................................................................... 15
6.3 DC CHARACTERISTICS ............................................................................................................. 15
6.4 A.C. TIMING CHARACTERISTICS ............................................................................................... 16
6.4.1 12M_XIN ........................................................................................................................... 16
6.4.2 Reset Timing ...................................................................................................................... 16
6.4.3 MII Timing......................................................................................................................... 17
6.4.4 STATION MANAGEMENT TIMING................................................................................. 18
6.4.5 SERIAL EEPROM TIMING .............................................................................................. 19
7.0 PACKAGE INFORMATION.................................................................................................. 20
APPENDIX A: SYSTEM APPLICATIONS ................................................................................ 21
A.1 USB TO FAST ETHERNET CONVERTER .................................................................................... 21
A.2 USB TO FAST ETHERNET AND/OR HOMELAN COMBO SOLUTION ........................................... 21
DEMONSTRATION CIRCUIT A: AX88172 (ED2 VERSION) + ETHERNET PHY(8201L)
........................................................................................................................................................... 22
DEMONSTRATION CIRCUIT B: AX88172 (ED3 VERSION) + ETHERNET PHY
(8201LBL) ........................................................................................................................................ 24
REMARK: ....................................................................................................................................... 26
REVISIONS HISTORY ................................................................................................................. 27
2
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AX88172
PRELIMINARY
FIGURES
FIG – 1 AX88172 BLOCK DIAGRAM ...................................................................................................................................4
FIG – 2 AX88172 PIN CONNECTION DIAGRAM ...................................................................................................................5
TABLES
TAB - 1 PIN SIGNALS ..........................................................................................................................................................8
TAB - 2 EEPROM MEMORY MAPPING ..............................................................................................................................9
3
ASIX ELECTRONICS CORPORATION
AX88172
PRELIMINARY
1.0 Introduction
1.1 General Description:
The AX88172 USB to Fast Ethernet Controller is a high performance and highly integrated USB bus Ethernet Controller
with embedded 7K*16 bit SRAM. The AX88172 supported Full/High Speed USB Device with bus power capability. The
AX88172 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3/ IEEE802.3u LAN standard.
The AX88172 supports media-independent interface (MII) to simplify the design on implementing Fast Ethernet and
HomePNA functions.
AX88172 uses 80-pin LQFP low profile package, 12MHz operation for USB and 25MHz operation for Ethernet, CMOS
process with pure 3.3V operation.
1.2 AX88172 Block Diagram:
MDC
MDIO
STA
7K* 16
SRAM
EECS
EECK
EEDI
EEDO
SEEPROM
Loader I/F
Memory Arbiter
USB to
Ethernet
Bridge
MAC
Core
MII /IF
USB Core and Interface
DM/DP
Fig – 1 AX88172 Block Diagram
4
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AX88172
PRELIMINARY
1.3 AX88172 Pin Connection Diagram
The AX88172 is housed in the 80-pin plastic light quad flat pack.
PHYRSTP
PHYRSTN
GPIO2
GPIO1
GPIO0
TEST1
TEST0
VDD
47
46
45
44
43
42
41
50
48
NC
51
49
NC
52
VSS
LED
53
56
NC
57
VDD
EECK
EECS
58
54
EEDI
59
55
EEDO
60
NC
VSS
61
40
VSS
62
39
RXDV
NC
63
38
RXER
NC
64
37
VDD
NC
65
36
RXD3
NC
66
35
RXD2
34
RXD1
33
RXD0
32
RXCLK
31
VDD
VDD
RST_TYPE
NC
67
ANA_XIQ
68
VDD
69
ASIX
AX88172
CLKI
70
TESTMODE
71
30
TXEN
RESET/RESET
72
29
TXD3
28
TXD2
ED3
VSS
73
VDD
74
27
TXD1
PVDD
75
26
TXD0
PVSS
76
25
CRS
VC
77
24
TXCLK
EPTEST
78
23
VBUS
79
22
COL
80
21
VDD
XIN12M
XOUT12M
17
18
19
20
NC
NC
NC
NC
VSS
EXTWAKEUPN
MDIO
AVDD
16
10
AVSS
MDC
9
DM
15
8
AVSS
VDD
7
DP
14
6
AVSS
NC
5
AVSS
13
4
AVDD
NC
3
R1
12
2
11
1
Fig – 2 AX88172 Pin Connection Diagram
5
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AX88172
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2.0 Signal Description
The following terms describe the AX88172 pin-out:
All pin names with the “/” suffix are asserted low.
The following abbreviations are used in following Tables.
I
O
I/O
OD
Input
Output
Input/Output
Open Drain
SIGNAL
R1
AVDD
AVSS
AVSS
DP
AVSS
DM
AVSS
AVDD
/EXTWAKEUP
NC
NC
VDD
MDC
MDIO
NC
NC
NC
NC
VSS
VDD
COL
NC
TX_CLK
CRS
TXD[3:0]
PU
PD
P
Internal Pull Up (100K)
Internal Pull Down (100K)
Power Pin
TYPE
I
PIN NO.
DESCRIPTION
1
Constant-votage pin
A 6.2K± 1% resistors is connected to AVSS. Be sure to make the line
between R1 and each resistor as short as possible.
P
2
Power supply pin for analog circuits +3.3V DC
P
3
Power supply pin for analog circuits Ground
P
4
Power supply pin for analog circuits Ground
B
5
USB data line Data+
P
6
Power supply pin for analog circuits Ground
B
7
USB data line DataP
8
Power supply pin for analog circuits Ground
P
9
Power supply pin for analog circuits +3.3V DC
I/PU
10
Remote-wakeup trigger from external pin. It active low
and should be keep low over 2 clocks (12MHz)
B
11
For testing
B
12
For testing
P
13
Power Supply for logic circuits: +3.3V DC.
O
14
Station Management Data Clock: The timing reference for MDIO. All
data transfers on MDIO are synchronized to the rising edge of this
clock. MDC is a 2.5MHz frequency clock output.
I/O/PU
15
Station Management Data Input/Output: Serial data input/output
transfers from/to the PHYs. The transfer protocol conforms to the
IEEE 802.3u MII specification.
O
16
For testing
O
17
For testing
O
18
For testing
O
19
For testing
P
20
Power Supply: +0V DC or Ground Power.
P
21
Power Supply for logic circuits: +3.3V DC.
I
22
Collision: this signal is driven by PHY when collision is detected.
23
No connection
I
24
Transmit Clock: TX_CLK is a continuous clock from PHY. It
provides the timing reference for the transfer of the TX_EN and
TXD[3:0] signals from the MII port to the PHY.
I
25
Carrier Sense: Asynchronous signal CRS is asserted by the PHY
when either the transmit or receive medium is non-idle.
O
29, 28, 27, Transmit Data: TXD[3:0] is transition synchronously with respect to
26
the rising edge of TX_CLK. For each TX_CLK period in which
TX_EN is asserted, TXD[3:0] are accepted for transmission by the
PHY.
6
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AX88172
TX_EN
VDD
RX_CLK
RXD[3:0]
VDD
RX_ER
RX_DV
VSS
VDD
TEST0
TEST1
GPIO[2:0]
/PHYRST
PHYRST
VSS
NC
NC
LED
VDD
NC
NC
EECS
EECK
EEDI
EEDO
VSS
VDD
RST_TYPE
NC
ANA_XIQ
VDD
CLKI
TESTMODE
O
PRELIMINARY
30
Transmit Enable: TX_EN is transition synchronously with respect to
the rising edge of TX_CLK. TX_EN indicates that the port is
presenting nibbles on TXD [3:0] for transmission.
P
31
Power Supply for logic circuits: +3.3V DC.
I
32
Receive Clock: RX_CLK is a continuous clock that provides the
timing reference for the transfer of the RX_DV, RXD[3:0] and
RX_ER signals from the PHY to the MII port of the MAC.
I
36, 35, 34, Receive Data: RXD[3:0] is driven by the PHY synchronously with
33
respect to RX_CLK.
P
37
Power Supply for logic circuits: +3.3V DC.
I
38
Receive Error: RX_ER is driven by PHY and synchronous to
RX_CLK, is asserted for one or more RX_CLK periods to indicate to
the port that an error has detected.
I
39
Receive Data Valid: RX_DV is driven by the PHY synchronously
with respect to RX_CLK. Asserted high when valid data is present on
RXD [3:0].
P
40
Power Supply: +0V DC or Ground Power.
P
41
Power Supply for logic circuits: +3.3V DC.
I/PU
42
Test Pin: This pin for test purpose only.
Pull up the pin or keep no connection for normal operation.
I/PU
43
Test Pin: This pin for test purpose only.
Pull up the pin or keep no connection for normal operation.
I/O/PU 46, 45, 44 General Purpose Input/ Output Pins.
O
47
Output for reset PHY active low
O
48
Output for reset PHY active high
P
49
Power Supply: +0V DC or Ground Power.
I/PD
50
For testing
I/PD
51
For testing
O
52
LED indicator: When link FS, drives logic high always. When link
HS, the pin drives logic low. and it will drives high/low a period when
line has activity (data transfer).
P
53
Power Supply for logic circuits: +3.3V DC.
I/PD
54
For testing
ID
55
For testing
O
56
EEPROM Chip Select: EEPROM chip select signal.
O
57
EEPROM Clock: Signal connected to EEPROM clock pin.
O
58
EEPROM Data In: Signal connected to EEPROM data input pin.
I/PD
59
EEPROM Data Out: Signal connected to EEPROM data output pin.
P
60
Power Supply: +0V DC or Ground Power.
P
61
Power Supply for logic circuits: +3.3V DC.
I/PU
62
This pin define the assert level of Reset (pin 72)
When =’1’ or NC, reset signal is active High
When =’0’, reset signal is active Low
I/PD 63, 64, 65, For testing
66, 67
I
68
Sets the IQ mode
This pin is used during testing. It must be set to low in IQ
measurement mode.
0: IQ mode
1: Normal operation mode
P
69
Power Supply for logic circuits: +3.3V DC.
I/PD
70
External 60MHz input
I/PD
71
For testing (TESTMODE)
0: Normal operation mode
1: External clock Synchronization mode
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AX88172
PRELIMINARY
RESET/RESET
I
72
VSS
VDD
PVDD
PVSS
P
P
P
P
73
74
75
76
VC
I
77
PTEST
I
78
XIN12M
XOUT12M
I
O
79
80
Reset/Reset
Reset is active high/low depend on RST_TYPE (pin 62) definition.
When assert, place AX88172 into reset mode immediately. Reset
complete loads the EEPROM data.
Power Supply: +0V DC or Ground Power.
Power Supply for logic circuits: +3.3V DC.
Power supply pin for PLL and oscillator circuits +3.3V DC
Power supply pin for PLL and oscillator circuits +0V DC or Ground
Powe
Monitor pin for two PLL charge pumps
Connect to GND on PCB when actually using
Charge pump monitor ON/OFF:
Connect to GND on PCB when actually using
12M crystal oscillator input
12M crystal oscillator output
Tab - 1 PIN signals
8
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AX88172
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3.0 EEPROM Memory Mapping
EEPROM
OFFSET
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H-1FH
HIGH BYTE
LOW BYTE
RESERVED
WORD COUNT FOR PRELOAD
*FLAG
HIGH-SPEED LENGTH OF DEVICE
HIGH-SPEED EEPROM OFFSET OF DEVICE
DESCRIPTOR (BYTE)
DESCRIPTOR
HIGH-SPEED LENGTH OF CONFIGURATION
HIGH-SPEED EEPROM OFFSET OF
DESCRIPTOR (BYTE)
CONFIGURATION DESCRIPTOR
NODE ID 1
NODE ID 0
NODE ID 3
NODE ID 2
NODE ID 5
NODE ID 4
LANGUAGE ID HIGH BYTE
LANGUAGE ID LOW BYTE
LENGTH OF STRING INDEX 1
EEPROM OFFSET OF STRING INDEX 1
LENGTH OF STRING INDEX 2
EEPROM OFFSET OF STRING INDEX 2
LENGTH OF STRING INDEX 3
EEPROM OFFSET OF STRING INDEX 3
LENGTH OF STRING INDEX 4
EEPROM OFFSET OF STRING INDEX 4
LENGTH OF STRING INDEX 5
EEPROM OFFSET OF STRING INDEX 5
LENGTH OF STRING INDEX 6
EEPROM OFFSET OF STRING INDEX 6
LENGTH OF STRING INDEX 7
EEPROM OFFSET OF STRING INDEX 7
RESERVED
RESERVED
MAX PACKETSIZE HIGH BYTE
MAX PACKET LOW BYTE
**(PHY TYPE[7:5]) (SECONDARY PHY
**(PHY TYPE[7:5])(FIRST PHY ID[4:0] )
ID[4:0])
PAUSE PACKET HIGH WATER LEVEL
PAUSE PACKET LOW WATER LEVEL
FULL-SPEED LENGTH OF DEVICE
FULL-SPEED EEPROM OFFSET OF DEVICE
DESCRIPTOR (BYTE)
DESCRIPTOR
FULL-SPEED LENGTH OF CONFIGURATION
FULL-SPEED EEPROM OFFSET OF
DESCRIPTOR (BYTE)
CONFIGURATION DESCRIPTOR
RESERVED
RESERVED
Tab - 2 EEPROM Memory Mapping
Note:
*FLAG:
Bit0
Self Powered (for USB GetStatus) 1: self power ; 0 : bus power
Bit 1
Reserved
Bit 2
RemoteWakeUP support
Bit 3
1
Bit 4 –5
Reserved
Bit 6
RX drop CRC Enable
Bit 7
TX append CRC enable
Bit 8
Capture Effective Mode
Bit 9 – F
Reserved
9
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** PHY TYPE[7:5]
3’b000 = 10/100 Ethernet PHY or 1M HOME PHY (Link report as normal case)
3’b100 = special case 1 (Link report always active)
3’b101 = reserved
3’b111 = No supported PHY
FOR EXAMPLE: EEPROM OFFSET 11 HIGH BYTE IS “E0” MEAN IS NO SUPPORTED
SECONDARY PHY.
***Unicode MAC Address:
If the MAC’s NODE ID is 01,23,45,67,89,ABh respect to NODE ID 0, NODE ID 1, … NODE ID5
Then the unicode will be 30-31,32-33,34-35,36-37,38-39,41-42h respects to BYTE 1 OF UNICODE MAC
ADDRESS- BYTE 2 OF UNICODE MAC ADDRESS, …-BYTE 12 OF UNICODE MAC ADDRESS.
Isolate 2 PHY step procedure by hardware when every hardware reset
1.
write 0 PHY_ID isolate and power down
2.
write PRIMARILY PHY ID isolate and power down
3.
write SECONDARY PHY ID isolate and power down
10
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4.0 USB Commands
There are three command groups for Endpoint 0 in AX88172:
The USB standard commands
USB Communication Class commands
USB vendor commands.
4.1 USB standard commands
The Language ID is 0x0904 for English
PPLL means buffer length
CC means configuration number
I I means Interface number
SETUP COMMAND
80 06 00 01 00 00 LL PP
80 06 00 02 00 00 LL PP
80 06 00 03 00 00 LL PP
80 06 01 03 09 04 LL PP
80 06 02 03 09 04 LL PP
80 06 03 03 09 04 LL PP
80 06 04 03 09 04 LL PP
80 06 05 03 09 04 LL PP
80 06 06 03 09 04 LL PP
80 06 07 03 09 04 LL PP
80 06 08 03 09 04 LL PP
80 08 00 00 00 00 01 00
00 09 CC 00 00 00 00 00
81 0A 00 00 I I 00 01 00
01 0B AS 00 00 00 00 00
Tab - 3 USB stabdard commands
DATA IN/OUT
Data PPLL bytes
Data PPLL bytes
Data 2 bytes
Data PPLL bytes
Data PPLL bytes
Data PPLL bytes
Data PPLL bytes
Data PPLL bytes
Data PPLL bytes
Data PPLL bytes
Data 12 bytes
Data 1 bytes
No Data
Data 1 byte
No Data
11
DESCRIPTION
Get Device Descriptor
Get Configuration Descriptor
Get Supported Language ID
Get Manufacture String
Get Product String
Get Serial Number String
Get Configuration String
Get Interface 0 String
Get Interface 1/0 String
Get Interface 1/1 Stirng
Get Ethernet Address String
Get Configuration
Set Configuration
Get Interface
Set Interface
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4.2 USB Vendor Commands
SETUP COMMAND
C0 02 XX YY 0M 00 02 00
DATA IN/OUT
Data 2 bytes
40 03 XX YY PP QQ 00 00
40 04 XX YY PP QQ 00 00
40 06 00 00 00 00 00 00
C0 07 PI 00 RG 00 02 00
40 08 PI 00 RG 00 02 00
C0 09 00 00 00 00 01 00
40 0A 00 00 00 00 00 00
C0 0B DR 00 00 00 02 00
40 0C DR 00 MM SS 00 00
40 0D 00 00 00 00 00 00
40 0E 00 00 00 00 00 00
C0 0F 00 00 00 00 02 00
40 10 RR 00 00 00 00 00
C0 11 00 00 00 00 03 00
40 12 II 00 00 00 00 00
40 13 II 00 00 00 00 00
40 14 II 00 00 00 00 00
C0 15 00 00 00 00 08 00
40 16 00 00 00 00 08 00
C0 17 00 00 00 00 06 00
C0 19 00 00 00 00 02 00
C0 1A 00 00 00 00 01 00
40 1B MM 00 00 00 00 00
C0 1C 00 00 00 00 01 00
40 1D MM 00 00 00 00 00
C0 1E 00 00 00 00 01 00
40 1F MM 00 00 00 00 00
No Data
No Data
No Data
Data 2 Bytes
Data 2 Bytes
Data 1 Bytes
No Data
Data 2 Bytes
No Data
No Data
No Data
Data 2 Bytes
No Data
Data 3 Bytes
No Data
No Data
No Data
Data 8 Bytes
Data 8 Bytes
Data 6 Bytes
Data 2 Bytes (*)
Data 1 Byte
No Data
Data 1 Byte
No Data
Data 1 Byte
No Data
DESCRIPTION
Read Rx/Tx SRAM
M = 0 : Rx, M=1 : Tx
Write Rx SRAM
Write Tx SRAM
Software MII Operation
Read MII Register
Write MII Register
Read MII Operation Mode
Hardware MII Operation
Read SROM
Write SROM
Write SROM Enable
Write SROM Disable
Read Rx Control Register
Write Rx Control Register
Read IPG/IPG1/IPG2 Register
Write IPG Register
Write IPG1 Register
Write IPG2 Register
Read Multi-Filter Array
Write Multi-Filter Array
Read Node ID
Read Ethernet/HomePNA PhyID
Read Medium Status (**)
Write Medium Mode (**)
Get Monitor Mode Status (***)
Set Monitor Mode On/Off (***)
Read GPIOs (****)
Write GPIOs (****)
* Note1: read 1st byte is Secondary PHY ID; 2nd byte is Primarily PHY ID
** Read / Write Medium status
Bit7 Bit6 Bit5 Bit4
Read
X
X
X
Flow_Control_En
Write X
X
X
Flow_Control_En
*** Read / Write Monitor Mode
Bit7-5
Bit4 Bit3
Read
3’b101
HS/FS X
Write X
X
X
**** Read / Write GPIO
Bit7
Bit6
Read
Write
Bit5
GPI2
GPO2
Bit3
Bit2
TxAbortAllow
TxAbortAllow
X
Bit2
Magic_Packet_En
Magic_Packet_En
Bit4
GPO2EN
GPO2EN
12
Bit3
GPI1
GPO1
Bit1
Full_Duplex
Full_Duplex
Bit1
Link_UP_Wake
Link_UP_Wake
Bit2
GPO1EN
GPO1EN
Bit1
GPI0
GPO0
Bit0
X
Bit0
Monitor_Mode
Monitor_Mode
Bit0
GPO0EN
GPO0EN
ASIX ELECTRONICS CORPORATION
AX88172
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Interrupt endpoint frame format
Byte Number
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
A1 Fixed value 00
00 Fixed value 00
NN Bit_1: SECONDARY PHY Link state (active high),
Bit_0: PRIMARILY PHY LINK STATE
00 Fixed value 00
00 Fixed value 00
80 90h
00 Fixed value 00
00 Fixed value
13
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5.0 USB Configuration Structure
5.1 USB Configuration.
The AX88172 supports 1 Configuration only.
5.2 USB Interface.
The AX88172 supports 2 interfaces, the interface 0 is Data Interface and interface 1 is for Communication Interface.
5.3 USB Endpoints.
The AX88172 supports 4 endpoints.
Endpoint 0
Control endpoint, it is for configuring device.
Endpoint 1
(optional) Interrupt endpoint, it is for reporting status
Endpoint 2 Bulk Out endpoint, it is for Transmitting Ethernet Packet.
Endpoint 3
Bulk In endpoint, it is for Receiving Ethernet Packet.
14
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6.0 Electrical Specification and Timings
6.1 Absolute Maximum Ratings
Description
SYM
Min
Max
Units
Operating Temperature
Ta
0
+85
°C
Storage Temperature
Ts
-65
+150
°C
Supply Voltage
Vdd
-0.3
+3.6
V
Input Voltage
Vin
-0.3
Vdd+0.3
V
Output Voltage
Vout
-0.3
Vdd+0.3
V
Lead Temperature (soldering 10 seconds maximum)
Tl
-55
+240
°C
Note: Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure
to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability.
6.2 General Operation Conditions
Description
Operating Temperature
Supply Voltage
SYM
Min
Ta
0
Vdd
+3.0
Tpy
25
+3.30
Max
+70
+3.6
Units
°C
V
6.3 DC Characteristics
(Vdd=3.0V to 3.6V, Vss=0V, Ta=0°C to 70°C)
Description
Low Input Voltage
High Input Voltage
Low Output Voltage
High Output Voltage
Input Leakage Current
Output Leakage Current
Input Pull-up / down resistance
SYM
Vil
Vih
Vol
Voh
Iil
Iol
Ri
Description
Power Consumption (3.3V)
SYM
SPt3v
15
Min
Tpy
Max
0.3*Vdd
0.4
+1
+10
Units
V
V
V
V
uA
uA
K ohm
Tpy
Max
Units
mA
0.7*Vdd
2.4
-1
-10
75
Min
150
ASIX ELECTRONICS CORPORATION
AX88172
PRELIMINARY
6.4 A.C. Timing Characteristics
6.4.1 12M_XIN (CL=16pF, +/-50ppm)
Thigh
12M_XIN
Tr
Tf
Tlow
Tcyc
Symbol
Tcyc
Thigh
Tlow
Tr/Tf
Description
Min
CYCLE TIME
CLK HIGH TIME
CLK LOW TIME
CLK SLEW RATE
34.71
34.71
1
Typ.
83.33
41.66
41.66
-
Max
49.99
49.99
4
Min
100
Typ.
-
Max
-
Units
ns
ns
ns
ns
6.4.2 Reset Timing
12M_XIN
RESET/RESET
Symbol
Trst
Description
Reset pulse width (6ms ~10ms)
16
Units
12M
_XIN
ASIX ELECTRONICS CORPORATION
AX88172
PRELIMINARY
6.4.3 MII Timing
Ttclk
Ttch
Ttcl
TXCLK(in)
Ttv
Tth
TXD<3:0>(out)
TXEN(out)
Trclk
Trch
Trcl
RXCLK(in)
Trs
Trh
RXD<3:0>(in)
RXDV(in)
Trs1
RXER(in)
CRS(in)
Symbol
Ttclk
Ttclk
Ttch
Ttch
Trch
Trch
Ttv
Tth
Trclk
Trclk
Trch
Trch
Trcl
Trcl
Trs
Trh
Trs1
Description
Min
14
140
14
140
3
3
14
140
14
140
6
6
6
Cycle time(100Mbps)
Cycle time(10Mbps)
high time(100Mbps)
high time(10Mbps)
low time(100Mbps)
low time(10Mbps)
Clock to data valid
Data output hold time
Cycle time(100Mbps)
Cycle time(10Mbps)
high time(100Mbps)
high time(10Mbps)
low time(100Mbps)
low time(10Mbps)
data setup time
data hold time
RXER data setup time
17
Typ.
40
400
40
400
-
Max
26
260
26
260
10
10
26
260
26
260
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88172
PRELIMINARY
6.4.4 STATION MANAGEMENT TIMING
Tclk
MDC
Tch
Tcl
Tod
MDIO
(output)
Ts
Th
MDIO
(input)
Symbol
Tclk
Tch
Tcl
Tod
Ts
Th
Description
MDC Clock Cycle Time
MDC Clock High Time
MDC Clock Low Time
Clock Falling Edge to Output Valid Delay
Data In Setup Time
Data In Hold Time
Min
0
10
100
18
Typ.
375
1328
1328
Max
2
Units
KHz
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88172
PRELIMINARY
6.4.5 SERIAL EEPROM TIMING
Tclk
EECK
Tcl
Tch
Tdv
EEDI
(output)
Tod
VALID
VALID
Tscs
Thcs
Tlcs
Typ.
187.5
2666
2666
Max
EECS
Th
Ts
EEDO
(input)
Symbol
Tclk
Tch
Tcl
Tdv
Tod
Tscs
Thcs
Tlcs
Ts
Th
DATA VALID
Description
EECK Clock Cycle Time
EECK Clock High Time
EECK Clock Low Time
EEDI Data Valid Output to EECK High Time
EECK High to EEDI Data Output Delay Time
EECS Valid to EECK High Time
EECK Low to EECS Invalid Time
Minimum EECS Low Time
Data Input Setup Time
Data Input Hold Time
Min
2666
2666
2666
0
23904
10
100
19
Units
KHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88172
PRELIMINARY
7.0 Package Information
A
A2
A1
L
L1
D
Hd
He
E
pin 1
e
b
θ
SYMBOL
MILIMETER
MIN.
NOM
MAX
A1
0.05
0.1
0.15
A2
1.3
1.40
1.5
A
1.70
b
0.175
0.18
0.28
D
11.9
12.00
12.1
E
11.9
12.00
12.1
e
0.5
Hd
13.6
14.00
14.4
He
13.6
14.00
14.4
L
0.3
0.50
0.7
L1
θ
1.00
0°
10°
20
ASIX ELECTRONICS CORPORATION
AX88172
PRELIMINARY
Appendix A: System Applications
Some typical applications for AX88170 are illustrated bellow.
A.1 USB to Fast Ethernet Converter
RJ45
MAGNETIC
10/100 PHY/TxRx
AX88172
EEPROM
USB I/F
A.2 USB to Fast Ethernet and/or HomeLAN Combo solution
RJ11
RJ45
MAGNETIC
MAGNETIC
10/100 Mbps
Ethernet PHY/TxRx
1/10 Mbps
Home LAN PHY
AX88172
EEPROM
USB I/F
21
ASIX ELECTRONICS CORPORATION
AX88172
USB to Fast Ethernet/HomePNA Controller
Demonstration Circuit A: AX88172 (ED2 version) + Ethernet PHY(8201L)
USB Port Link/Act LED
VDD3L
D1
DC 5.0V POWER
OPTION
R1
TXD0
VDD5
D2
/PHY_RST
L1
F.BEAD.
VDD3L
R3
VDD3L
60MHz
VDD3L
RST
GND
10K
VDD3
PVDD
PVSS
C4
0.1u
GND
GND
C6
C8
GND
RXDV
RXER
VDD3L
RXD3
RXD2
RXD1
RXD0
RX_CLK
VDD3L
TXEN
TXD3
TXD2
TXD1
TXD0
CRS
TX_CLK
J2
DPLUS
DMINUS
4
1
3
2
1
GND
VDD5
D+
D-
4
2
U2
EECS
EECK
EEDI
EEDO
3
1
2
3
4
CS
SK
DI
DO
VCC
NC
NC
GND
8
7
6
5
VDD3
C3
COL
VDD3L
C5
COL
0.01u
CRS
ADJ/GND
C19
+ C18
R7
VDD3L
GND
HIGH : USED "U2" ONLY.
LOW : USED "R8" ONLY.
U3 : TOREX / XC74UL14AAMR
U3
8
VCC
33
5
60MHz
C15
0.1u
5
VDD3
GND
Y
4
RST
XC74UL14
0.47uF
60MHz
R9
C17
0.1u
VCC
A
3
C13
4
GND
F.BEAD.
C14
0.1u
NC
2
OUT
F.BEAD.
VDD3
+ C20
0
10u/16V
47u/16V
1206 & DIP
VDD3L
L7
AVSS and PVSS :
Single-point ground
F.BEAD.
L8
VDD3
0.1u
VDD3
RESET ACTIVE
15K
R8
47u/16V
C21
CRS
RESET ACTIVE
1
2
C16 +
COL
OPTION
OPTION
U4
1
MDIO
GND
0.1u
AMS1117
0.01u
MDC
VDD3
SW PUSHBUTTON
L6
/PHY_RST
MDIO
0.1u
1206 & DIP
VOUT
RXER
MDC
93C56
L5
VIN
RXDV
/PHY_RST
AX88172
C10
U5
RX_CLK
S1
VDD3
3
RXD3
RXER
0.1u
USB-CON
C11
1206 & DIP
RXD2
RXDV
C12
VDD5
RXD1
RX_CLK
OPTION
(Next version chip)
C9
0.1u
RXD0
RXD3
VDD3
0.1u
TXEN
RXD2
S
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSS
RXDV
RXER
VDD
RXD3
RXD2
RXD1
RXD0
RXCLK
VDD
TXEN
TXD3
TXD2
TXD1
TXD0
CRS
TXCLK
NC
COL
VDD
R6
6.2K 1%
TX_CLK
TXEN
RXD1
1M
220
TXD3
TX_CLK
J1
0.1u
R5
24P
3
2
1
RXD0
GND
R4
VDD3L
MDC
MDIO
AVDD
AVSS
AVSS
DPLUS
AVSS
DMINUS
AVSS
AVDD
C7
Y1
12.000MHz
F.BEAD.
TXD2
TXD3
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
AX88172
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
0.1u
24P
L4
1000P
TXD1
TXD2
JACK
F.BEAD.
C2
S
0
VDD
RST_TYPE
NC
NC
NC
NC
NC
ANA_XIQ
VDD
CLKI
TESTMODE
RESET
VSS
VDD
PVDD
PVSS
VC
PTEST
XIN12M
XOUT12M
VSS
EEDO
EEDI
EECK
EECS
NC
SPEEDUP
VDD
LED
ATPGEN
NC
VSS
PHYRSTP
PHYRSTN
GPIO2
GPIO1
GPIO0
TEST1
TEST0
VDD
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
R1
AVDD
AVSS
AVSS
DP
AVSS
DM
AVSS
AVDD
EXTWAKEUPN
NC
NC
VDD
MDC
MDIO
NC
NC
NC
NC
VSS
VDD3L
F.BEAD.
DC POWER
DIODE
C1
L3
U1
R2
L2
VDD3L
GND
0 : PIN72 RESET ACTIVE LOW.
GND
EEDO
EEDI
EECK
EECS
OPTION
1 / NC : PIN72 RESET ACTIVE HIGH.
VDD3L
LED
LED
TXD0
TXD1
1206 & DIP
1K
C22
0.1u
C23
0.1u
C24
0.1u
C25
0.1u
C26
0.1u
C27
0.1u
C28
0.1u
F.BEAD.
VDD3
AVDD
PVDD
C29
+ C30
0.1u
C31
0.1u
GND
22u
GND
C32
0.1u
C33
0.01u
AVSS
C36
C34
0.1u
GND
+ C35
22u
Title
C37
0.1u
0.01u
PVSS
AX88172 DEMO Board
Size
B
1206 & DIP
1206 & DIP
22
Date:
Document Number
Rev
2.1
AX88172
Friday, May 31, 2002
Sheet
1
of
2
ASIX ELECTRONICS CORPORATION
AX88172
USB to Fast Ethernet/HomePNA Controller
MDC
MDC
U5
VDD3
R10
REALTEK
RTL8201
1.5K
U6
TX_CLK
RXDV
RXD0
RXD1
RXD2
RXD3
20
R14
RX_CLK
20
COL
CRS
RXER
X1
X2
R15
2K
LED0
LED1
LED2
LED3
LED4
9
10
12
13
15
DVDD0
VDD3
8
14
GND
11
17
MDC
MDIO
TXD0
TXD1
TXD2
TXD3
TXEN
TXC
RXDV
RXD0
RXD1
RXD2
RXD3
RXC
COL
CRS
RXER
X1
X2
AVDD0
AVDD1
AVDD2
RTL 8201
AGND
AGND
AGND
RTT3/VCTRL
TPTX+
TPTXTPRX+
TPRX-
LED0/PHYA0
LED1/PHYA1
LED2/PHYA2
LED3/PHYA3
LED3/PHYA4
RTSET
ISOLATE
REPT
SPEED
DUPLEX
ANE
LDPS
MII/SNIB
RESETB
DVDD0
DVDD1
DGND
DGND
32
36
48
AVDD0
AVDD1
AVDD2
29
35
45
GND
GND
GND
VDD3
R11
R12
49.9
49.9
U6 : BOTHHAND / TS6121A
27
U7
34
1
2
3
33
31
6
7
8
30
28
43
40
39
38
37
41
44
42
R16
R19
R20
R25
R26
R27
R28
R29
2K 1%
1K
1K
1K
1K
1K
1K
1K
16
15
14
6
7
8
11
10
9
1
2
3
6
11
10
9
4
5
7
8
R21
C38
75
R22
75
R23
75
R24
75
RJ45
0.01u
VDD3
C39
0.01u
C40
0.01u
/PHY_RST
J3
TX+
TXRX+
RX-
16
15
14
TS6121A
R18
49.9
R17
49.9
1
2
3
S
R13
25
26
6
5
4
3
2
7
22
21
20
19
18
16
1
23
24
46
47
MDIO
TXD0
TXD1
TXD2
TXD3
TXEN
TXC
RXDV
RXD0
RXD1
RXD2
RXD3
RXC
COL
CRS
RXER
S
MDIO
TXD0
TXD1
TXD2
TXD3
TXEN
C42
0.01u
/PHY_RST
C41
0.01u/2KV
RTL8201
( CONNECT TO CHASIS GND )
Set PHY ADDRESS TO 00011
VDD3
L9
F.BEAD.
VDD3
L10
AVDD2
F.BEAD.
AVDD1
R30
C43
C44
C45
0.1u
0.1u
0.1u
4.7K
D3
LED0
R31
510
Link LED
LED
R32
4.7K
D4
L11
F.BEAD.
VDD3
L12
DVDD0
LED1
F.BEAD.
AVDD0
R33
510
FULL LED
LED
C46
C47
C48
0.1u
0.1u
0.1u
R34
D5
4.7K
R35
510
LED2
Link 10-Active
LED
R36
VDD3
R37
VDD3
1M
D6
C50
+
Y2
10uF/16V
GND
R38
510
LED3
C49
1206 & DIP
4.7K
0.1u
CRYSTAL 25.000 MHz
R39
0
Link 100-Active
LED
X2
X1
C51
20P
R40
C52
20P
D7
LED4
4.7K
R41
510
COLL
LED
Title
AX88172 DEMO Board
Size
B
Date:
23
Document Number
Rev
2.1
RTL8201-TS6121A
Friday, May 31, 2002
Sheet
2
of
2
ASIX ELECTRONICS CORPORATION
AX88172
USB to Fast Ethernet/HomePNA Controller
Demonstration Circuit B: AX88172 (ED3 version) + Ethernet PHY (8201LBL)
USB Port Link/Act LED
VDD3L
D1
R1
TXD0
VDD5
C1
10K
R3
VDD3L
RST
GND
VDD3
PVDD
PVSS
C3
0.1u
GND
GND
C5
F.BEAD.
TX_CLK
TXEN
1000P
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
0.1u
AX88172
TXD3
TX_CLK
TXEN
RXD0
RXD0
RXD1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSS
RXDV
RXER
VDD
RXD3
RXD2
RXD1
RXD0
RXCLK
VDD
TXEN
TXD3
TXD2
TXD1
TXD0
CRS
TXCLK
NC
COL
VDD
GND
RXDV
RXER
VDD3L
RXD3
RXD2
RXD1
RXD0
RX_CLK
VDD3L
TXEN
TXD3
TXD2
TXD1
TXD0
CRS
TX_CLK
J1
DPLUS
DMINUS
4
1
3
2
RXD1
RXD2
GND
VDD5
D+
D-
S
VDD3L
TXD2
TXD3
RXD3
1
4
RX_CLK
2
3
RXD2
RXD3
RX_CLK
RXDV
RXDV
RXER
S
0
VDD
RST_TYPE
NC
NC
NC
NC
NC
ANA_XIQ
VDD
CLKI
TESTMODE
RESET
VSS
VDD
PVDD
PVSS
VC
PTEST
XIN12M
XOUT12M
VSS
EEDO
EEDI
EECK
EECS
NC
SPEEDUP
VDD
LED
ATPGEN
NC
VSS
PHYRSTP
PHYRSTN
GPIO2
GPIO1
GPIO0
TEST1
TEST0
VDD
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
R1
AVDD
AVSS
AVSS
DP
AVSS
DM
AVSS
AVDD
EXTWAKEUPN
NC
NC
VDD
MDC
MDIO
NC
NC
NC
NC
VSS
VDD3L
R2
TXD1
TXD2
F.BEAD.
VDD3L
/PHY_RST
GND
VDD3L
LED
GND
EEDO
EEDI
EECK
EECS
L1
L2
U2
TXD0
TXD1
1K
LED
RXER
/PHY_RST
USB-CON
/PHY_RST
MDC
MDC
MDIO
COL
VDD3L
C4
COL
0.01u
CRS
MDIO
COL
CRS
VDD3
VDD3
GND
AX88172
GND
GND
Y1
12.000MHz
VDD3L
MDC
MDIO
R6
24P
C7
AVDD
AVSS
AVSS
DPLUS
AVSS
DMINUS
AVSS
AVDD
C6
U1
1M
EECS
EECK
EEDI
EEDO
R7
R8
220
24P
VDD3
1
2
3
4
C9
6.2K 1%
CS
SK
DI
DO
VCC
NC
NC
GND
8
7
6
5
VDD3
C2
0.1u
93C56
C8
0.1u
0.1u
R9
C11
15K
C10
0.1u
R11
0.1u
RST
VDD3
VDD3L
0
C14
1206 & DIP
1206 & DIP
U4
VDD5
3
VOUT
VIN
ADJ/GND
C18
+ C17
L4
0.47uF
C16
1
C15 +
0.1u
AMS1117
0.01u
F.BEAD.
2
AVSS and PVSS :
Single-point
ground
+ C19
10u/16V
47u/16V
47u/16V
1206 & DIP
VDD3L
L5
F.BEAD.
L6
VDD3
C20
0.1u
C21
0.1u
C22
0.1u
C23
0.1u
C24
0.1u
C25
0.1u
C26
0.1u
C27
0.1u
F.BEAD.
VDD3
AVDD
PVDD
C28
+ C29
0.1u
C30
0.1u
GND
22u
GND
C31
0.1u
C32
C35
0.01u
AVSS
C33
0.1u
GND
+ C34
22u
Title
C36
0.1u
0.01u
PVSS
AX88172 DEMO Board ED3
Size
B
1206 & DIP
1206 & DIP
24
Date:
Document Number
Rev
2.2
AX88172
Friday, October 04, 2002
Sheet
1
of
2
ASIX ELECTRONICS CORPORATION
AX88172
VDD3
MDC
R12
USB to Fast Ethernet/HomePNA Controller
MDC
1.5K
U5
MDIO
MDIO
TXD0
TXD1
TXD2
TXD3
TXEN
TX_CLK
TXD0
TXD1
TXD2
TXD3
TXEN
R15
20
TXC
RXDV
RXD0
RXD1
RXD2
RXD3
R16 20
COL
CRS
RXER
RXDV
RXD0
RXD1
RXD2
RXD3
RX_CLK
COL
CRS
RXER
RXC
X1
X2
R17
LED0/PHYAD0
LED1/PHYAD1
LED2/PHYAD2
LED3/PHYAD3
LED4/PHYAD4
2K
DVDD25
VDD3
VDD3
25
26
6
5
4
3
2
7
22
21
20
19
18
16
1
23
24
46
47
9
10
12
13
15
8
14
48
11
17
45
MDC
MDIO
TXD0
TXD1
TXD2
TXD3
TXEN
TXC
RXDV
RXD0
RXD1
RXD2
RXD3
RXC
COL
CRS
RXER/FXEN
X1
X2
AVDD25
AVDD33
AVDD25
32
36
AVDD25
AVDD3
C38
0.1U
0.1U
GND
AGND
AGND
29
35
R13
50
GND
R14
50
U6
NC
RTL8201BL
1
1
31
30
3
15
TPTXTPTX+
33
34
14
16
RTSET
ISOLATE
RPTR
SPEED
DUPLEX
ANE
LDPS
MII/SNIB/RTT3
RESETB
DVDD25
DVDD33
DVDD33
28
43
40
39
38
37
41
44
42
RD+
RX+
RD-
CT
CT
RX-
TD-
TX-
CT
CMT
TD+
TX+
7
2
5
3
6
4
11
5
12
6
10
7
8
PE68515
R18
50
for EMI supression
U7
27
2
TPRX+
TPRX-
LED0/PHYAD0
LED1/PHYAD1
LED2/PHYAD2
LED3/PHYAD3
LED4/PHYAD4
R19
50
TX+
TXRX+
C39
0.1U
GND
C40
0.1U
GND
N/C
N/C
RXN/C
N/C
9
GND
RJ8-45
R20
5.6K (1%)
R21
75
R22
75
R23
75
R24
75
CH_GND
PHY_RST
(CONNECT TO CHASSIS GND)
GND
DGND
DGND
AGND
GND
GND
C37
C41
0.1U
GND
C42
0.01U/3KV
RTL8201BL LQFP48
R25
5.1K
R26
5.1K
R18 value need fine tune,
the range may from 2K to
5.6K
R27
5.1K
R32
R34
R29
5.1K
R30
5.1K
R31
5.1K
R33
510
Link LED
1. This configuration shows
Enable: Auto negotiation, Full duplex, 100Mbps,
Link Down Power Saving, MII interface
Disable: Isolate, Repeater mode
2. These senven configuration pins could be connected to VDD
or GND directly.
VDD3
4.7K
D2
LED0
R28
5.1K
VDD3
Set PHY ADDRESS TO 00011
Hardwire Configuration network:
GND
Y2
1M
CRYSTAL 25.000 MHz
R35
0
X2
X1
L7
LED
R36
4.7K
C43
20P
D3
LED1
R37
510
FULL LED
D4
AVDD3
VDD3
VDD3
C49
0.1U
GND
GND
C50
0.1U
Link 10-Active
GND
LED
R40
D5
4.7K
R41
BEAD
C45
22U
GND
510
LED2
U1/pin48
L8
C48
0.1U
4.7K
R39
U1/pin14
BEAD
LED
R38
VDD3
DVDD25
AVDD25
C44
20P
C46
0.1U
GND
C47
0.1U
GND
RTL8201BL has built in 3.3V to 2.5V regulator, and
pin 8(AVDD25) sources out 2.5V. A 22uF capacitir
and a 0.1uF capacitor are recommended between
AVDD25 and GND. Place C14, C15, L4 close to AVDD25
and place C11 close to DVDD25.
Place L2, C17, C18, C19 as close to each power pin
as possible.
510
LED3
Link 100-Active
LED
R42
4.7K
Title
D6
LED4
R43
RTL8201BL application circuit - interface with MAC(MII)
510
COLL
Size
B
LED
Date:
25
Document Number
RTL8201BL MII1.0
Friday, December 20, 2002
Rev
2.2
Sheet
2
of
2
ASIX ELECTRONICS CORPORATION
AX88172
PRELIMINARY
Remark:
The schematic change between ED2 and ED3 are shown following:
1.
2.
3.
4.
60MHZ oscillator is no longer needed
AX88172 Pin 23 need coonect to VBUS in ED3
Pin 70 (CLKI) changes from 60MHz OSC to NC,
Pin 71 (test mode) from VDD3L to NC.
26
AX88172
PRELIMINARY
Revisions history
Revision
Date
V. 1.0
V.1.1
12/25/01
12/28/01
V.1.2
V.1.3
V.1.4
Comment
Initial Release
Pin 62 change from “SROM size to NC”
R1 change from 6K +/-1% to 6.2K+/-1%
Power on reset specific 6ms ~10ms
“Primary”PHY ID change to “First” PHY ID in
EEPROM memory mapping
2002/2/25 Pin 62 change from “NC” to “RST_TYPE”
Pin 72 change from “RESET” to”RESET/RESET”
On page 12 modify following:
USB vendor command modify from “disable H/W
MII operation” to “Software MII operation”
USB vendor command modify from “Enable H/W MII
operation” to “Hardware MII operation”
Read/write Mointor mode at read bit 7-5 change
from 100 to 101”
Add /Reset timing
Reference design schematic updated
BOM update
2002/5/7 Chip ED2 new schematic with external 60 MHZ
Add RTl 8201 BL version schematic
Remove BOM
2002/12/20 Add ED3 reference design with RTL 8201BL version
PHY and remark the difference
Add 12M osc spec
27
AX88172
PRELIMINARY
4F, NO.8, HSIN ANN RD., SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R.O.C.
TEL: 886-3-5799500
FAX: 886-3-5799558
Email: support@asix.com.tw
Web: http://www.asix.com.tw
28