SRAM Austin Semiconductor, Inc. GENERAL DESCRIPTION 128K x 36 SSRAM The Austin Semiconductor, Inc. Zero Bus Latency SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. ASI’s 4Mb ZBL SRAMs integrate a 128K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMS are optimized for 100 percent bus utilization, eliminating any turnaround cycles for READ to WRITE, or WRITE to READ, transitions. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, chip enable (CE\), two additional chip enables for easy depth expansion (CE2, CE2\), cycle start input (ADV/LD\), synchronous clock enable (CKE\), byte write enables (BWa\, BWb\, BWc\, and BWd\) and read/write (R/ W\). Asynchronous inputs include the output enable (OE\, which may be tied LOW for control signal minimization), clock (CLK) and snooze enable (ZZ, which may be tied LOW if unused). There is also a burst mode pin (MODE) that selects between interleaved and linear burst modes. MODE may be tied HIGH, LOW or left unconnected if burst is unused. The flow-through data-out (Q) is enabled by OE\. WRITE cycles can be from one to four bytes wide as controlled by the write control inputs. All READ, WRITE and DESELECT cycles are initiated by the ADV/LD\ input. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV/LD\). Use of burst mode is optional. It is allowable to give an address for each individual READ and WRITE cycle. BURST cycles wrap around after the fourth access from a base address. To allow for continuous, 100 percent use of the data bus, the flow-through ZBL SRAM uses a LATE WRITE cycle. For example, if a WRITE cycle begins in clock cycle one, the address is present on rising edge one. BYTE WRITEs need to be asserted on the same cycle as the address. The write data associated with the address is required one cycle later, or on the rising edge of clock cycle two. Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During a BYTE WRITE cycle, BWa\ controls DQa pins; BWb\ controls DQb pins; BWc\ controls DQc pins; and BWd\ controls DQd pins. Cycle types can only be defined when an address is loaded, i.e., when ADV/LD\ is LOW. Parity/ECC bits are available on this device. Austin’s 4Mb ZBL SRAMs operate from a +3.3V VDD power supply, and all inputs and outputs are LVTTL-compatible. The device is ideally suited for systems requiring high bandwidth and zero bus turnaround delays. SYNCHRONOUS ZBL SRAM FLOW-THRU OUTPUT FEATURES • High frequency and 100% bus utilization • Fast cycle times: 11ns & 12ns • Single +3.3V +5% power supply (VDD) • Advanced control logic for minimum control signal interface • Individual BYTE WRITE controls may be tied LOW • Single R/W\ (READ/WRITE) control pin • CKE\ pin to enable clock and suspend operations • Three chip enables for simple depth expansion • Clock-controlled and registered addresses, data I/Os and control signals • Internally self-timed, fully coherent WRITE • Internally self-timed, registered outputs to eliminate the need to control OE\ • SNOOZE MODE for reduced-power standby • Common data inputs and data outputs • Linear or Interleaved Burst Modes • Burst feature (optional) • Pin/function compatibility with 2Mb, 8Mb, and 16Mb ZBL SRAM • Automatic power-down OPTIONS AS5SS128K36 MARKING • Timing (Access/Cycle/MHz) 8.5ns/11ns/90 MHz 9ns/12ns/83 MHz -11 -12 • Packages 100-pin TQFP DQ • Operating Temperature Ranges Military (-55oC to +125oC) Industrial (-40oC to +85oC) XT IT No. 1001 For more products and information please visit our web site at www.austinsemiconductor.com AS5SS128K36 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 SRAM AS5SS128K36 Austin Semiconductor, Inc. PIN ASSIGNMENT (Top View) SA SA CE\ CE2 BWd\ BWc\ BWb\ BWa\ CE2\ VDD VSS CLK R/W\ CKE\ OE\ (G\) ADV/LD\ NF NF SA SA 100-pin TQFP (DQ) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PIN DESCRIPTIONS DQb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS VSS VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQa SA1 SA0 DNU DNU VSS VDD DNU DNU SA SA SA SA SA SA SA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE (LBO\) SA SA SA SA DQc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc VSS VDD VDD VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQd TQFP PINS SYMBOL TYPE DESCRIPTION 37 36 32-35, 44-50, 81, 82, 99, 100 SA0 SA1 SA Input 93 94 95 96 BWa\ BWb\ BWc\ BWd\ Input 87 CKE\ Input 88 R/W\ Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. Pins 83 and 84 are reserved as address bits for the higher-density 8Mb and 16Mb ZBL SRAMs, respectively. SA0 and SA1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle as the address. BWa\ controls DQa pins; BWb\ controls DQb pins; BWc\ controls DQc pins; BWd\ controls DQd pins. Synchronous Clock Enable: This active LOW input permits CLK to propagate throughout the device. When CKE is HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet setup and hold times around the rising edge of CLK. Read/Write: This input determines the cycle type when ADV/LD\ is LOW and is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Full bus-width WRITEs occur if all byte write enables are LOW. AS5SS128K36 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SRAM AS5SS128K36 Austin Semiconductor, Inc. PIN DESCRIPTIONS (continued) TQFP PINS SYMBOL TYPE DESCRIPTION 64 ZZ Input 89 CLK Input Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. Clock: This signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. 98, 92 CE\, CE2\ Input 97 CE2 86 OE\ (G\) ADV/LD\ 85 Synchronous Chip Enable: These active LOW inputs are used to enable the device and are sampled only when a new external address is loaded (ADV/LD\ LOW). CE2\ can be used for memory depth expansion. Input Synchronous Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD\ LOW). This input can be used for memory depth expansion. Input Output Enable: This active LOW, asynchronous inputs enables the data I/O output drivers. G\ is the JEDEC-standard term for OE\. Input Synchronous Address Advance/Load: When HIGH, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When ADV/LD\ is HIGH, R/W\ is ignored. A LOW on ADV/LD\ clocks a new address at the CLK rising edge. Input Mode: This inputs selects the burst sequence. A LOW on this pin selects linear burst. NC or HIGH on this pin selects interleaved burst. Do not alter input state while device is operating. LBO\ is the JEDEC-standard term for MODE. Input/Output SRAM Data I/Os: Byte "a" is DQa pins; Byte "b" is DQb pins; Byte "c" is DQc pins; Byte "d" is DQd pins. Input data must meet setup and hold times around the rising edge CLK. 31 MODE (LBO\) (a) 51, 52, 53, 56-59, 62, 63 (b) 68, 69, 72-75, 78, 79, 80 (c)1, 2, 3, 6-9, 12, 13 (d) 18, 19, 22-25, 28, 29, 30 15, 16, 41, 65, 91 DQa DQb DQc DQd VDD Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range. 5, 10, 14, 17, 21, 26 40, 55, 60, 66, 67, 71 76, 90 4, 11, 20, 27, 54, 61 70, 77 38, 39, 42, 43, 83, 84 64 Vss Ground Ground: GND VDDQ Supply NC ---- Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. No Connect: These pins can be left floating or connected to GND to minimize thermal impedance. 38, 39, 42, 43 DNU ---- 83, 84 NF ---- AS5SS128K36 Rev. 2.0 12/00 Do Not Use: These signals may with be unconnected or wired to GND to minimize thermal impedance. No Function: These pins are internally connected to the die and will have the capacitance of an input pin. It is allowable to leave these pins unconnected or driven by signals. Pins 83 and 84 are reserved for address expansion. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 SRAM AS5SS128K36 Austin Semiconductor, Inc. INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) First Address (external) X...X00 X...X01 X...X10 X...X11 Second Address Third Address Fourth Address (internal) (internal) (internal) X...X01 X...X10 X...X11 X...X00 X...X11 X...X10 X...X11 X...X00 X...X01 X...X10 X...X01 X...X00 LINEAR BURST ADDRESS TABLE (MODE = LOW) First Address (external) X...X00 X...X01 X...X10 X...X11 Second Address Third Address Fourth Address (internal) (internal) (internal) X...X01 X...X10 X...X11 X...X10 X...X11 X...X00 X...X11 X...X00 X...X01 X...X00 X...X01 X...X10 PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS* FUNCTION R/W\ BWa\ BWb\ BWc\ BWd\ READ H X X X X Write Abort/NOP L H H H H 2 L L H H H 2 L H L H H 2 L H H L H 2 L H H H L L L L L L Write Byte a (DQa, DQPa) Write Byte b (DQb, DQPb) Write Byte c (DQc, DQPc) Write Byte d (DQd, DQPd) Write all bytes * NOTE: Using R/W\ and byte write(s), any one or more bytes may be written. AS5SS128K36 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 SRAM AS5SS128K36 Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM 17 SA0, SA1, SA 17 ADDRESS REGISTER MODE 15 CE K WRITE ADDRESS REGISTER ADV/LD\ BWa\ BWb\ BWc\ BWd\ R/W\ OE\ CE\ CE2 CE2\ SA1' Q1 SA0' Q0 SA1 D1 SA0 D0 ADV/LD\ K CLK CKE\ 17 BURST LOGIC 17 17 128K X 9 X 4 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S D A T A S T E E R I N G O U T P U T DQs B U F F E R S E INPUT E REGISTER READ LOGIC NOTE: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. AS5SS128K36 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 SRAM AS5SS128K36 Austin Semiconductor, Inc. STATE DIAGRAM FOR ZBL SRAM DS BURST DS DS DESELECT DS DS RE AD TE RI W READ WRITE BEGIN READ BEGIN WRITE WRITE READ BURST BURST BURST KEY: WRITE AD RE W RI TE READ BURST READ BURST WRITE BURST COMMAND ACTION DS DESELECT READ New READ WRITE New WRITE BURST BURST READ, BURST WRITE or CONTINUE DESELECT NOTE: 1. A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE\ HIGH only blocks the clock (CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock (CLK). AS5SS128K36 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 SRAM AS5SS128K36 Austin Semiconductor, Inc. TRUTH TABLE (5-10) ADDRESS CE\ CE2\ CE2 USED DESELECT CYCLE None H X X DESELECT CYCLE None X H X DESELECT CYCLE None X X L CONTINUE DESELECT CYCLE None X X X READ CYCLE External L L H (Begin Burst) READ CYCLE Next X X X (Continue Burst) NOP/DUMMY READ External L L H (Begin Burst) DUMMY READ Next X X X (Continue Burst) WRITE CYCLE External L L H (Begin Burst) WRITE CYCLE Next X X X (Continue Burst) NOP/WRITE ABORT None L L H (Begin Burst) WRITE ABORT Next X X X (Continue Burst) IGNORE CLOCK EDGE Current X X X (Stall) SNOOZE MODE None X X X OPERATION ZZ ADV/LD\ R/W\ BWx OE\ CKE\ CLK DQ NOTES 1 L L L L L L L H X X X X X X X X X X X X L L L L L L L L H H H H High-Z High-Z High-Z High-Z L L H X L L L H Q L H X X L L L H Q 1, 11 L L H X H L L H High-Z 2 L H X X H L L H High-Z 1, 2, 11 L L L L X L L H D 3 L H X L X L L H D 1, 3, 11 L L L H X L L H High-Z 2, 3 L H X H X L L H High-Z 1, 2, 3, 11 L X X X X H L H --- 4 H X X X X X X High-Z NOTE: 1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT cycle is first executed. 2. DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a WRITE command is given, but no operation is performed. 3. OE\ may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the output drivers during a WRITE cycle. OE\ may be used when the bus turn-on and turn-off times do not meet an applications requirements. 4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE CLOCK EDGE cycle. 5. X means “Don’t Care.” H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa\, BWb\, BWc\, BWd\) are HIGH. BWx = L means all byte write signals are LOW. 6. BWa\ enables WRITES to Byte “a” (DQa pins); BWb\ enables WRITES to Byte “b” (DQb pins); BWc\ enables WRITES to Byte “c” (DQc pins); BWd\ enables WRITES to Byte “d” (DQd pins). 7. All inputs except OE\ and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 8. Wait states are inserted by setting CKE\ HIGH. 9. This device contains circuitry that will ensure that the outputs will be in the High-Z during power-up. 10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST cycle. 11. The address counter is incremented for all CONTINUE BURST cycles. AS5SS128K36 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 SRAM AS5SS128K36 Austin Semiconductor, Inc. *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Junction Temperature depends upon package type, cycle time, loading, ambient temperture and airflow. ABSOLUTE MAXIMUM RATINGS* Voltage on VDD Supply Relative to VSS.................-0.5V to +4.6V Voltage on VDDQ Supply Relative to VSS.................-0.5V to VDD VIN.................................................................. -0.5V to VDDQ +0.5V Storage Temperature (Plastics) ..........................-55°C to +150°C Short Circuit Output Current ........................…..................100mA Max. Junction Temperature*.............................................+150°C DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (-55oC < TA < +125oC; VDD, VDDQ = +3.3V +0.165V unless otherwise noted) DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES VIH 2.0 VDD + 0.3 V 1, 2 VIH 2.0 VDD + 0.3 V 1, 2 VIL -0.3 0.8 V 1, 2 0V < VIN < VDD ILI -1.0 1.0 µA 3 Output(s) Disabled, 0V < VIN < VDD ILO -1.0 1.0 µA Output High Voltage IOH = -4.0mA VOH 2.4 --- V 1, 4 Output Low Voltage IOL = 8.0mA VOL --- 0.4 V 1, 4 VDD 3.135 3.465 V 1 VDDQ 3.135 VDD V 1, 5 Input High (Logic 1) Voltage Input High (Logic 1) Voltage DQ Pins Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Supply Voltage Isolated Output Buffer Supply CAPACITANCE DESCRIPTION CONDITIONS SYMBOL TYP MAX UNITS NOTES CI 3 4 pF 6 TA = 25oC; f = 1 MHz CO 4 5 pF 6 VDD = 3.3V CA 3 3.5 pF 6 CCK 3 3.5 pF 6 Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance NOTE: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH < +4.6V for t < tKHKH /2 for I < 20mA. Undershoot: VIL < -0.7V for t < tKHKH /2 for I < 20mA. Power-up: VIH < +3.465V and VDD < 3.135V for t < 200ms. 3. MODE pin has an internal pull-up, and input leakage = + 10µA. 4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O curvers are available upon request. 5. VDDQ should never exceed VDD. VDD and VDDQ should be externally wired together to the same power supply. 6. This parameter is sampled. AS5SS128K36 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 SRAM AS5SS128K36 Austin Semiconductor, Inc. IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (-55oC < TA < +125oC; VDD, VDDQ = +3.3V +0.165V unless otherwise noted) DESCRIPTION CONDITIONS SYM MAX -11 -12 UNITS NOTES Device selected; All inputs < VIL Power Supply Current: Operating or > VIH; Cycle time > tKC (MIN) IDD 275 250 mA 1, 2 IDD1 22 20 mA 1, 2 ISB2 10 10 mA 2 ISB3 25 25 mA 2 ISB4 65 60 mA 2 ISB2Z 10 10 mA 2 VDD = MAX; Outputs open Device selected; VDD = MAX; Power Supply Current: Idle CKE\ > VIH; All inputs < VSS + 0.2 or > VDD -0.2; Cycle time > tKC (MIN) Device selected; VDD = MAX; CMOS Standby All inputs < VSS + 0.2 or > VDD -0.2; All inputs static; CLK frequency = 0 Device selected; VDD = MAX; TTL Standby Clock Running All inputs < VIL or > VIH; All inputs static; CLK frequency = 0 Device selected; VDD = MAX; ADV/LD\ > VIH; All inputs < VSS + 0.2 or > VDD - 0.2; Cycle time > tKC (MIN) Snooze Mode ZZ > VIH THERMAL RESISTANCE DESCRIPTION Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Top of Case) CONDITIONS SYM TYP UNITS Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 θJA 46 o 3 θJC 2.8 o 3 C/W C/W NOTES NOTE: 1. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading. 2. “Device deselected” means device is in a deselected cycle as defined in the truth table. “Device selected” means device is active (not in deselected mode). 3. This parameter is sampled. AS5SS128K36 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 SRAM AS5SS128K36 Austin Semiconductor, Inc. AC ELECTRICAL CHARACTERISTICS 6, 8, 9 (-55oC < TA < +125oC; VDD, VDDQ = +3.3V +0.165V) -11 SYM MIN MAX DESCRIPTION -12 MIN MAX UNITS NOTES CLOCK Clock cycle time tKHKH Clock frequency tKF Clock HIGH time tKHKL 3.0 3.0 ns 1 Clock LOW time tKLKH 3.0 3.0 ns 1 11 12 90 ns 83 MHz OUTPUT TIMES Clock to output valid tKHQV Clock to output invalid tKHQX 3.0 3.0 ns 2 Clock to output in Low-Z tKHQX1 3.0 3.0 ns 2, 3, 4, 5 Clock to output in High-Z tKHQZ 5.0 5.0 ns 2, 3, 4, 5 OE\ to output valid tGLQV 5.0 5.0 ns 6 OE\ to output in Low-Z tGLQX ns 2, 3, 4, 5 OE\ to output in High-Z tGHQZ ns 2, 3, 4, 5 8.5 0 9.0 0 5.0 5.0 ns SETUP TIMES Address tAVKH 2.2 2.5 ns 7 Clock enable (CKE\) tEVKH 2.2 2.5 ns 7 Control signals tCVKH 2.2 2.5 ns 7 Data-in tDVKH 2.2 2.5 ns 7 Address tKHAX 0.5 0.5 ns 7 Clock enable (CKE\) tKHEX 0.5 0.5 ns 7 Control signals tKHCX 0.5 0.5 ns 7 Data-in tKHDX 0.5 0.5 ns 7 HOLD TIMES NOTE: 1. Measured as HIGH above VIH and LOW below VIL. 2. Contact ASI for more information on these parameters. 3. This parameter is sampled. 4. This parameter is measured with the output loading shown in Figure 2. 5. Transistion is measured +200mV from steady state voltage. 6. OE\ can be considerted a “Don’t Care” during WRITEs; however, controlling OE\ can help fine-tune a system for ZBL timing. 7. This is a synchrnous device. All addresses must meet the specified setup and hold times for all rising edgges o CLK when they are being registered into the device. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when ADV/LD\ is LOW to remain enabled. 8. Test conditions as specified with the output loading shown in Figure 1, unless otherwise noted. 9. A WRITE cycle is defined by R/W\ LOW having been registered into the device at ADV/LD\ LOW. A READ cycle is defined by R/W\ HIGH with ADV/LD\ LOW. Both cases must meet setup and hold times. AS5SS128K36 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 SRAM AS5SS128K36 Austin Semiconductor, Inc. AC TEST CONDITIONS Input pulse levels Vss to 3.3V Input slew rate Input timing reference levels Output reference levels Output load 1 ns 1.5V 1.5V See Figures 1 and 2 OUTPUT LOADS 3.3v 317Ω Q Z0=50Ω Q 50Ω 351Ω 5 pF VT = 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT Fig. 2 OUTPUT LOAD EQUIVALENT LOAD DERATING CURVES The ASI 128K x 36 ZBL SRAM timing is dependent upon the capacitive loading on the outputs. Consult the factory for copies of I/O current versus voltage curves. AS5SS128K36 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 SRAM AS5SS128K36 Austin Semiconductor, Inc. SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time the ZZ pin is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become disabled and all outputs go to High-Z. The ZZ pin is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic HIGH, ISB2Z is guaranteed after the time tZZI is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete sucessfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during tRZZ, only a DESELECT or READ cycle should be given. SNOOZE MODE ELECTRICAL CHARACTERISTICS DESCRIPTION CONDITIONS SYM ZZ > VIH ISB2Z Current during SNOOZE MODE MIN MAX UNITS NOTES 10 mA ZZ active to input ignored tZZ 0 tKHKH ns 1 ZZ inactive to input sampled tRZZ 0 tKHKH ns 1 ZZ active to snooze current tZZI tKHKH ns 1 ZZ inactive to exit snooze current tRZZI ns 1 0 SNOOZE MODE WAVEFORM CLK ZZ ISUPPLY 1 tZZ 1 tZZI 1 AS5SS128K36 Rev. 2.0 12/00 tRZZ 12 1 IISB2Z 12tRZZI 1 123456 12 12345 12 123456 12123456789012345678901 123456789012345678901 12345 12 123456 12 123456789012345678901 12345 12 DESELECT 123456 12 12345 12 or READ Only 123456 12123456789012345678901 123456789012345678901 12345 12 ALL INPUTS (except ZZ) Outputs 1 12345678901234567890 12345 12 12345678901234567890 12345 12 12345678901234567890 12345 12 12345 12 (Q)12345678901234567890 High-Z 12345 12 12345678901234567890 12345 12 12345678901234567890 12345 12 12345678901234567890 12345 12 12345678901234567890 12345 12 12345678901234567890 12345 12345 12345 12345 12345Don’t Care Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12 SRAM AS5SS128K36 Austin Semiconductor, Inc. READ/WRITE TIMING tKHKH 1 2 3 4 5 6 7 8 9 10 CLK tKHKL tEVKH tKHEX 1234 1234 1234 1234 1234 123 123 1234 tKLKH 123 1234 1234 1234 123 1234 123 123 1234 1234 1234 1234 123 1234 1234 1234 123 123 1234 CLE\ 1234 1234 1234 1234 1234 tCVKH tKHCX 1234 12 123456789 11 1234 12 12345678 12 1234 1234 1234 1234 1234 12 123456789 1234 12 12345678 12 1234 1234 12 1 121234567812 1234 123456789 1234 1234 123 1234 CE\1234 1234 1234 1234 1234 123 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 123 1234 1234 1234 1234 1234 1234 1234 123 1234 ADV/LD\1234 1234 1234 1234567890 1234 1234567890 1234 1234 1234 1234567890 1234 1234567890 1234 1234 1234 1234 1234567890 1234 1234567890 1234 1234 R/W\1234 1234 1234 1234 1234 12 123456789012345678901 12 12 12345678 1234 1234 1234 12 12345678901234567890112 121234567812 12 1 1234 1234 1234 1 12 123456789012345678901 12 121234567812 BWx\ 1234 123 1234567 1 123 12 123 12 1234567 1234 1234 1234 123 1234567 1 123 A3 123 12 123 123 12 12345671123 1123 A5 123 123 A6 123 123 A7 1234567 1234567 1 123 123 A4 12 12 123 1123 123 123 ADDRESS1234 A1 1234A2 123 tKHQV tKHQZ tKHQX tKHQX1 tGLQV 1234 12 12 123 1234D(A1) 123 123 D(A2)123 123 D(A2+1) 123 123 12 12 123 123 1234 123 123 123 Q(A3) 12 12 Q(A4) 12 12 Q(A4+1)123 123 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234567890 1234567890 1234567890 123456789 123456789 123456789 123 11234567 123 11234567 123 11234567 tAVKH tKHAX DQ tDVKH t tGHQZ KHDX tGLQX D(A5) 12 123 12 123123 123 12 12 Q(A6) 123 123123 123 D(A7) tKHQX OE\ COMMAND WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4 +1) WRITE D(A5) WRITE D(A7) READ Q(A6) DESELECT 1234 123 1234 123 1234Undefined 123Don’t Care 1234 READ/WRITE TIMING PARAMETERS -11 SYMBOL tKHKH MIN -11 -12 MAX 11 MIN SYMBOL MAX 12 MIN -12 MAX MIN 5.0 tGHQZ 5.0 tAVKH 2.2 tKHKL 3.0 3.0 tEVKH 2.2 2.5 tKLKH 3.0 3.0 tCVKH 2.2 2.5 tDVKH 2.2 2.5 tKHAX 0.5 0.5 90 tKF 8.5 tKHQV tKHQX 3.0 tKHQX1 3.0 9.0 3.0 5.0 tGLQV 0 2.5 tKHEX 0.5 0.5 5.0 tKHCX 0.5 0.5 5.0 tGLDX 0.5 0.5 3.0 5.0 tKHQZ tGLQX 83 MAX 0 NOTE: 1. For this waveform, ZZ is tied LOW. 2. Burst sequence order is determined by MODE (0=linear, 1=interleaved). BURST operations are optional. 3. CE\ represents three signals. When CE\ = 0, it represents CE\ = 0, CE2\ = 0, CE2 = 1. 4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register. AS5SS128K36 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13 SRAM AS5SS128K36 Austin Semiconductor, Inc. NOP, STALL AND DESELECT CYCLES 1 2 3 4 5 6 7 8 9 10 CLK 1234 1234 1234 CKE\1234 1234 1234 CE\1234 1234 1234 ADV/LD\1234 1234 1234 1234 R/W\1234 1234 1234 1234 BWx\ ADDRESS 1234 1234 123 1234 123 1234 1234 123 1234 123 1234 1234 1234 1234 1234 1234 123 1234 123 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 123 1234 123 1234 12 12345678 12 1234 12 12345678 123 1234 1234 12 12345678 12 1234 12 12345678 123 1234 112 123456789 1234 12 12 1234 123 1234 12345678 11234567812 12 123456789 1234 1234 123 1234 1234 12 12345678 12 1234 1 123456789 12 12 123 1234 1234 1234 12 12345678 12 1234 112 123456789 12 12 123 1234 1234 12 12345678 12 1 123456789 12 1234 1234 1234 123 1234 1234 12 12345678 12 1234 123456789 1 12 1234 1234567890123456 1234 12 12345678 12 1234 123456789 1 12 1234 1234567890123456 12345678 1234 12 12 1234 112345678912 1234 1234567890123456 12 1234567890123456789012 12 1234567890 12345678901234567890123 12 1234567890123456789012 12 1234567890 12345678901234567890123 1234567890123456789012 12 12 123 1234567890 12345678901234567890123 123 112345678901234 123 123 112345678901234 123 123 11234567890123412 123 12 123 112345678901234 11234567890123412 123 A5 123 112345678901234 A1 A2 A3 123 A4 123 tKHQZ 1234 123 123D(A1) 1234 1234 1234 123 DQ 123 123 123 123 Q(A2) Q(A3) 123 123 123 123 12 12 12 12 D(A4) 123 12 123 12 123 123 Q(A5) 12 12 tKHQX COMMAND WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) STALL NOP READ Q(A5) DESELECT CONTINUE DESELECT 1234 123 1234 123 1234Undefined 123 Don’t Care 1234 NOP, STALL AND DESELECT TIMING PARAMETERS -11 SYMBOL MIN tKHQX 3.0 tKHQZ -12 MAX MIN MAX 3.0 5.0 5.0 NOTE: 1. 2. 3. 4. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE\ being used to create a “pause”. A WRITE is not performed during this cycle. For this waveform, ZZ and OE\ are tied LOW. CE\ represents three signals. When CE\ = 0, it represents CE\ = 0, CE2\ = 0, CE2 = 1. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register. AS5SS128K36 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 14 SRAM AS5SS128K36 Austin Semiconductor, Inc. ASI Case # 1001 (Package Designator DQ) 16.00 +0.20/-0.05 14.00 + 0.10 22.10 +0.10/-0.15 20.10 + 0.10 See Detail A 1.40 + 0.05 0.10+0.10/-0.05 1.50 + 0.10 0.15 +0.03/-0.02 1.00 TYP 0.65 Basic 0.32+0.06/-0.10 0.60 + 0.15 Detail A NOTE: All dimensions in Millimeters. AS5SS128K36 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 15 SRAM AS5SS128K36 Austin Semiconductor, Inc. ORDERING INFORMATION EXAMPLE: AS5SS128K36DQ-11/IT Device Number AS5SS128K36 AS5SS128K36 Package Speed ns Process Type DQ -11 /* DQ -12 /* *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range AS5SS128K36 Rev. 2.0 12/00 -40oC to +85oC -55oC to +125oC Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 16