AUSTIN MT4C1004J

MT4C1004J
MT5C1005 883C
4 MEG
256K xx 14 DRAM
SRAM
AUSTIN SEMICONDUCTOR, INC.
DRAM
4 MEG x 1 DRAM
FAST PAGE MODE
AVAILABLE AS MILITARY
SPECIFICATONS
PIN ASSIGNMENT (Top View)
• SMD 5962-90622
• MIL-STD-883
FEATURES
• Industry standard x1 pinout, timing, functions and
packages
• High-performance, CMOS silicon-gate process
• Single +5V ±10% power supply
• Low-power, 2.5mW standby; 300mW active, typical
• All inputs, outputs and clocks are fully TTL and CMOS
compatible
• 1,024-cycle refresh distributed across 16ms
• Refresh modes: /R?A/S-ONLY, /C/A/S-BEFORE-/R/?A/S (CBR),
and HIDDEN
• FAST PAGE MODE access cycle
• CBR with ?W/E a HIGH (JEDEC test mode capable via
WCBR)
OPTIONS
20-Pin ZIP
18-Pin DIP
• Packages
Ceramic DIP (300 mil)
Ceramic DIP (400 mil)
Ceramic LCC
Ceramic SOJ
Ceramic ZIP
Ceramic Gull Wing
- 7
- 8
-10
-12
CN
C
ECN
ECJ
CZ
ECG
1
18
Vss
A9
1
2
17
Q
Q
3
RAS
3
16
CAS
D
5
*A10
4
15
A9
RAS
7
A0
5
14
A8
NC
9
A1
6
13
A7
A0
11
A2
7
12
A6
A2
13
A3
8
11
A5
Vcc
15
Vcc
9
10
A4
A5
17
A7
19
2
CAS
4
Vss
6
WE
8
A10*
10
NC
12
A1
14
A3
16
A4
18
A6
20
A8
20-Pin SOJ
20-Pin LCC
20-Pin Gull Wing
MARKING
• Timing
70ns access
80ns access
100ns access
120ns access
D
WE
No. 101
No. 102
No. 202
No. 504
No. 400
No. 600
1
D
WE
RAS
NC
*A10
2
3
4
5
26
25
24
23
22
Vss
Q
CAS
NC
A9
A0
A1
A2
A3
Vcc
9
10
11
12
13
18
17
16
15
14
A8
A7
A6
A5
A4
*Address not used for /R/A/S-ONLY REFRESH
GENERAL DESCRIPTION
falling edge of ?W/E or /C/A/S, whichever occurs last. If ?W/E
goes LOW prior to /C/?A/S going LOW, the output pin remains
open (High-Z) until the next /C/A/S cycle. If ?W/E goes LOW
after data reaches the output pin, Q is activated and retains
the selected cell data as long as /C/A/S remains LOW (regardless of ?W/E or /R/A/S). This LATE-?W/E pulse results in a
READ-WRITE cycle. FAST PAGE MODE operations allow
faster data operations (READ, WRITE or READ-MODIFYWRITE) within a row-address (A0 -A10) defined page
The MT4C1004J is a randomly accessed solid-state
memory containing 4,194,304 bits organized in a x1 configuration. During READ or WRITE cycles, each bit is uniquely
addressed through the 22 address bits which are entered 11
bits (A0 -A10) at a time. /R/A/S is used to latch the first 11 bits
and /C/A/S the latter 11 bits. A READ or WRITE cycle is
selected with the ?W/E input. A logic HIGH on ?W/E dictates
READ mode while a logic LOW on ?W/E dictates WRITE
mode. During a WRITE cycle, data-in (D) is latched by the
MT4C1004J 883C
REV. 11/97
DS000021
2-23
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
MT4C1004J
MT5C1005 883C
4 MEG
256K xx 14 DRAM
SRAM
AUSTIN SEMICONDUCTOR, INC.
the chip is preconditioned for the next cycle during the /R/A/
S HIGH time. Memory cell data is retained in its correct state
by maintaining power and executing any /R?A/S cycle (READ,
WRITE, /R?A/S-ONLY, /C/A/S-BEFORE-/R/A/S, or HIDDEN REFRESH) so that all 1,024 combinations of /R?A/S addresses
(A0 -A9) are executed at least every 16ms, regardless of
sequence. The /C?A/S - BEFORE-/R?A/S cycle will invoke the
refresh counter for automatic /R/?A/S addressing.
boundary. The FAST PAGE MODE cycle is always initiated with a row address strobed-in by /R/A/S followed by a
column address strobed-in by C
/ /A/S. /C/A/S may be toggled-in
by holding /R/A/S LOW and strobing-in different column
addresses, thus executing faster memory cycles. Returning
/R/A/S HIGH terminates the FAST PAGE MODE operation.
Returning /R/A/S and /C/A/S HIGH terminates a memory cycle
and decreases chip current to a reduced standby level. Also,
FUNCTIONAL BLOCK DIAGRAM
FAST PAGE MODE
WE
CAS
*EARLY-WRITE
DETECTION CIRCUIT
NO. 2 CLOCK
GENERATOR
RAS
COLUMN
ADDRESS
BUFFER(11)
D
DATA OUT
BUFFER
Q
COLUMN
DECODER
11
4096
REFRESH
CONTROLLER
SENSE AMPLIFIERS
I/O GATING
4096
REFRESH
COUNTER
10
11
ROW
ADDRESS
BUFFERS (11)
1
10
NO. 1 CLOCK
GENERATOR
ROW
DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
11
DATA IN
BUFFER
1024
MEMORY
ARRAY
Vcc
Vss
*NOTE: WE LOW prior to CAS LOW, EW detection circuit output is a HIGH (EARLY-WRITE)
CAS LOW prior to WE LOW, EW detection circuit output is a LOW (LATE-WRITE)
MT4C1004J 883C
REV. 11/97
DS000021
2-24
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
MT4C1004J
MT5C1005 883C
4 MEG
256K xx 14 DRAM
SRAM
AUSTIN SEMICONDUCTOR, INC.
TRUTH TABLE
ADDRESSES
DATA
?R/A/S
?C/A/S
?W/E
tR
tC
D (Data In)
Q (Data Out)
Standby
H
H>X
X
X
X
Don’t Care
High-Z
READ
L
L
H
ROW
COL
Don’t Care
Data Out
EARLY-WRITE
L
L
L
ROW
COL
Data In
High-Z
READ-WRITE
L
L
H>L
ROW
COL
Data In
Data Out
FUNCTION
FAST-PAGE-MODE 1st Cycle
L
H>L
H
ROW
COL
Don’t Care
Data Out
READ
L
H>L
H
n/a
COL
Don’t Care
Data Out
FAST-PAGE-MODE 1st Cycle
L
H>L
L
ROW
COL
Data In
High-Z
EARLY-WRITE
L
H>L
L
n/a
COL
Data In
High-Z
FAST-PAGE-MODE 1st Cycle
L
H>L
H>L
ROW
COL
Data In
Data Out
READ-WRITE
L
H>L
H>L
n/a
COL
Data In
Data Out
L
H
X
ROW
n/a
Don’t Care
High-Z
H
ROW
COL
Don’t Care
Data Out
2nd Cycle
2nd Cycle
2nd Cycle
/R/A/S-ONLY REFRESH
HIDDEN
READ
L>H>L
L
REFRESH
WRITE
L>H>L
L
L
ROW
COL
Data In
High-Z
H>L
L
H
X
X
Don’t Care
High-Z
/C/A/S-BEFORE-/R/A/S REFRESH
MT4C1004J 883C
REV. 11/97
DS000021
2-25
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
MT4C1004J
MT5C1005 883C
4 MEG
256K xx 14 DRAM
SRAM
AUSTIN SEMICONDUCTOR, INC.
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin Relative to VSS ............... -1.0V to +7.0V
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... 50mA
Lead Temperature (Soldering 5 Seconds)................. 270°C
Storage Temperature ................................... -65°C to +150°C
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (-55°C ≤ TA ≤ 125°C; VCC = 5V ± 10%)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
Supply Voltage
VCC
4.5
5.5
V
Input High (Logic 1) Voltage, All Inputs
VIH
2.4
VCC+.5
V
Input Low (Logic 0) Voltage, All Inputs
VIL
-.5
0.8
V
II
-5
5
µA
OUTPUT LEAKAGE CURRENT (Q is Disabled, 0V ≤ VOUT ≤ 5.5V) VCC=5.5V
IOZ
-5
5
µA
OUTPUT LEVELS
Output High Voltage (IOUT = -5mA)
Output Low Voltage (IOUT = 4.2mA)
VOH
2.4
INPUT LEAKAGE CURRENT
Any Input 0V ≤ VIN ≤ 5.5V
(All other pins not under test = 0V)
VCC=5.5V
NOTES
V
VOL
0.4
V
MAX
PARAMETER/CONDITION
SYMBOL
-7
-8
-10
-12
STANDBY CURRENT (TTL)
(/R/A/S = /C/A/S = VIH)
ICC1
4
4
4
4
mA
STANDBY CURRENT (CMOS)
(/R/A/S = /C/A/S = VCC -0.2V; all other inputs = VCC -0.2V)
ICC2
2
2
2
2
mA
OPERATING CURRENT: Random READ/WRITE
Average Power-Supply Current
(/R/A/S, /C/A/S, Address Cycling: tRC = tRC (MIN))
ICC3
85
75
65
65
mA
3, 4
OPERATING CURRENT: FAST PAGE MODE
Average Power-Supply Current
(/R/A/S = VIL, /C/A/S, Address Cycling: tPC = tPC (MIN))
ICC4
60
50
45
40
mA
3, 4
REFRESH CURRENT: /R/A/S-ONLY
Average Power-Supply Current
(/R/A/S Cycling, /C/A/S = VIH: tRC = tRC (MIN))
ICC5
85
75
65
65
mA
3
REFRESH CURRENT: /C/A/S-BEFORE-/R/A/S
Average Power-Supply Current
(/R/A/S, /C/A/S, Address Cycling: tRC = tRC (MIN))
ICC6
85
75
65
65
mA
3, 5
MT4C1004J 883C
REV. 11/97
DS000021
2-26
UNITS NOTES
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
MT4C1004J
MT5C1005 883C
4 MEG
256K xx 14 DRAM
SRAM
AUSTIN SEMICONDUCTOR, INC.
CAPACITANCE
PARAMETER
MAX
UNITS
NOTES
Input Capacitance: A0-A10, D
SYMBOL
CI1
MIN
7
pF
2
Input Capacitance: /R/A/S, /C/A/S, ?W/E
CI2
7
pF
2
Output Capacitance: Q
CO
8
pF
2
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C ≤ TC ≤ 125; VCC = 5V ± 10%)
AC CHARACTERISTICS
PARAMETER
Random READ or WRITE cycle time
READ-WRITE cycle time
FAST- PAGE-MODE READ
or WRITE cycle time
FAST- PAGE-MODE READ-WRITE
cycle time
-7
SYM
tRC
tRWC
tPC
MIN
130
155
40
tPRWC
65
tRAC
Access time from /R/A/S
tCAC
Access time from /C/A/S
tAA
Access time from column address
tCPA
Access time from /C/A/S precharge
tRAS
/R/A/S pulse width
tRASP
/R/A/S pulse width (FAST PAGE MODE)
tRSH
/R/A/S hold time
tRP
/R/A/S precharge time
tCAS
/C/A/S pulse width
tCSH
/C/A/S hold time
tCPN
/C/A/S precharge time
/C/A/S precharge time (FAST PAGE MODE) tCP
tRCD
/R/A/S to /C/A/S delay time
tCRP
/C/A/S to /R/A/S precharge time
tASR
Row address setup time
tRAH
Row address hold time
tRAD
/R/A/S to column
address delay time
Column address setup time
Column address hold time
Column address hold time
(referenced to /R/A/S)
Column address to
/R/A/S lead time
Read command setup time
Read command hold time
(referenced to /C/A/S)
Read command hold time
(referenced to /R/A/S)
/C/A/S to output in Low-Z
Output buffer turn-off delay
?W/E command setup time
MT4C1004J 883C
REV. 11/97
DS000021
tASC
70
70
20
50
20
70
10
10
20
5
0
10
15
-8
MAX
MIN
150
175
45
-10
MAX
70
70
20
35
35
10,000
100,000
10,000
50
35
80
80
20
60
20
80
10
10
20
5
0
10
15
MIN
180
210
55
-12
MAX
85
80
20
40
40
10,000
100,000
10,000
60
40
100
100
25
70
25
100
12
12
25
5
0
15
20
MIN
220
255
70
MAX
140
90
25
45
45
10,000
100,000
10,000
75
50
120
120
30
90
30
120
15
15
25
10
0
15
20
UNITS NOTES
ns
ns
ns
ns
120
30
60
60
100,000
100,000
10,000
90
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
15
16
17
18
tAR
0
15
50
0
20
60
0
25
70
0
25
85
ns
ns
ns
tRAL
35
40
50
60
ns
tRCS
tRCH
0
0
0
0
0
0
0
0
ns
ns
19
tRRH
0
0
0
0
ns
19
tCLZ
0
0
0
ns
ns
ns
20
21
tCAH
tOFF
tWCS
20
2-27
0
0
0
20
0
0
0
20
0
0
0
20
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
MT4C1004J
MT5C1005 883C
4 MEG
256K xx 14 DRAM
SRAM
AUSTIN SEMICONDUCTOR, INC.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C ≤ TC ≤ 125; VCC = 5V ± 10%)
AC CHARACTERISTICS
PARAMETER
Write command hold time
Write command hold time
(referenced to /R/A/S)
Write command pulse width
Write command to /R/A/S lead time
Write command to /C/A/S lead time
Data-in setup time
Data-in hold time
Data-in hold time
(referenced to /R/A/S)
-7
-8
tWP
15
20
20
0
12
50
15
20
20
0
15
60
20
25
25
0
18
70
25
30
30
0
25
90
ns
ns
ns
ns
ns
ns
70
35
80
40
100
50
120
60
ns
ns
21
21
21
tCWL
tDS
tDH
tDHR
MIN
15
60
MAX
MIN
20
70
-12
MIN
15
50
tRWL
MAX
-10
SYM
tWCH
tWCR
MAX
MIN
25
85
MAX
UNITS
ns
ns
NOTES
22
22
/R/A/S to ?W/E delay time
Column address
to ?W/E delay time
tRWD
/C/A/S to ?W/E delay time
Transition time (rise or fall)
Refresh period (1,024 cycles)
/R/A/S to /C/A/S precharge time
/C/A/S setup time
(/C/A/S-BEFORE-/R/A/S REFRESH)
tCWD
tCSR
0
10
0
10
0
10
0
10
ns
ns
ms
ns
ns
/C/A/S hold time
(/C/A/S-BEFORE-/R/A/S REFRESH)
tCHR
10
15
20
25
ns
5
?/W/E hold time
(/C/A/S-BEFORE-/R/A/S REFRESH)
tWRH
10
10
10
10
ns
24, 25
?/W/E setup time
(/C/A/S-BEFORE-/R/A/S REFRESH)
tWRP
10
10
10
10
ns
24, 25
?/W/E hold time
(WCBR test cycle)
tWTH
10
10
10
10
ns
24, 25
?/W/E setup time
(WCBR test cycle)
tWTS
10
10
10
10
ns
24, 25
MT4C1004J 883C
REV. 11/97
DS000021
tAWD
tT
20
3
tREF
tRPC
50
16
20
3
2-28
50
16
25
3
50
16
30
3
50
16
5
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J
MT5C1005 883C
4 MEG
256K xx 14 DRAM
SRAM
NOTES
cycle and clear the data-out buffer, /C/A/S must be
pulsed HIGH for tCPN.
17. Operation within the tRCD (MAX) limit ensures that
tRAC (MAX) can be met. tRCD (MAX) is specified as
a reference point only; if tRCD is greater than the
specified tRCD (MAX) limit, then access time is
controlled exclusively by tCAC.
18. Operation within the tRAD (MAX) limit ensures that
tRCD (MAX) can be met. tRAD (MAX) is specified as
a reference point only; if tRAD is greater than the
specified tRAD (MAX) limit, then access time is
controlled exclusively by tAA.
19. Either tRCH or tRRH must be satisfied for a READ
cycle.
20. tOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. tWCS, tRWD, tAWD and tCWD are restrictive
operating parameters in LATE WRITE, READ-WRITE
and READ-MODIFY-WRITE cycles only. If tWCS ≥
tWCS (MIN), the cycle is an EARLY-WRITE cycle and
the data output will remain an open circuit throughout the entire cycle. If tRWD ≥ tRWD (MIN), tAWD ≥
tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a
READ-WRITE and the data output will contain data
read from the selected cell. If neither of the above
conditions are met, the cycle is a LATE-WRITE and
the state of Q is indeterminate (at access time and
until /C/A/S goes back to VIH).
22. These parameters are referenced to /C/A/S leading edge
in EARLY-WRITE cycles and ?W/E leading edge in
LATE-WRITE or READ-WRITE cycles.
23. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case ?W/E = LOW.
24. tWTS and tWTH are set up and hold specifications for
the ?W/E pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of tWRP and tWRH in the
CBR REFRESH cycle.
25. JEDEC test mode only.
1. All voltages referenced to VSS.
2. This parameter is sampled, not 100% tested.
Capacitance is measured with Vcc = 5V, f = 1 MHz at
less than 50mVrms, TA = 25°C ±3°C, Vbias = 2.4V
applied to each input and output individually with
remaining inputs and outputs open.
3. ICC is dependent on cycle rates.
4. ICC is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (-55°C ≤ TA ≤ 125°C) is assured.
7. An initial pause of 100µs is required after power-up
followed by eight /R?A/S refresh cycles (/R/A/S-ONLY or
CBR with ?/W/E HIGH) before proper device operation
is assured. The eight /R/A/S cycle wake-up should be
repeated any time the 16ms refresh requirement is
exceeded.
8. AC characteristics assume tT = 5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If /C/A/S = VIH, data output is High-Z.
12. If /C/A/S = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to 2 TTL gates and
100pF.
14. Assumes that tRCD < tRCD (MAX). If tRCD is greater
than the maximum recommended value shown in this
table, tRAC will increase by the amount that tRCD
exceeds the value shown.
15. Assumes that tRCD ≥ tRCD (MAX).
16. If /C/A/S is LOW at the falling edge of /R/A/S, Q will be
maintained from the previous cycle. To initiate a new
MT4C1004J 883C
REV. 11/97
DS000021
2-29
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
MT4C1004J
MT5C1005 883C
4 MEG
256K xx 14 DRAM
SRAM
AUSTIN SEMICONDUCTOR, INC.
READ CYCLE
tRC
tRP
tRAS
RAS
V IH
V IL
tCSH
tRRH
tRSH
,
,
,
,
,
,, ,, , , ,,,,, ,
,, ,
, ,, ,
tRCD
tCRP
CAS
tCAS
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAL
tRAH
tASC
ROW
tCAH
ROW
COLUMN
tRCH
tRCS
WE
V IH
V IL
tAA
,,
tRAC
tCAC
tOFF
tCLZ
Q
V OH
V OL
OPEN
VALID DATA
OPEN
EARLY-WRITE CYCLE
tRC
tRAS
RAS
tRP
V IH
V IL
tCSH
tRSH
,
,
,
, ,,, ,,,,,,
,
,
,
,
,
,
,
,
,
,, , ,, , ,,,,,,,
,,,,,, ,,, ,, ,,,
,
,
tCRP
CAS
tRCD
tCAS
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAH
tRAL
tASC
ROW
tCAH
ROW
COLUMN
tCWL
tRWL
tWCR
tWCS
tWCH
tWP
WE
V IH
V IL
tDHR
tDH
tDS
D
V IH
V IL
Q
V OH
V OL
VALID DATA
OPEN
DON’T CARE
UNDEFINED
MT4C1004J 883C
REV. 11/97
DS000021
2-30
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
MT4C1004J
MT5C1005 883C
4 MEG
256K xx 14 DRAM
SRAM
AUSTIN SEMICONDUCTOR, INC.
READ-WRITE CYCLE
(LATE-WRITE and READ-MODIFY-WRITE CYCLES)
tRWC
tRAS
tRP
V IH
V IL
RAS
tCSH
tRSH
tRCD
tCRP
tCAS
,,, ,,, ,,,,,,,,
, ,,,, ,,,, , , ,,,, ,,,
,, ,, ,,,, ,, ,,,
V IH
V IL
CAS
tAR
tRAD
tRAH
tASR
V IH
V IL
ADDR
tRAL
tASC
ROW
tCAH
COLUMN
ROW
tRWD
tCWL
tRCS
tCWD
tRWL
tAWD
WE
V IH
V IL
D
V IH
V IL
tWP
tDS
tDH
VALID DATA
,,
,,
tAA
tRAC
tOFF
tCAC
t CLZ
Q
V OH
V OL
OPEN
VALID DATA
OPEN
FAST-PAGE-MODE READ CYCLE
tRASP
RAS
tCSH
tCRP
CAS
tRP
V IH
V IL
tRSH
tPC
tRCD
tCAS
tCP
tCAS
tCP
tCAS
tCPN
,
,
,
,
,
,
,
,, ,,, ,, ,,,, ,,,,,,
,
, ,, , , ,
, , ,,,,
, , ,,,,
,
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAL
tRAH
tASC
ROW
tCAH
COLUMN
tRCS
WE
tASC
tASC
COLUMN
tRCH
tCAH
COLUMN
ROW
tRCS
tRCS
tRRH
tRCH
tRCH
V IH
V IL
tAA
tAA
tRAC
tCPA
tCAC
tOFF
tCLZ
Q
tCAH
V OH
V OL
OPEN
tCAC
tAA
tCPA
tOFF
tCLZ
VALID
DATA
tCAC
tOFF
tCLZ
VALID
DATA
VALID
DATA
OPEN
DON’T CARE
UNDEFINED
MT4C1004J 883C
REV. 11/97
DS000021
2-31
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
MT4C1004J
MT5C1005 883C
4 MEG
256K xx 14 DRAM
SRAM
AUSTIN SEMICONDUCTOR, INC.
FAST-PAGE-MODE EARLY-WRITE CYCLE
tRP
tRASP
RAS
V IH
V IL
tCSH
tPC
,
,, ,, ,,,, ,,,
,
,
,
,
,
,
,
,, , ,, ,,,
,,,, ,,, ,,
tCRP
CAS
tRCD
tCAS
tCP
tCAS
tRSH
tCP
,
,,,
,
,
,
,
,, ,,
,,
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAH
tASC
ROW
tCAH
tASC
COLUMN
tCAH
tWCS
COLUMN
tCWL
tWCH
tWCS
tWCH
tWP
WE
tRAL
tCAH
tASC
COLUMN
tCWL
tWCS
tWCH
tWP
tWP
tWCR
tRWL
tDHR
tDH
D
Q
V IH
V IL
tDS
VALID DATA
tDH
tDS
VALID DATA
V IH
V IL
ROW
tCWL
V IH
V IL
tDS
tCPN
tCAS
V IH
V IL
tDH
VALID DATA
OPEN
FAST-PAGE-MODE READ-WRITE CYCLE
(LATE-WRITE and READ-MODIFY-WRITE CYCLES)
tRASP
RAS
tRP
V IH
V IL
tCSH
* tPC
tRSH
tPRWC
,, ,, ,,, ,, ,,,,
,, ,, , , , ,, ,
,
,
,
,
,
,
,
,,,,, ,, ,, , , ,,,,,,
, , , ,
, , ,,
,,,,
tCRP
CAS
tRCD
tCAS
tCP
tCAS
tCP
tCAS
tCPN
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAH
tRAL
tASC
ROW
tCAH
tASC
COLUMN
tCAH
tASC
COLUMN
tCAH
COLUMN
tRCS
tCWL
tAWD
tWP
tCWL
tAWD
tCWD
WE
V IH
V IL
D
V IH
V IL
ROW
tRWL
tRWD
tCWL
tWP
tAWD
tCWD
tDS
tDH
tDS
VALID DATA
tDH
tDS
VALID DATA
tAA
tWP
tCWD
tDH
VALID DATA
tAA
tAA
tCPA
tCPA
tRAC
tCAC
tOFF
tCLZ
Q
V OH
V OL
OPEN
tCAC
tCLZ
VALID
DATA
tCAC
tOFF
tCLZ
VALID
DATA
VALID
DATA
OPEN
DON’T CARE
*tPC = LATE-WRITE Cycle
tPRWC = FAST READ-MODIFY-WRITE Cycle
MT4C1004J 883C
REV. 11/97
DS000021
tOFF
UNDEFINED
2-32
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
MT4C1004J
MT5C1005 883C
4 MEG
256K xx 14 DRAM
SRAM
AUSTIN SEMICONDUCTOR, INC.
/R/A/S-ONLY REFRESH CYCLE
(ADDR = A0-A9; A10 and ?W/E = DON’T CARE)
tRC
tRAS
RAS
V IH
V IL
CAS
V IH
V IL
ADDR
V IH
V IL
,,
tRP
,
,
,
,
,,,,, ,,
tCRP
tRPC
tASR
tRAH
ROW
V
Q V OH
OL
ROW
OPEN
/C/A/S-BEFORE-//R/A/S REFRESH CYCLE
(A0-A10 = DON’T CARE)
tRP
RAS
tRAS
tRP
tRAS
V IH
V IL
tRPC
,,,,,,,,,,,,,,,,,,
,
,
tCPN
CAS
tCSR
tRPC
tCHR
tCSR
tCHR
V IH
V IL
OPEN
Q
tWRP
WE
tWRH
tWRP
tWRH
V IH
V IL
HIDDEN REFRESH CYCLE 23
(?W/E = HIGH)
(READ)
(REFRESH)
tRAS
RAS
tRAS
V IH
V IL
,
,
,
,
,
,
,,
,
, ,, ,,, , ,,,,,
,
,
,
tCRP
CAS
tRP
tRCD
tRSH
tCHR
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAH
tASC
ROW
tRAL
tCAH
COLUMN
tAA
tRAC
tCAC
tOFF
tCLZ
Q
V OH
V OL
OPEN
VALID DATA
OPEN
,
DON’T CARE
UNDEFINED
MT4C1004J 883C
REV. 11/97
DS000021
2-33
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
MT4C1004J
MT5C1005 883C
4 MEG
256K xx 14 DRAM
SRAM
AUSTIN SEMICONDUCTOR, INC.
4 MEG POWER-UP AND REFRESH
CONSTRAINTS
POWER-UP
The 4 Meg JEDEC test mode constraint may introduce
another problem. The 1 Meg POWER-UP cycle requires a
100µs delay followed by any eight ?R?A/S cycles. The 4 Meg
POWER-UP is more restrictive in that eight ?R?A/S-ONLY or
CBR REFRESH (?W/E held HIGH) cycles must be used. The
restriction is needed since the 4 Meg may power-up in the
JEDEC specified test mode and must exit out of the test
mode. The only way to exit the 4 Meg JEDEC test mode is
with either a ?R?A/S-ONLY or a CBR REFRESH cycle (?W/E
held HIGH).
The EIA/JEDEC 4 Meg DRAM introduces two potential
incompatibilities compared to the previous generation
1 Meg DRAM. The incompatibilities involve refresh and
power-up. Understanding these incompatibilities and providing for them will offer the designer and system user
greater compatibility between the 1 Meg and 4 Meg.
REFRESH
The most commonly used refresh mode of the 1 Meg is
the CBR (?C?A/S-BEFORE-?R?A/S) REFRESH cycle. The CBR for
the 1 Meg specifies the ?W/E pin as a “don’t care.” The 4 Meg,
on the other hand, specifies the CBR REFRESH mode with
the ?W/E pin held at a voltage HIGH level.
A CBR cycle with ?W/E LOW will put the 4 Meg into the
JEDEC specified test mode (WCBR).
tRP
RAS
SUMMARY
1. The 1 Meg CBR REFRESH allows the ?W/E pin to be
“don’t care” while the 4 Meg CBR requires ?W/E to be
HIGH.
2. The eight ?R?A/S wake-up cycles on the 1 Meg may be any
valid ?R?A/S cycle while the 4 Meg may only use ?R?A/SONLY or CBR REFRESH cycles (?W/E held HIGH).
tRAS
tRP
tRAS
V IH
V IL
tRPC
,
,
,, ,, ,, ,,,,,,
,
,
,
,
,
,
,
,
,
,
,
,, ,,,,,,, ,, ,
,
tCPN
CAS
V IH
V IL
Q
V OH
V OL
tCSR
1 MEG
DRAM
tCSR
tCHR
OPEN
tWTS
4 MEG
DRAM
tRPC
tCHR
WCBR TEST MODE: WE
V IH
V IL
CBR REFRESH: WE
V IH
V IL
CBR REFRESH: WE
V IH
V IL
tWRP
tWTH
tWTS
tWRH
tWRP
tWTH
tWRH
DON’T CARE
COMPARISON OF 4 MEG TEST MODE AND WCBR TO 1 MEG CBR
MT4C1004J 883C
REV. 11/97
DS000021
2-34
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J
MT5C1005 883C
4 MEG
256K xx 14 DRAM
SRAM
ELECTRICAL TEST REQUIREMENTS
SUBGROUPS
(per Method 5005, Table I)
MIL-STD-883 TEST REQUIREMENTS
INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS
(Method 5004)
2, 8A, 10
FINAL ELECTRICAL TEST PARAMETERS
(Method 5004)
1*, 2, 3, 7*, 8, 9, 10, 11
GROUP A TEST REQUIREMENTS
(Method 5005)
1, 2, 3, 4**, 7, 8, 9, 10, 11
GROUP C AND D END-POINT ELECTRICAL PARAMETERS
(Method 5005)
1, 2, 3, 7, 8, 9, 10, 11
* PDA applies to subgroups 1 and 7.
** Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input
or output capacitance.
MT4C1004J 883C
REV. 11/97
DS000021
2-35
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C
REV. 11/97
DS000021
2-36
MT4C1004J
MT5C1005 883C
4 MEG
256K xx 14 DRAM
SRAM
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.