HCTL-2017 and HCTL-2021 Quadrature Decoder/Counter Interface ICs Data Sheet Description Features The HCTL-2021/2017 is CMOS ICs that performs the quadrature decoder, counter, and bus interface function. The HCTL-2021/2017 is designed to improve system performance in digital closed loop motion control systems and digital data input systems. It does this by shifting time intensive quadrature decoder functions to a cost effective hardware solution. The HCTL-2021/2017 consists of a quadrature decoder logic, a binary up/down state counter, and an 8-bit bus interface. The use of Schmitt-triggered CMOS inputs and input noise filters allows reliable operation in noisy environments. The HCTL-2021/2017 contains 16-bit counter and provides TLL/CMOS compatible tri-state output buffers. Operation is specified for a temperature range from –40 to +85°C at clock frequencies up to 33MHz. • Interfaces Encoder to Microprocessor The HCTL-2021/2017 provides quadrature decoder output signals and cascade signals for use with many standard computer ICs. • 5V Operation (VDD – VSS) The HCTL-2021/2017 is compliant to RoHS directive and had been declared as a lead free product. • 33 MHz Clock Operation • High Noise Immunity: Schmitt Trigger Inputs and Digital Noise Filter • 16-Bit Binary Up/Down Counter • Latched Outputs • 8-Bit Tristate Interface • 8 or 16-Bit Operating Modes • Quadrature Decoder Output Signals, Up/Down and Count • Cascade Output Signals, Up/Down and Count • Substantially Reduced System Software • TTL/CMOS Compatible I/O • Operating Temperature: -40°C to 85°C • 16-pin and 20-Pin Launch Pad Applications • Interface Quadrature Incremental Encoders to Microprocessors • Interface Digital Potentiometers to Digital Data Input Buses Devices Part Number Description Pinout HCTL-2017 33 MHz clock operation. 16-bit counter. PINOUT A HCTL-2021 33 MHz clock operation. 16-bit counter. Quadrature decoder output signals. Cascade output signals. PINOUT B 1 D0 VDD 16 2 CLK D1 15 3 SEL D2 14 VDD 20 Soldering and Mounting Considerations CLK D1 19 3 SEL D2 18 4 OE D3 17 It is recommended to use manual soldering for HCTL2021/2017 launch pad devices due to the characteristics of the material used in the launch pad design that not allow wave soldering. 1 D0 2 4 OE D3 13 5 U/D CNTdec 16 5 RST D4 12 6 NC CNTcas 15 7 RST D4 14 8 CH B D5 13 9 CH A D6 12 10 VSS D7 11 CH B D5 11 7 CH A D6 10 8 VSS D7 9 6 Direct mounting on printed circuit board (PCB) only is recommended for HCTL-2021/2017 launch pad devices. Mounting gap of 1mm between the base of the launch pad and customer’s printed circuit board (PCB) is required. NOTE: Precaution is required in order to avoid bend or loose pin during product handling. PINOUT B PINOUT A Package Dimensions with Tolerances Length (L) Width (W) Thickness (T) HCTL-2017 22.86 ± 0.5 mm 12.70 ± 0.5 mm 1.67 ± 0.25 mm HCTL-2021 27.94 ± 0.5 mm 12.70 ± 0.5 mm 1.67 ± 0.25 mm (dimension in mm) HCTL-2021 SHOWN 2 PIN DRAWING Operating Characteristics Table 1. Absolute Maximum Ratings (All voltages below are referenced to VSS) Parameter Symbol Limits Units DC Supply Voltage VDD -0.3 to +6.0 V Input Voltage VIN -0.3 to (VDD +0.3) V Storage Temperature TS -40 to +100 °C Operating Temperature [1] TA -40 to +85 °C Table 2. Recommended Operating Conditions Parameter Symbol Limits Units DC Supply Voltage VDD 4.5 to 5.5 V Ambient Temperature [1] TA -40 to +85 °C Table 3. DC Characteristics VDD = 5V ± 5%; TA = -40 to 85°°C Symbol Parameter Condition Min Typ Max Unit VIL [2] Low-Level Input Voltage 1.5 V VIH [2] High-Level Input Voltage VT+ Schmitt-Trigger Positive-Going Threshold VT- Schmitt-Trigger Negative-Going Threshold 1.0 1.5 V VH Schmitt-Trigger Hysteresis 1.0 2.0 V IIN Input Current VIN=VSS or VDD -10 1 VOH [2] High-Level Output Voltage IOH = -3.75 mA 2.4 4.5 VOL [2] Low-Level Output Voltage IOL = +3.75mA IOZ High-Z Output Leakage Current VO=VSS or VDD IDD Quiescent Supply Current CIN [3] COUT [3] 3.5 V 3.5 4.0 +10 V µA V 0.2 0.4 V 1 +10 µA VIN=Vss or VDD 1 10 µA Input Capacitance Any Input 5 PF Output Capacitance Any Output 5 PF -10 Notes: 1. Free Air 2. In general, for any VDD between the allowable limits (+4.5V to +5.5V), VIL = 0.3VDD and VIH = 0.7VDD; typical values are VOH = VDD – 0.5V and VOL = VSS + 0.2V 3. Including package capacitance but excluding PCB capacitance. 3 Functional Pin Description Table 4. Functional Pin Descriptions Pin Symbol HCTL-2017 HCTL-2021 Description VDD 16 20 Power Supply VSS 8 10 Ground CLK 2 2 CLK is a Schmitt-trigger input for the external clock signal. CHA CHB 7 6 9 8 CHA and CHB are Schmitt-trigger inputs that accept the outputs from a quadrature-encoded source, such as incremental optical shaft encoder. Two channels, A and B, nominally 90 degrees out of phase, are required. RST 5 7 This active low Schmitt-trigger input clears the internal position counter and the position latch. It also resets the inhibit logic. RST is asynchronous with respect to any other input signals. OE 4 4 This CMOS active low input enables the tri-state output buffers. The OE/ and SEL inputs are sampled by the internal inhibit logic on the falling edge of the clock to control the loading of the internal position data latch. SEL 3 3 These CMOS inputs directly controls which data byte from the position latch is enabled into the 8-bit tri-state output buffer. As in OE/ above, SEL also control the internal inhibit logic. SEL BYTE SELECTED 0 High 1 Low CNTDCDR NA 16 A pulse is presented on this LSTTL-compatible output when the quadrature decoder has detected a state transition. CNT U/D NA 5 This LSTTL-compatible output allows the user to determine whether the IC is counting up or down and is intended to be used with the CNT DCDR and CNTCAS outputs. The proper signal U (high level) or D/ (low level) will be present before the rising edge of the CNT DCDR and CNTCAS outputs. CNTCAS NA 15 A pulse is presented on this LSTTL-compatible output when the HCTL-2021 internal counter overflows or underflows. The rising edge on this waveform may be used to trigger an external counter. D0 1 1 D1 15 19 These LSTTL-compatible tri-state outputs form an 8-bit output ports through which the contents of the 16-bit position latch may be read in 2 sequential bytes. The High byte is read first followed by the Low bytes. D2 14 18 D3 13 17 D4 12 14 D5 11 13 D6 10 12 D7 9 11 NC NA 6 4 Not connected - this pin should be left floating. Switching Characteristics Table 5. Switching Characteristics Max/Min specifications at VDD = 5.0 ? 5%, TA = -40 to +85 OC, CL = 40 pf Symbol Description Min. 1 tCLK Clock Period 30 ns 2 tCHH Pulse width, clock high 15 ns 3 tCD Delay time, rising edge of clock to valid, updated count information on D0-7 31 ns 4 tODE Delay time, OE fall to valid data 29 ns 5 tODZ Delay time, OE rise to Hi-Z state on D0-7 29 ns 6 tSDV Delay time, SEL valid to stable, selected data byte (delay to High Byte = delay to Low Byte) 29 ns 7 tCLH Pulse width, clock low 15 ns 8 tSS Setup time, SEL before clock fall 12 ns 9 tOS Setup time, OEN before clock fall 12 ns 10 tSH Hold time, SEL after clock fall 0 ns 11 tOH Hold time, OE after clock fall 0 ns 12 tRST Pulse width, RST low 10 ns 13 tUDD Delay time, U/D valid after clock rise 4 29 ns 14 tCHD Delay time, CNTDCDR or CNTCAS high after clock rise 4 31 ns 15 tCLD Delay time, CNTDCDR or CNTCAS low after clock fall 4 31 ns Figure 1. Reset Waveform Figure 2. Waveforms for Positive Clock Edge Related Delays Figure 3. Tri-State Output Timing 5 Max. Units Figure 4. Bus Control Timing Figure 5. Decoder, Cascade Output Timing Operation A block diagram of the HCTL-20xx family is shown in Figure 6. The operation of each major function is described in the following sections. Figure 6. Simplified Logic Diagram 6 Digital Noise Filter The digital noise filter section is responsible for rejecting noise on the incoming quadrature signals. The input section uses two techniques to implement improved noise rejection. Schmitt-trigger inputs and a three-clockcycle delay filter combine to reject low level noise and large, short duration noise spikes that typically occur in motor system applications. Both common mode and differential mode noise are rejected. The user benefits from these techniques by improved integrity of the data in the counter. False counts triggered by noise are avoided. Figure 7 shows the simplified schematic of the input section. The signals are first passed through a Schmitttrigger buffer to address the problem of input signals with slow rise times and low-level noise (approximately < 1V). The cleaned up signals are then passed to a fourbit delay filter. The signals on each channel are sampled on rising clock edges. A time history of the signals is stored in the four-bit shift register. Any change on the input is tested for a stable level being present for three consecutive rising clock edges. Therefore, the filtered output waveforms can change only after an input level has the same value for three consecutive rising clock edges. Refer to Figure 8, which shows the timing diagram. The result of this circuitry is that short noise spikes between rising clock edges are ignored and pulses shorter than two clock periods are rejected. J Q CHA filtered Q CHB filtered CK K CHA D Q D Q D Q D Q CK J CK K CHB D Q D Q D Q D Q CK Figure 7. Simplified Digital Noise Filter Logic 3 t CLK CLK CHA tE CHB tE tES tE tES tES tE Noise Spike CHA filtered CHB filtered CHI filtered Figure 8. Signal Propagation through Digital Noise Filter 7 tES Quadrature Decoder Design Considerations The quadrature decoder decodes the incoming filtered signals into count information. This circuitry multiplies the resolution of the input signals by a factor of four (4X decoding). The designer should be aware that the operation of the digital filter places a timing constraint on the relationship between incoming quadrature signals and the external clock. Figure 8 shows the timing waveform with an incremental encoder input. Since an input has to be stable for three rising clock edges, the encoder pulse width (tE - low or high) has to be greater than three clock periods (3tCLK). This guarantees that the asynchronous input will be stable during three consecutive rising clock edges. A realistic design also has to take into account finite rise time of the waveforms, asymmetry of the waveforms, and noise. In the presence of large amounts of noise, tE should be much greater than 3tCLK to allow for the interruption of the consecutive level sampling by the three-bit delay filter. It should be noted that a change on the inputs that is qualified by the filter will internally propagate in a maximum of seven clock periods. The quadrature decoder samples the outputs of the CHA and CHB filters. Based on the past binary state of the two signals and the present state, it outputs a count signal and a direction signal to the integral position counter. Figure 9 shows the quadrature states of Channel A and Channel B signals. The 4x decoder will output a count signal for every state transition (count up and count down). Figure 9 shows the valid state transitions for 4x decoder. The 4x decoder will output a count signal at respective state transition, depending on the counting direction. Channel A leading channel B results in counting up. Channel B leading channel A results in counting down. Illegal state transitions, caused by faulty encoders or noise severe enough to pass through the filter, will produce an erroneous count. clk 2 1 state 3 4 chA chB Position Counter This section consists of a 16-bit binary up/down counter which counts on rising clock edges as explained in the Quadrature Decoder Section. All 16-bit of data are passed to the position data latch. The system can use this count data in several ways: Tes Te Telp count up A. System total range is d ≤ 16 bits, so the count represents "absolute" position. 1 Valid State Transitions 4 2 3 count down CHA CHB STATE 4X Decoder (Count Up & Count Down) 1 0 1 Pulse 1 1 2 Pulse 0 1 3 Pulse 0 0 4 Pulse Figure 9. 4x Decoder Mode 8 The quadrature decoder circuitry imposes a second timing constraint between the external clock and the input signals. There must be at least one clock period between consecutive quadrature states. As shown in Figure 8, a quadrature state is defined by consecutive edges on both channels. Therefore, tES (encoder state period) > tCLK. The designer must account for deviations from the nominal 90 degree phasing of input signals to guarantee that tES > tCLK. B. The system is cyclic with ≤ 16 bits of count per cycle. RSTN (or CHI) is used to reset the counter every cycle and the system uses the data to interpolate within the cycle. C. System count is > 8 or 16 bits, so the count data is used as a relative or incremental position input for a system software computation of absolute position. In this case counter rollover occurs. In order to prevent loss of position information, the processor must read the outputs of the IC before the count increments one-half of the maximum count capability. Two's-complement arithmetic is normally used to compute position from these periodic position updates. D. The system count is >16 bits so the HCTL-2021/2017 can be cascaded with other standard counter ICs to give absolute position. Position Data Latch Quadrature Decoder Output The position data latch is a 16-bit latch which captures the position counter output data on each rising clock edge, except when its inputs are disabled by the inhibit logic section during four-byte read operations. The output data is passed to the bus interface section. When active, a signal from the inhibit logic section prevents new data from being captured by the latch, keeping the data stable while successive reads are made through the bus section. The latch is automatically re-enabled at the end of these reads. The latch is cleared to 0 asynchronously by the RST signal. The quadrature decoder output section consists of count and up/down outputs derived from the 4x decoder mode of the HCTL-2021/2017. When the decoder has detected a count, a pulse, one-half clock cycle long, will be output on the CNTDCDR pin. This output will occur during the clock cycle in which the internal counter is updated. The U/D pin will be set to the proper voltage level one clock cycle before the rising edge of the CNTDCDR pulse, and held one clock cycle after the rising edge of the CNTDCDR pulse. These outputs are not affected by the inhibit logic. Inhibit Logic Cascade Output The Inhibit Logic Section samples the OE and SEL signals on the falling edge of the clock and, in response to certain conditions (see Figure 10), inhibits the position data latch. The RST signal asynchronously clears the inhibit logic, enabling the latch. The cascade output also consists of count and up/down outputs. When the HCTL-2021/2017 internal counter overflows or underflows, a pulse, one-half clock cycle long, will be output on the CNTCAS pin. This output will occur during the clock cycle in which the internal counter is updated. The U/D pin will be set to the proper voltage level one clock cycle before the rising edge of the CNTCAS pulse, and held one clock cycle after the rising edge of the CNTCAS pulse. These outputs are not affected by the inhibit logic. Bus Interface The bus interface section consists of a 16 to 8 line multiplexer and an 8-bit, three-state output buffer. The multiplexer allows independent access to the low and high bytes of the position data latch. The SEL and OE signals determine which byte is output and whether or not the output bus is in the high-Z state. Step SEL OE CLK Inhibit Signal Action 1 L L Falling 1 Set inhibit; read high byte 2 H L Falling 1 Read low byte; starts reset 3 X H Falling 0 Complete inhibit logic reset Figure 10. Two Bytes Read Sequence Figure 11. Simplified Inhibit Logic 9 Cascade Considerations The HCTL-2021/2017 cascading system allows for position reads of more than four bytes. These reads can be accomplished by latching all the bytes and then reading the bytes sequentially over the 8-bit bus. It is assumed here that, externally, a counter followed by a latch is used to count any count that exceeds 16 bits. This configuration is compatible with the HCTL-2021/ 2017 internal counter/latch combination. Consider the sequence of events for a read cycle that starts as the HCTL-2021/2017 internal counter rolls over. On the rising clock edge, count data is updated in the internal counter, rolling it over. A count-cascade pulse (CNTCAS) will be generated with some delay after the rising clock edge (t CHD ). There will be additional propagation delays through the external counters and registers. Meanwhile, with SEL and OE low to start the read, the internal latches are inhibited at the falling edge and do not update again till the inhibit is reset. If the CNTCAS pulse now toggles the external counter and this count gets latched a major count error will Figure 12. Decode and Cascade Output Diagram (4x) 10 occur. The count error is because the external latches get updated when the internal latch is inhibited. Valid data can be ensured by latching the external counter data when the high byte read is started (SEL and OE low). This latched external byte corresponds to the count in the inhibited internal latch. The cascade pulse that occurs during the clock cycle when the read begins gets counted by the external counter and is not lost. For example, suppose the HCTL-2021/2017 count is at FFFFh and an external counter is at F0h, with the count going up. A count occurring in the HCTL-2021/2017 will cause the counter to roll over and a cascade pulse will be generated. A read starting on this clock cycle will show FFFFh from the HCTL-2021/2017. The external latch should read F0h, but if the host latches the count after the cascade signal propagates through, the external latch will read F1h. General Interfacing Actions The 16-bit latch and inhibit logic allows access to 16 bits of count with an 8-bit bus. When only 8-bits of count are required, a simple 8-bit (1-byte) mode is available by holding SEL high continuously. This disables the inhibit logic. OE provides control of the tristate bus, and read timing is shown in Figure 2 and 3. 1. On the rising edge of the clock, counter data is transferred to the position data latch, provided the inhibit signal is low. For proper operation of the inhibit logic during a twobyte read, OE and SEL must be synchronous with CLK due to the falling edge sampling of OE and SEL. The internal inhibit logic on the HCTL-2021/2017 inhibits the transfer of data from the counter to the position data latch during the time that the latch outputs are being read. The inhibit logic allows the microprocessor / microcontroller to first read the high order 4 or 8 bits from the latch and then read the low order 8 bits from the latch. Meanwhile, the counter can continue to keep track of the quadrature states from the CHA and CHB input signals. Figure 11 shows the simplified inhibit logic circuit. The operation of the circuitry is illustrated in the read timing shown in Figure 13. 2. When OE goes low, the outputs of the multiplexer are enabled onto the data lines. If SEL is low, then the high order data bytes are enabled onto the data lines. If SEL is high, then the low order data bytes are enabled onto the data lines. 3. When the IC detects a low on OE and SEL during a falling clock edge, the internal inhibit signal is activated. This blocks new data from being transferred from the counter to the position data latch. 4. When SEL goes high, the data outputs change from the high byte to the low byte. 5. The first of two reset conditions for the inhibit logic is met when the IC detects a logic high on SEL and a logic low on OE during a falling clock edge. 6. When OE goes high, the data lines change to a high impedance state. 7. The IC detects a logic high on OE during a falling clock edge. This satisfies the second reset condition for the inhibit logic. Figure 13. Typical Interface Timing 11 For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries. Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved. Obsoletes 5989-4610EN AV01-0353EN - September 13, 2006