AL4CS205/215/225/235/245 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs Applications - Features Multimedia System ATM Switches Routers Cable Modems Wireless Base Stations SONET(Synchronous Optical Network) Multiplexers TBC(Time Base Corrector) Hard Disk cache memory Description The AL4CS2x5 series memory products are high-performance, low-power 18bit read/write FIFO (First-In-First-Out) memory chip designed to buffer high speed streaming data for a wide range of applications. The AL4CS2x5 FIFO memories are AverLogic Technologies, Inc.’s new serial products that are also specially designed to target at various communication applications. • • • • • • • • • • • • • High performance, low-power, FIFO(FirstIn First-Out) memory 256 x 18 bit I/O port (AL4CS205) 512 x 18 bit I/O port (AL4CS215) 1K x18 bit 1/O port (AL4CS225) 2K x18 bit I/O port (AL4CS235) 4K x18 bit I/O port (AL4CS245) High clock speed (133MHz) Fully independent read/write access Empty, Full, Half Full and programmable Almost Empty, Almost Full flags Output enable control (data skipping) Cascadable expansion in depth and width 3.3V±10% power supply with 5V signal tolerant input Standard 64-pin TQFP and STQFP Ordering Information Part number AL4CS205, AL4CS215, AL4CS225, AL4CS235, AL4CS245 Package 64-pin plastic TQFP and STQFP Power Supply +3.3V±10% 48 33 49 32 AVERLOGIC AL4CS2X5 X-XX-XX XXXXX XXXX 64 17 1 16 TQFP, STQFP PACKAGE TOP VIEW /OE Input data bus RAM ARRAY 256 x18, 512 x18 1024 x18, 2048 x18 4096 x18 Input Buffer Output Buffer Output data bus WCLK RCLK /WEN Write Control Logic Read Control Logic Write Pointer Read Pointer /REN /LD Flag Logic Offset Regissers /RS Expansion Logic Reset Logic /FF /EF /HF /PAF /PAE /WXO /RXO /WXI /RXI AL4CS205/215/225/235/245 FIFO Block Diagram The 18bit input and output ports operate independently at a maximum speed of 133 MHz. The built-in address decoder and pointer managing circuits provide a straightforward bus interface to serially read/write memory that reduces inter-chip design efforts. The AL4CS2x5 embedded memory array and high performance process technologies with extended controller functions (read skip, fixed and programmable status flags.. etc.) offer flexible memory management. These FIFOs support up to 18bit input and output data bus-width that is controlled by separate clock and enable signals respectively. The input data is acquired at each rising edge of a free running write clock while a write enable control pin is asserted. The output data is available after each rising edge of a free running read clock while a read enable and output enable control pins are asserted. When output enable (/OE) is LOW, the data output bus is active. If /OE is HIGH, the output data bus will be in a high-impedance. This signal can control whether the data is going to be skipped during the read operation. controlling software to manipulate the FIFO more easily or to do retransmit operation. Multiple AL4CS2x5s can cascade to expand the storage depth or provide a longer delay. The FIFOs can be chained by looping connect /WXO, /RXO pins of the first FIFO chip to /WXI, /RXI pins of successive chips respectively and connect /WXO, /RXO pins of last cascading chip to /WXI, /RXI pins of the first FIFO chip. Expanding AL4CS2x5 data bus width is also possible by using multiple AL4CS2x5 chips in parallel. These chips are available as a 64pin TQFP and STQFP Package. DISTRIBUTED BY: The FIFO Full/Empty, Half-Full and programmable Almost Full/Almost Empty flags are powerful functions that can help AVERLOGIC TECHNOLOGIES, INC. TEL: 1 408 361-0400 e-mail: [email protected] URL: www.averlogic.com April 5, 2002