AZ DISPLAYS, INC. COMPLETE LCD SOLUTIONS SPECIFICATIONS FOR LIQUID CRYSTAL DISPLAY PART NUMBER: REVISED: AGM1064B Series MAY 14, 2003 General Specification Table 1 Item Standard Value Unit Character Format 100X64 DOTS Dots Module Dimension 34.1(W) *25.3(H) *2.0(T) mm Viewing Area 28.0(W) * 20.9(H) mm DOT Size 0.21(W) * 0.234(H) mm DOT Pitch 0.24(W) * 0.264(H) mm Driving 1/64duty, 1/9bias View Direction 6H ■ TN □ LCD Type 12H □ STN Gray □ STN Yellow Green□ FSTN Negative □ FM LCD □ Reflective □ Display Mode DC/DC Converter STN Blue □ FSTN Positive ■ Color STN □ Transflective□ Transmissive ■ Driver IC Interface Other: □ NT7532H-TABF1 6800 □ Interna l ■ 8080□ Ｉ2 Ｃ□ External □ Operation Temperature -10℃—60℃ Storage Temperature -20℃—70℃ Page 1 Electronic Units 3.1 Absolute Maximum Ratings No ITEM Symbol Min. Typ. Max. Unit 1 OPERATING TEMPERATURE T OP -10 - 60 ℃ 2 STORAGE TEMPERATURE T ST -20 - 70 ℃ 3 SUPPLY VOLTAGE FOR LOGIC VDD -VSS VSS 3.6 V 4 SUPPLY VOLTAGE FOR LCD VLCD VSS 13.5 V 5 INPUT VOLTAGE VI VSS VDD+０．５ V 6 STATIC ELECTRICITY - Be sure that you are grounded when handing LCM 3.2 Electrical Characteristics (Ta=25℃, VDD=3.0V) No Item Symbol Condition Min. Typ. Max. Uni t 1 Supply Voltage For Logic VDD-VSS / / 3.0 / V 2 Supply Voltage For LCD Driver VDD-Vo (VLCD) / / 10.0 / V 3 Input High Voltage VIH H level 0.8VDD / VDD V 4 Input Low Voltage VIL L level 0 / 0.2VDD V 5 Supply Current For Logic IDD / / ／ １ mA 9 USED IC ＮＴ７５３２Ｈ－ＴＡＢＦ１（ＮＯＶＡＴＥＫ） *Idd Measurement condition is for all pixels on display. (Unit: mA) Page 2 3.3 Interface Pin Function NO SYMBOL 1 NC 2 NC 3 NC 4 NC I/O 5 FR I/O 6 CL I/O 7 /DOF I/O 8 NC 9 /CS1 10 CS2 11 RES Table 5 Description This is the liquid crystal alternating current signal I/O terminal M/S = “H”: Output M/S = “H”: Input When the NT7532 chip is used in master/slave mode, the various FR terminals must be connected. This is the display clock input terminal. When the NT7532 chips are used in master/slave mode, the various CL terminals must be connected. This is the liquid crystal display blanking control terminal. M/S = “H”: Output M/S = “H”: Input When the NT7532 chip is used in master/slave mode, the various DOF terminals must be connected. NC I This is the chip select signal. When CS1=“L”and CS2=“H”, then the chip select becomes active, and data/command I/O is enabled. I When RES is set to “L”, the settings are initialized. The reset operation is performed by the RES signal level 12 A0 I 13 RD/WR I 14 E/RD I 15 D0 I/O This is connected to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or a command. A0 = “H”: Indicate that D0 to D7 are display data A0 = “L”: Indicates that D0 to D7 are control data When connected to an 8080 MPU, this is active LOW. This terminal connects to the 8080 MPU WR signal. The signals on the data bus are latched at the rising edge of the WR signal. When connected to a 6800 Series MPU, this is the read/write control signal input terminal. When W R/ = “H”: Read When W R/ = “L”: Write When connected to an 8080 MPU, it is active LOW. This pad is connected to the RD signal of the 8080MPU, and the NT7532 data bus is in an output status when this signal is “L”. When connected to a 6800 Series MPU, this is active HIGH. This is used as an enable clock input of the 6800 series MPU This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus. Page 3 16 D1 17 D2 18 D3 19 D4 20 D5 When the serial interface is selected (P/S=“L”), then D7 serves as the serial data input terminal (SI) and D6 serves as the serial clock input terminal (SCL). At this time, D0 to D5 are set to high impedance. When the chip select is inactive, D0 to D7 are set to high impedance. 21 D6（SCL） 22 D7（SI） 23 DUTY0 Select the LCD driver duty DUTY1 DUTY1 I 24 LCD driver duty 0 0 1/33 0 1 1/49 1 0 1/55 1 1 1/69 DUTY1 2.4 - 3.5V power supply input. These pads must be connected 25 VDD Supply each other. 26 VDD2 Supply LCD. These pads must be connected each other. 27 VSS 28 VOUT O 29 NC NC 30 CAP3+ O Capacitor 3+ pad for internal DC/DC voltage converter. 31 CAP1- O Capacitor 1- pad for internal DC/DC voltage converter. 32 CAP1+ O Capacitor 1+ pad for internal DC/DC voltage converter. 33 CAP2+ O Capacitor 2+ pad for internal DC/DC voltage converter. 34 CAP2- O Capacitor 2- pad for internal DC/DC voltage converter. I This is the external input reference voltage (VREF) for the internal voltage regulator. It is valid only when external VREF is used. VEXT must be ≥ 2.4V and ≤ VDD2. When using internal VREF, this pad must be NC. 35 VEXT This is the power supply for the step-up voltage circuit for the Supply Ground output for pad option. DC/DC voltage converter output Page 4 36 VRS I 37 V1 38 V2 39 V3 40 V4 41 V0 42 VR I 43 M/S I 44 CLS I 45 C86 I 46 P/S I Supply 47 /HPM I 48 IRS I Select the internal voltage regulator or external voltage regulator. VRS = 0: using the external VREF VRS = 1: using the internal VREF LCD driver supplies voltages. The voltage determined by LCD cell is impedance-converted by a resistive driver or an operation amplifier for application. Voltages should be according to the following relationship: V0 = V1 = V2 = V3 = V4 = VSS When the on-chip operating power circuit is on, the following voltages are supplied to V1 to V4 by the on-chip power circuit. Voltage selection is performed by the Set LCD Bias command. LCD bias V1 V2 V3 1/5 bias 4/5V0 3/5V0 2/5V0 1/6 bias 5/6V0 4/6V0 2/6V0 1/7 bias 6/7V0 5/7V0 2/7V0 1/8 bias 7/8V0 6/8V0 2/8V0 1/9 bias 8/9V0 7/9V0 2/9V0 Voltage adjustment pad. Applies voltage between V0 and VSS using a resistive divider. This terminal selects the master/slave operation for the NT7532 chips. Master operation outputs the timing signals that are required for the LCD display, while slave operation inputs the timing signals required for the liquid crystal display, synchronizing the liquid crystal display system. Terminal to select whether enable or disable the display clock internal oscillator circuit. CLS = “H”: Internal oscillator circuit is enabled CLS = “L”: Internal oscillator circuit is disabled (requires external input) When CLS = “L”, input the display clock through the CL pad. This is the MPU interface switch terminal C86 = “H”: 6800 Series MPU interface C86 = “L”: 8080 MPU interface This is the parallel data input/serial data input switch terminal P/S = “H”: Parallel data input P/S = “L”: Serial data input The following applies depending on the P/S status: P/S "H" "L" Data/Command A0 A0 Data D0 to D7 SI (D7) Read/Write RD WR Write only Serial SCL (D6) When P/S = “L”, D0 to D5 are HZ. D0 to D5 may be “H”, “L”or Open. RD(E) and WR( W R/ ) are fixed to either “H”or “L”. With serial data input, RAM display data reading is not Supported. This is the power control terminal for the power supply circuit for liquid crystal drive. HPM = “H”, Normal mode HPM = “L”, High power mode This pad is enabled only when the master operation mode is selected and It is fixed to either “H”or “L”when the slave operation mode is selected. This terminal selects the resistors for the V0 voltage level adjustment. IRS = “H”, Use the internal resistors IRS = “L”, Do not use the internal resistors The V0 voltage level is regulated by an external resistive Page 5 voltage divider attached to the VR terminal. This pad is enabled only when the master operation mode is selected. It is fixed to either “H”or “L”when the slave operation mode is selected 49 NC NC 3.4 Commands The display control instructions control the internal state of the NT7532H-TABF1(NOVATEK). Instruction is received from MPU to NT7532H-TABF1(NOVATEK) for the splay control. The following table shows various instructions. *: Don’t care Command A0 RD WR D7 D6 D5 1 Hex 1 0 1 AEh AFh 1 0 1 0 Set Display Start Line 0 1 0 0 1 Set Page Address 0 1 0 1 0 1 1 Page Address 0 1 0 0 0 0 1 Higher Column Address 0 1 0 0 0 0 0 Lower Column Address 0 0 1 1 1 0 Write Data xx 1 0 1 Read Data xx ADC Select 0 1 0 1 0 1 0 0 0 0 0 1 A0h A1h Normal/Rever se Display 0 1 0 1 0 1 0 0 1 1 0 1 A6h A7h Entire Display ON/OFF 0 1 0 1 0 1 0 0 1 0 0 1 A4h A5h Set LCD Bias 0 1 0 1 0 1 0 0 0 1 01 A2h A3h Read-ModifyWrite 0 1 0 1 1 1 0 0 0 0 0 E0h End 0 1 0 1 1 1 0 1 1 1 0 EEh Write Display Data Read Display Data 1 D0 0 Read Status 0 D1 Display OFF Set Column Address 1 D4 Code D3 D2 40h TO 7Fh B0h to BFh Display Start Address Status 0 0 0 00h TO 1Fh 0 XX Function Turn on LCD panel when goes high, and turn off when goes low Specifies RAM display line for COM0 Set the display data RAM page in Page Address register Set 4 higher bits and 4 lower bits of column address of display data RAM in register Reads the status information Write data in display data RAM Read data from display data RAM Set the display data RAM address SEG output correspondence Normal indication when low, but full indication when high Selects normal display (0) or entire display on Sets LCD driving voltage bias ratio Increments column address counter during each write Releases the Read-Modify-Write Page 7 6 Reset Common Output Mode Select Set Power Control V0 Voltage Regulator Internal Resistor ratio Set Electronic Volume mode Set Electronic Volume Register Set Set Static indicator ON/OFF Set Static Indicator Register 0 0 0 1 1 1 0 0 0 1 1 0 1 1 0 1 0 1 0 0 0 0 1 0 0 * 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 * 0 * Operation Status 1 0 1 0 1 Electronic Control Value 0 1 0 * * 0 1 0 0 0 1 0 1 0 0 1 0 * * * * * * 1 Resets internal functions C0h to CFh Selects COM output scan direction *: invalid data 28h to 2Fh Resistor Ratio 0 E2h 20h to 27h Mode ACh ADh XX Power Save 0 1 0 - - - - - - - - - NOP 0 1 0 1 1 1 0 0 0 1 1 E3h Test Command 0 1 0 1 1 1 1 * * * * Test Mode Reset 0 1 0 1 1 1 1 0 0 0 0 Selects internal resistor ratio Rb/Ra mode 81h XX 0 1 Selects the power circuit operation mode F1h to FFh F0h Sets the V0 output voltage electronic volume register Sets static indicator ON/OFF 0: OFF, 1: ON Sets the flash mode Compound command of Display OFF and Entire Display ON Command for non-operation IC test command. Do not use! Command of test mode reset Page 5 3.5 Timing Characteristics 1. System Buses Read/Write Characteristics (for 8080 Series MPU) Symbol TAH8 TAS8 TCYC8 TEWHW TEWHR TEWLW TEWLR Parameter Address hold time Address setup time System cycle time Control low pulse width (write) Control low pulse width (read) Control high pulse width (write) Control high pulse width (read) Data setup time Data hold time /RD access time Output disable time Min TYP MAX UNIT Condition 0 0 300 - - ns ns ns SCL 90 - - ns WR 120 - - ns RD 120 - - ns WR 60 - - ns RD A0 TDS8 40 ns D0~D7 TDH8 15 ns TACC8 140 ns D0~D7, CL = 100pF TOH8 10 400 ns *1. The input signal rise time and fall time (tr, tf) is specified at 15ns or less. (tr + tf) < (tCYC8 - tCCLW - tCCHW ) for write, (tr + tf) < (tCYC8 - tCCLR - tCCHR) for read. *2. All timing is specified using 20% and 80% of VDD as the reference. *3. tCCLW and tCCLR are specified as the overlap interval when CS1 is low (CS2 is high) and WR or RD is low. 2. System Buses Read/Write Characteristics (for 6800 Series MPU) Page 5 Symbol TAH6 TAS6 TCYC6 TEWHW TEWHR TEWLW TEWLR TDS6 TDH6 TACC6 TOH6 Parameter Address hold time Address setup time System cycle time Control low pulse width (write) Control low pulse width (read) Control high pulse width (write) Control high pulse width (read) Data setup time Data hold time /RD access time Output disable time Min TYP MAX UNIT Condition 0 0 300 - - ns ns ns SCL 90 - - ns WR 120 - - ns RD 120 - - ns WR 60 - - ns RD 40 15 10 - 140 400 ns ns ns ns A0 D0~D7 D0~D7, CL = 100pF Page 5 3. Serial Interface Timing Symbol TSCYC TSHW TSLW TSAS TSAH TSDS TSDH TCSS TCSH Parameter Serial clock cycle Serial clock H pulse width Serial clock L pulse width Address setup time Address hold time Data setup time Data hold time Chip select setup time Chip select hold time Min TYP MAX UNIT Condition 250 - - ns SCL 100 - - ns SCL 100 - - ns SCL 150 150 100 100 150 150 - - ns ns ns ns ns ns D/I D/I SDI SDI CS1, CS2 CS1, CS2 *1. The input signal rise time and fall time (tr , tf) is specified at 15ns or less. *2. All timing is specified using 20% and 80% of VDD as the standard. Page 5 Electro -optical Units 4.1 Electro-optical Characteristics No Item Symbol Condition Min 1 Contrast Ratio CR Ta=23±3℃ - 5.5 - - Rise Tr θ１＝θ２＝ - 260 - ms Down Tf θ３＝θ４＝０ - 200 - ms - 60 - 2 Response time ６Ｈ φ＝２７０ １２Ｈ 3 Viewing Angle Range φ＝９０ ３Ｈ φ＝０ ９Ｈ φ＝１８０ 4 LCD Driving Voltage θ１ Typ Max Unit Drive Vop =10V 1/64 Duty θ２ θ３ Ta=23±3℃ Cr=2 θ４ VOP Ta=23±3℃ - 25 - 1/9 Bias Deg - 50 - - 50 - - 10 - f=100HZ V Page 5 BLUE ANODE 1.MODE: FSTN-Transflective-Positive 2.1/65duty,1/9bias,view angle 6 o'clock 3.Vdd=3.0V Vlcd=10.0V 4.Operation temperature:-10¡ãC~+60¡ãC 5.Store temperature:-20¡ãC~+70¡ãC 6.Driver IC:NT7532H-TABF1 7.The tolerance unless classified ¡À0.2 AZ Displays, Inc. AGM1064B-MLB-FBW DWG: SM5424