ARIZONA MICROTEK, INC. AZ12010 Multiply by 16, 32 Phase-Locked Loop Clock Generator FEATURES • • • • • • Differential Inputs/Outputs for External Voltage Controlled SAW Oscillator Optional Internal Crystal Oscillator Driver Internal Edge-Matching Phase/Frequency Detector Internal Charge-Pump/Integrator Amplifier RF Bipolar Design for Low Phase Noise Available in a 3x3 mm MLP Package PACKAGE AVAILABILITY PACKAGE MARKING NOTES MLP 16 (3x3) AZ12010AL AZ12010A <Date Code> MLP 16 (3x3) RoHS Compliant / Lead (Pb) Free AZ12010AL+ AZ12010A+ <Date Code> MLP 16 (3x3) AZ12010BL AZ12010B <Date Code> AZ12010BL+ AZ12010B+ <Date Code> 1,2 AZ12010XP N/A 3 MLP 16 (3x3) RoHS Compliant / Lead (Pb) Free DIE 1 DESCRIPTION PART NO. 2 3 1,2 1,2 1,2 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape & Reel. Date code format: “YY” for year followed by “WW” for week. Waffle Pack The AZ12010 contains all of the functional elements necessary to implement a Phase-Locked Loop for clock multiplication at frequencies up to 800 MHz. A fixed 32 times multiplication allows the use of low cost crystals or a low frequency reference signal. The output can be divided by two for 16 times net multiplication. The VCSO is differentially or single-ended driven using the chip CML SAW outputs. The dynamic properties of the PLL are under the control of the user through selection of the desired external components. 1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541 www.azmicrotek.com AZ12010 3X3 MLP 16 PACKAGE AZM12010A: CPPOL pulled High AZM12010B: CPPOL pulled Low November 2006 * REV - 5 www.azmicrotek.com 2 AZ12010 DIE MAP Pad Center Locations Signal Name SAWIN ¯¯¯¯¯¯¯ SAWIN TEST ENABLE VEE REFIN ¯¯¯¯¯¯¯¯ REFOUT CPOUT CPREF INTREF INTSUM VEE INTOUT CPPOL VBB VEEP Q ¯ Q VCC VCC SAWOUT ¯¯¯¯¯¯¯¯ SAWOUT DIV_SEL VEE November 2006 * REV - 5 X coordinate (μ) -522.0 -522.0 -522.0 -522.0 -522.0 -522.0 -365.0 -213.0 -61.0 91.0 243.0 395.0 552.0 552.0 552.0 552.0 552.0 552.0 395.0 243.0 91.0 -61.0 -219.0 -377.0 www.azmicrotek.com 3 Y coordinate (μ) 372.3 220.3 68.3 -83.7 -235.7 -387.7 -515.8 -515.8 -515.8 -515.8 -515.8 -515.8 -387.7 -235.7 -83.7 68.3 220.3 372.3 509.9 509.9 509.9 509.9 509.9 509.9 AZ12010 Name REFIN ¯¯¯¯¯¯¯¯ REFOUT CPREF CPOUT CPPOL INTREF INTSUM INTOUT SAWIN ¯¯¯¯¯¯¯ SAWIN SAWOUT SAWOUT ¯¯¯¯¯¯¯¯ ENABLE DIV_SEL Q Q ¯ VBB VEEP VCC VEE AZ12010 FUNCTIONAL PIN/PAD DESCRIPTIONS Functional Description Reference Frequency Input This pin/pad includes an on-chip 470 Ω pull down resistor to VBB. The input from the reference circuit should be AC coupled. Reference Frequency Output This pin is an inverted and amplified version of the signal on the REFIN pin. The gain from REFIN to ¯¯¯¯¯¯¯¯ REFOUT is approximately 20. If VEEP is connected to VEE, a 4 ma on-chip current source is provided for the output. ¯¯¯¯¯¯¯¯ REFOUT is not available on the packaged versions (AZ12010A, AZ12010B). Charge Pump Reference Output The pin/pad voltage is nominally 1.2 volts below VCC. Charge Pump Output The charge pump output voltage is VCPREF ±0.3V during a phase correction pulse. When there is no correction pulse the output goes high impedance. Charge Pump Polarity When this pin/pad is pulled high the PLL operates with a VCSO circuit exhibiting negative pulling slope (the VCSO frequency goes down when the control voltage goes up). When this pin/pad is pulled low (AZM12010B) the PLL operates with a VCSO circuit exhibiting positive pulling slope (the VCSO frequency goes up when the control voltage goes up). If the pin/pad is left open (AZM12010A), an internal pullup resistor selects negative pulling slope mode. Integrator Reference Input This pin/pad should be connected to CPREF through a bias current cancellation network Integrator Summing Junction This pin/pad is the summing junction for the integrator amplifier Integrator Output SAW Amplifier Inputs If only one input is used (Single-ended VCSO), the unused input should be bypassed with a capacitor to VBB. SAW Amplifier Outputs These are open collector outputs for driving the VCSO device. Operating at nominally 9 ma, external pullup resistors must be connected between these pins/pads and VCC. If only one output is used, the other output should be connected to VCC through a 50Ω resistor. PLL Output Enable The Q and Q ¯ outputs are enabled when this pin/pad is pulled high. When this pin/pad is low, the Q output is high, and the Q ¯ output is low. If the pin/pad is left open, an internal pullup resistor enables the outputs. Divide Select When this pin/pad is high, the Q and Q ¯ outputs are divided by one from the SAW device. When it is low, the Q and Q ¯ outputs are divided by two from the SAW device. If the pin/pad is left open, an internal pullup resistor selects the divide by one mode. Clock Output These pin/pads are the main clock output. When ENABLE is low, the outputs are disabled with Q high and Q ¯ low. Reference Voltage Output This pin/pad is used to bias the REFIN signal. It must be bypassed externally to the VEE pins/pads with a 0.01 μF capacitor. REFOUT ¯¯¯¯¯¯¯¯ Current Source If VEEP is connected to VEE, a 4 ma on-chip current source is provided for the ¯¯¯¯¯¯¯¯ REFOUT output. VEEP is not available on the packaged versions (AZ12010A, AZ12010B). Positive Supply +3.0 to +3.6 V Negative Supply Ground November 2006 * REV - 5 www.azmicrotek.com 4 Logic Level PECL LVCMOS LVTTL CML (Analog) LVCMOS LVTTL LVCMOS LVTTL PECL AZ12010 Absolute Maximum Ratings are those values beyond which device life may be impaired. Symbol VCC VI IOUT TA TSTG Characteristic Power Supply (VEE = GND) Input Voltage (VEE = GND) — Continuous PECL Output Current — Surge Operating Temperature Range Storage Temperature Range Rating 0 to +6.0 0 to +6.0 50 100 -40 to +85 -65 to +150 Unit Vdc Vdc mA °C °C AZ12010 DC CHARACTERISTICS (VCC = +3.0 to +3.6 V, VEE = GND) Symbol -40°C Min Max VCC VCC -1.38 -1.26 Characteristic Reference Voltage VBB REFIN Pull-Down resistor to VBB SAWIN, ¯¯¯¯¯¯¯ SAWIN PullDown resistor to VBB High level integrator output RREF RSAW VHCTL Output HIGH Voltage VOH 1 Q, Q ¯ Output HIGH Voltage2 SAWOUT, SAWOUT ¯¯¯¯¯¯¯¯ VOH Output LOW Voltage1 VOL 2 Q, Q ¯ Output LOW Voltage SAWOUT, SAWOUT ¯¯¯¯¯¯¯¯ Input HIGH Voltage, VIH LVCMOS/LVTTL EN, DIV_SEL Input LOW Voltage, VIL LVCMOS/LVTTL EN, DIV_SEL ICC (IEE) Power Supply Current 1. Load is 50Ω to VCC-2V 2. Load is 50Ω to VCC VOL Max VCC -1.26 Min VCC -1.38 25°C Typ VCC -1.31 85°C Max VCC -1.26 Min VCC -1.38 Max VCC -1.26 VCC -1.0 VCC -1.0 0.5 VCC -1.0 0.5 0.5 VCC -1085 VCC -880 VCC -1025 VCC -880 VCC -1025 VCC -10 VCC VCC -10 VCC VCC -10 VCC -1830 VCC -349 VCC -1555 VCC -481 VCC -1810 VCC -365 VCC -1620 VCC -516 VCC -1810 VCC -392 2.2 VCC 2.2 VCC 0.0 0.8 0.0 V 0.5 V VCC -880 VCC -1025 VCC -880 mV VCC VCC -10 VCC mV VCC -1620 VCC -557 VCC -1810 VCC -465 VCC -1620 VCC -661 2.2 VCC 2.2 VCC V 0.8 0.0 0.8 0.0 0.8 V 65 45 65 mA 65 VCC -955 V Ω 10K VCC -1.0 Unit Ω 470 Low level integrator output VLCTL 0°C Min VCC -1.38 VCC -1705 VCC -449 54 65 mV mV AZ 12010 AC CHARACTERISTICS (VCC = +3.0 to +3.6 V, VEE = GND) Symbol APD fVCO t r / tf aV 1. Characteristic Phase Detector Gain External VSCO frequency Output Rise & Fall Times (20% - 80%) Q,¯¯ Q SAW Amplifier and Driver Gain at 622.08 MHz1 Min -40°C Typ Max Min 25°C Typ Max Min Max 20.3 800 800 800 120 18 24.5 28 15.5 21 www.azmicrotek.com 5 Unit radians/V MHz ps 24.5 13.5 Single Ended Input and Output, Driven from 50Ω backmatched source, Load 50Ω to VCC. November 2006 * REV - 5 85°C Typ 19 22.5 dB AZ12010 Loop Filter Design The combination of the phase detector, amplifier, VCO and divider form a second-order phase-locked loop. Proper selection of the loop components is important to obtain stable, low jitter operation. The loop bandwidth (or natural frequency, ωn) and damping factor (ζ) are the two major driving forces that define the loop’s response to a disturbance. The value of ζ is typically 0.7 to ensure the fastest step response consistent with no ringing. However in many oscillator application ζ may be 3 or higher to provide further phase noise reduction. ωn is chosen as a compromise between settling time, VCO jitter and reference feedthrough. These values can be computed by the following equations: ωn = ζ = 1 N Kφ KVCO τ1 τ 2ω n 2 τ 1 = R1C1 τ 2 = R2 C1 Kφ = Phase Detector Gain (20.3 radians/V) KVCO = VCO Gain (radians/sec/volt) N = Frequency Divisor value (32) The component definitions are shown in the figure below. R3 should be equal to R1 to minimize integrator offsets. C1 R1 R2 EXTERNAL VCSO CONTROL VOLTAGE R3 CPREF CPOUT INTREF INTSUM INTOUT INTEGRATOR CHARGE PUMP Figure 1 Charge Pump and Integrator November 2006 * REV - 5 www.azmicrotek.com 6 AZ12010 Application Circuit A typical application circuit is shown in Figure 2. VCC C1 R1 CPPOL CPOUT CPREF R3 R2 INTREF INTSUM INTOUT VCC ENABLE CONT OUTPT DRVR REFOUT CHARGE PUMP ENABLE DIV_SEL INTEGRATOR 4mA VEEP Q PLL OUTPUT Q MUX REFIN INPUT RCVR PHASE/ FREQ DETECT R4 470 Ω VBB SAW RCVR VBB C2 0.01 μF F SAWOUT /16 SAW DRIVE SAWOUT /2 2 x 10kΩ VEE SAWIN SAWIN C3 0.01 μF GROUND SAW RESONATOR W/ MATCHING & TUNING NETWORK Figure 2. Typical Application, Always Enabled and Divide by One for Output November 2006 * REV - 5 www.azmicrotek.com 7 R5 AZ12010 PACKAGE DIAGRAM MLP 16 NOTES NOTES 1. DIMENSIONING AND TOLERANCING 1. DIMENSIONING AND TOLERANCING CONFORM TO ASME T14-1994. CONFORM TO ASME #1 T14-1994. 2. THE TERMINAL AND PAD 2. THE NUMBERING TERMINAL #1CONVENTION AND PAD SHALL NUMBERING CONVENTION CONFORM TO JESD 95-1SHALL SPP-012. CONFORM TO JESD 95-1 SPP-012. 3. DIMENSION b APPLIES TO METALLIZED 3. DIMENSION b APPLIES TO METALLIZED PAD AND IS MEASURED BETWEEN 0.25 PAD AND AND 0.30mm IS MEASURED BETWEEN FROM PAD TIP. 0.25 ANDCOPLANARITY 0.30mm FROM PAD TIP. TO THE 4. APPLIES 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE EXPOSED PAD AS WELL AS THE TERMINALS. TERMINALS. MILLIMETERS DIMMILLIMETERS MIN MAX DIMA MIN 0.80 MAX 1.00 A A1 0.800.00 1.100.05 A1 A3 0.00 0.250.05 REF 0.25 A3 b 0.18REF 0.30 b D 0.225 3.90 0.275 4.10 D D2 2.902.65 3.102.95 D2 E 1.653.90 1.954.10 E E2 2.902.65 3.102.95 E2 e 1.65 0.501.95 BSC 0.50 e L 0.35BSC 0.45 0.45 L aaa 0.35 0.25 0.250.10 aaabbb 0.100.10 bbbccc 0.10 ccc November 2006 * REV - 5 www.azmicrotek.com 8 AZ12010 Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part. November 2006 * REV - 5 www.azmicrotek.com 9