ADS5510 SLAS499 – JANUARY 2007 11-Bit, 125-MSPS Analog-To-Digital Converter • FEATURES • • • • • • • • • • • 11-bit Resolution 125-MSPS Sample Rate High SNR: 66.3 dBFS at 100 MHz fIN High SFDR: 81 dBc at 100 MHz fIN 2.3-VPP Differential Input Voltage Internal Voltage Reference 3.3-V Single-Supply Voltage Analog Power Dissipation: 578 mW Serial Programming Interface TQFP-64 PowerPAD™ Package Pin-Compatible With: – ADS5500 (14-Bit, 125 MSPS) – ADS5541 (14-Bit, 105 MSPS) – ADS5542 (14-Bit, 80 MSPS) – ADS5520 (12-Bit, 125 MSPS) – ADS5521 (12-Bit, 105 MSPS) – ADS5522 (12-Bit, 80 MSPS) Recommended Operational Amplifiers: THS3201, THS3202, THS4503, THS4509, THS9001, OPA695, OPA847 APPLICATIONS • • • • • • Wireless Communication – Communication Receivers – Base Station Infrastructure Test and Measurement Instrumentation Single and Multichannel Digital Receivers Communication Instrumentation – Radar – Infrared Video and Imaging Medical Equipment DESCRIPTION The ADS5510 is a high-performance, 11 bit, 125 MSPS analog-to-digital converter (ADC). To provide a complete converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for applications demanding the highest speed and highest dynamic performance in little space, the ADS5510 has excellent power consumption of 578 mW at 3.3-V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements. Parallel CMOS-compatible output ensures seamless interfacing with common logic. The ADS5510 is available in 64-pin TQFP PowerPAD package over the industrial temperature range. AVDD CLK+ CLK− VIN+ Timing Circuitry S&H VIN− CM DRVDD 11-Bit Pipeline ADC Core Internal Reference CLKOUT Digital Error Correction SEN SDATA SCLK D0 . . . D10 OVR DFS Control Logic Serial Programming Register A GND Output Control ADS5510 DRGND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated ADS5510 www.ti.com SLAS499 – JANUARY 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ADS5510 HTQFP-64 (2) PowerPAD PAP –40°C to 85°C ADS5510I (1) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS5510IPAP Tray, 160 ADS5510IPAPR Tape and Reel, 1000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Thermal pad size: 3,5 mm x 3,5 mm (min), 4 mm x 4 mm (max). θJA = 21.47°C/W and θJC = 2.99°C/W, when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard, four-layer, 3 in x 3 in PCB. (2) ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VSS –0.3 to 3.7 V ±0.1 V –0.3 to minimum (AVDD + 0.3, 3.6) V Logic input to DRGND –0.3 to DRVDD V Digital data output to DRGND –0.3 to DRVDD V Operating temperature range –40 to 85 °C 105 °C –65 to 150 °C Supply Voltage AVDD to AGND, DRVDD to DRGND AGND to DRGND Analog input to AGND (2) (3) TJ Tstg (1) (2) (3) Junction temperature Storage temperature range Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. If the input signal can exceed 3.6 V, then a resistor greater than or equal to 25 Ω should be added in series with each of the analog input pins to support input voltages up to 3.8 V. For input voltages above 3.8 V, the device can only handle transients and the duty cycle of the overshoot should be limited to less than 5% for inputs up to 3.9 V. The overshoot duty cycle can be defined as the ratio of the total time of overshoot to the total intended device lifetime, expressed as a percentage. The total time of overshoot is the integrated time of all overshoot occurrences over the lifetime of the device. RECOMMENDED OPERATING CONDITIONS PARAMETER MIN TYP MAX UNIT Supplies AVDD Analog supply voltage 3 3.3 3.6 V DRVDD Output driver supply voltage 3 3.3 3.6 V 1.45 1.55 Analog input Differential input range VCM 2.3 Input common-mode voltage (1) VPP 1.65 V Digital Output Maximum output load 10 pF Clock Input ADCLK input sample rate (sine wave) 1/tC DLL ON 60 125 DLL OFF 2 80 Clock amplitude, sine wave, differential 1 Clock duty cycle TA (1) 2 3 MSPS VPP 50% Open free-air temperature range –40 Input common-mode should be connected to CM. Submit Documentation Feedback 85 °C ADS5510 www.ti.com SLAS499 – JANUARY 2007 ELECTRICAL CHARACTERISTICS Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.3 V, sampling rate = 125 MSPS, 50% clock duty cycle, DLL On, 3-VPP differential clock, and –1 dBFS differential input, unless otherwise noted PARAMETER CONDITIONS MIN Resolution TYP MAX UNIT 11 bits 2.3 VPP Analog Inputs Differential input range Differential input impedance See Figure 24 6.6 kΩ Differential input capacitance See Figure 24 4 pF 300 µA Analog input common-mode current (per input) Analog input bandwidth Source impedance = 50 Ω 750 Voltage overload recovery time MHz Clock cycles 4 Internal Reference Voltages V(REFM) Reference bottom voltage V(REFP) Reference top voltage 0.95 Reference error VCM V 2.1 –4% ±0.9% V 4% 1.55 ±0.05 Common-mode voltage output V Dynamic DC Characteristics and Accuracy No missing codes Tested DNL Differential nonlinearity error fIN = 10 MHz -0.5 ±0.25 0.5 LSB INL Integral nonlinearity error fIN = 10 MHz -1.5 ±0.8 1.5 LSB -11 +2.5 +11 mV Offset error Offset temperature coefficient PSRR DC power-supply rejection ratio Gain error ∆offset error/∆AVDD from AVDD = 3 V to AVDD = 3.6 V (1) -2 Gain temperature coefficient 0.01 mV/°C 0.25 mV/V ±0.45 0.01 +2 %FS ∆%/°C Dynamic AC Characteristics fIN = 10 MHz SNR Signal-to-noise ratio 62.5 66.5 fIN = 100 MHz 66.3 fIN = 130 MHz 66 fIN = 170 MHz fIN = 10 MHz SFDR Spurious-free dynamic range (1) Second-harmonic dBFS 65.5 73 84 fIN = 70 MHz 81 fIN = 100 MHz 82 fIN = 130 MHz 78 fIN = 170 MHz 72 fIN = 10 MHz HD2 66.7 fIN = 70 MHz 73 dBc 91 fIN = 70 MHz 87 fIN = 100 MHz 84 fIN = 130 MHz 79 fIN = 170 MHz 74 dBc Gain error is specified by design and characterization; it is not tested in production. Submit Documentation Feedback 3 ADS5510 www.ti.com SLAS499 – JANUARY 2007 ELECTRICAL CHARACTERISTICS (continued) Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.3 V, sampling rate = 125 MSPS, 50% clock duty cycle, DLL On, 3-VPP differential clock, and –1 dBFS differential input, unless otherwise noted PARAMETER CONDITIONS fIN = 10 MHz HD3 Third-harmonic MIN TYP 73 84 fIN = 70 MHz 81 fIN = 100 MHz 82 fIN = 130 MHz 78 fIN = 170 MHz fIN = 10 MHz ENOB Signal-to-noise + distortion UNIT dBc 72 62 fIN = 70 MHz SINAD MAX 66.5 66.3 fIN = 100 MHz 66 fIN = 130 MHz 65.6 fIN = 170 MHz 65 10.0 dBFS Effective number of bits fIN = 10 MHz IMD Two-tone intermodulation distortion f = 50.1 MHz, 46.1 MHz (-7 dBFS each tone) 10.8 Bits 85 dBFS PSRR AC power supply rejection ratio Supply noise frequency ≤ 100 MHz 35 dB Power Supply 4 ICC Total supply current fIN = 10 MHz 236 260 mA I(AVDD) Analog supply current fIN = 10 MHz 175 190 mA I(DRVDD) Output buffer supply current fIN = 10 MHz 61 70 mA Analog only 578 627 Power dissipation Output buffer power with 10-pF load on digital output to ground 202 231 Standby power With Clocks running 180 250 Submit Documentation Feedback mW mW ADS5510 www.ti.com SLAS499 – JANUARY 2007 DIGITAL CHARACTERISTICS Valid over full recommended operating temperature range, AVDD = DRVDD = 3.3 V, unless otherwise noted PARAMETER CONDITIONS MIN TYP MAX UNIT Digital Inputs VIH High-level input voltage 2.4 VIL Low-level input voltage 0.8 V IIH High-level input current 10 µA IIL Low-level input current -10 µA Input current for RESET Input capacitance V –20 µA 4 pF Digital Outputs VOL Low-level output voltage CLOAD = 10 pF VOH High-level output voltage CLOAD = 10 pF Output capacitance Submit Documentation Feedback 0.3 2.4 0.4 V 3 V 3 pF 5 ADS5510 www.ti.com SLAS499 – JANUARY 2007 TIMING CHARACTERISTICS (1) (2) Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.3 V, sampling rate = 125 MSPS, 50% clock duty cycle, 3-VPP differential clock, and CLOAD = 10 pF, unless otherwise noted PARAMETER DESCRIPTION MIN TYP MAX UNIT Switching Specification tA tSETUP Aperture delay Input CLK falling edge to data sampling point Aperture jitter (uncertainty) Uncertainty in sampling instant fs 2.3 2.7 ns 1.7 2 ns Data tHOLD Data hold time 50% of CLKOUT rising edge to data becoming invalid (3) tSTART Input clock to output data valid start (4) (5) Input clock rising edge to data valid start delay tEND Input clock to output data valid end (4) (5) Input clock rising edge to data valid end delay tJIT Output clock jitter Uncertainty in CLKOUT rising edge, peak-to-peak 150 210 psPP tr Output clock rise time Rise time of CLKOUT from 20% to 80% of DRVDD 1.7 1.9 ns tf Output clock fall time Fall time of CLKOUT from 80% to 20% of DRVDD 1.5 1.7 ns tPDI Input clock to output clock delay Input clock rising edge, zero crossing, to output clock rising edge 50% 4.8 5.5 ns tr Data rise time Data rise time measured from 20% to 80% of DRVDD 3.6 4.6 ns tf Data fall time Data fall time measured from 80% to 20% of DRVDD 2.8 3.7 ns Output enable(OE) to data output delay Time required for outputs to have stable timings with regard to input clock (6) after OE is activated 1000 Time to valid data after coming out of software power down 1000 Time to valid data after stopping and restarting the clock 1000 Latency (1) (2) (3) (4) (5) (6) to 50% of CLKOUT rising edge ns Data setup time Wakeup time 6 valid (3) 1 300 Time for a sample to propagate to the ADC outputs 2 5.8 4.2 2.6 6.9 17.5 ns ns Clock cycles Clock cycles Clock cycles Timing parameters are ensured by design and characterization, and not tested in production. See Table 5 through Table 8 in the Application Information section for timing information at additional sampling frequencies. Data valid refers to 2 V for LOGIC HIGH and 0.8 V for LOGIC LOW. See the Output Information section for details on using the input clock for data capture. These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 2). Add 1/2 clock period for the valid number for a falling edge CLKOUT polarity. Data outputs are available within a clock from assertion of OE; however, it takes 1000 clock cycles to ensure stable timing with respect to input clock. Submit Documentation Feedback ADS5510 www.ti.com SLAS499 – JANUARY 2007 Analog Input Signal Sample N N + 1 N + 2 N + 3 N + 4 N + 14 N + 15 N + 16 N + 17 tA Input Clock tSTART Output Clock tPDI tsu Data Out (D0−D10) N − 17 N − 16 N − 15 N − 13 N−3 N−2 N−1 Data Invalid tEND A. N − 14 17.5 Clock Cycles N th It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing matches closely with the specified values. Figure 1. Timing Diagram RESET TIMING CHARACTERISTICS Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.3 V, and 3-VPP differential clock, unless otherwise noted PARAMETER DESCRIPTION MIN TYP MAX UNIT Switching Specification t1 Power-on delay Delay from power-on of AVDD and DRVDD to RESET pulse active 10 ms t2 Reset pulse width Pulse width of active RESET signal 2 µs t3 Register write delay Delay from RESET disable to SEN active 2 µs Power-up time Power Supply (AVDD, DRVDD) Delay from power-up of AVDD and DRVDD to output stable 40 ms t1 10 ms t2 2 ms t3 2 ms SEN Active RESET (Pin 35) Figure 2. Reset Timing Diagram Submit Documentation Feedback 7 ADS5510 www.ti.com SLAS499 – JANUARY 2007 SERIAL PROGRAMMING INTERFACE CHARACTERISTICS The ADS5510 has a three-wire serial interface. The ADS5510 latches serial data SDATA on the falling edge of serial clock SCLK when SEN is active. • Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at the falling edge. • Minimum width of data stream for a valid loading is 16 clocks. • Data is loaded at every 16th SCLK falling edge while SEN is low. • In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. • Data can be loaded in multiples of 16-bit words within a single active SEN pulse. • The first 4-bit nibble is the address of the register while the last 12 bits are the register contents. A3 SDATA A2 A1 A0 D11 D10 ADDRESS D9 D0 DATA MSB Figure 3. DATA Communication is 2-Byte, MSB First SEN tSLOADS tSLOADH tWSCLK tWSCLK tSCLK SCLK tsu(D) SDATA th(D) MSB LSB MSB LSB 16 x M Figure 4. Serial Programming Interface Timing Diagram Table 1. Serial Programming Interface Timing Characteristics (1) 8 SYMBOL PARAMETER tSCLK SCLK period MIN (1) TYP (1) MAX (1) 50 ns tWSCLK SCLK duty cycle tSLOADS SEN to SCLK setup time 8 ns tSLOADH SCLK to SEN hold time 6 ns tDS Data setup time 8 ns tDH Data hold time 6 ns Typ, min, and max values are characterized, but not production tested. Submit Documentation Feedback 25% UNIT 50% 75% ADS5510 www.ti.com SLAS499 – JANUARY 2007 Table 2. Serial Register Table A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 (1) D0 DLL CTRL DESCRIPTION Clock DLL 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Internal DLL is on; recommended for 60 MSPS to 125 MSPS clock speeds. 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 Internal DLL is off; recommended for 2 MSPS to 80 MSPS clock speeds. TP<1> TP<0> 1 1 1 0 0 0 0 0 0 0 0 0 0 0 X 0 Normal mode of operation 1 1 1 0 0 0 1 0 0 0 0 0 0 0 X 0 All outputs forced to 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 X 0 All outputs forced to 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 X 0 Each output bit toggles between 0 and 1. Test Mode PDN (2) (3) Power Down 1 1 1 1 0 0 0 0 0 0 0 0 0 0 X 0 Normal mode of operation 1 1 1 1 1 0 0 0 0 0 0 0 0 0 X 0 Device is put in power-down (low-current) mode. (1) (2) (3) The register contents default to the appropriate setting for normal operation up on RESET. The patterns given are applicable to the straight offset binary output format. If two's complement output format is selected, the test mode outputs will be the binary two's complement equivalent of these patterns as described in the Output Information section. While each bit toggles between 1 and 0 in this mode, there is no assured phase relationship between the data bits D0 through D10. For example, when D0 is a 1, D1 in not assured to be a 0, and vice versa. Table 3. Data Format Select (DFS) Table DFS-PIN VOLTAGE (VDFS) V DFS t 2 12 AV DD DATA FORMAT CLOCK OUTPUT POLARITY Straight Binary Data valid on rising edge 4 12 5 AV DD t V DFS t 12 AV DD Two's Complement Data valid on rising edge 7 12 8 AV DD t V DFS t 12 AV DD Straight Binary Data valid on falling edge Two's Complement Data valid on falling edge V DFS u 10 12 AV DD Submit Documentation Feedback 9 ADS5510 www.ti.com SLAS499 – JANUARY 2007 PIN CONFIGURATION 10 54 53 52 51 50 DRVDD 55 DRGND 56 D1 57 D2 58 D4 59 D3 60 D5 D7 61 D6 D8 62 DRGND D9 63 DRVDD D10 (MSB) 64 DRGND OVR PAP PACKAGE HTQFP-64 (TOP VIEW) 49 DRGND 1 48 DRGND SCLK 2 47 D0 (LSB) SDATA 3 46 NC SEN 4 45 NC AVDD 5 44 NC AGND 6 43 CLKOUT AVDD 7 42 DRGND AGND 8 AVDD 9 ADS5510 PowerPAD 41 OE 40 DFS 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AGND 18 IREF 17 REFM 33 AVDD REFP AGND 16 AVDD 34 AVDD AGND AVDD 15 AGND 35 RESET AVDD AGND 14 AVDD 36 AGND AGND AGND 13 AVDD 37 AVDD AGND AGND 12 INM 38 AGND INP CLKM 11 AGND 39 AVDD CM CLKP 10 Submit Documentation Feedback ADS5510 www.ti.com SLAS499 – JANUARY 2007 PIN CONFIGURATION (continued) PIN ASSIGNMENTS (1) TERMINAL NO. OF PINS I/O AVDD 5, 7, 9, 15, 22, 24, 26, 28, 33, 34, 37, 39 12 I Analog power supply AGND 6, 8, 12, 13, 14, 16, 18, 21, 23, 25, 27, 32, 36, 38 14 I Analog ground DRVDD 49, 58 2 I Output driver power supply DRGND 1, 42, 48, 50, 57, 59 6 I Output driver ground NC 44, 45, 46 2 — INP 19 1 I Differential analog input (positive) INM 20 1 I Differential analog input (negative) REFP 29 1 O Reference voltage (positive); 0.1-µF capacitor in series with a 1-Ω resistor to GND REFM 30 1 O Reference voltage (negative); 0.1-µF capacitor in series with a 1-Ω resistor to GND IREF 31 1 I Current set; 56-kΩ resistor to GND; do not connect capacitors CM 17 1 O Common-mode output voltage RESET 35 1 I Reset (active high), 200-kΩ resistor to AVDD (2) OE 41 1 I Output enable (active high) DFS 40 1 I Data format and clock out polarity select (3) (4) CLKP 10 1 I Data converter differential input clock (positive) CLKM 11 1 I Data converter differential input clock (negative) SEN 4 1 I Serial interface chip select (4) SDATA 3 1 I Serial interface data (4) SCLK 2 1 I Serial interface clock (4) 47, 51-56, 60-63 11 O 11 bit parallel data output OVR 64 1 O Over-range indicator bit CLKOUT 43 1 O CMOS clock out in sync with data NAME NO. D0 (LSB) to D10 (MSB) (1) (2) (3) (4) DESCRIPTION Not connected PowerPAD is connected to analog ground. If unused, the RESET pin should be tied to AGND. See the serial programming interface section for details. Table 3 defines the voltage levels for each mode selectable via the DFS pin. Pins OE, DFS, SEN, SDATA, and SCLK have internal clamping diodes to the DRVDD supply. Any external circuit driving these pins must also run off the same supply voltage as DRVDD. Submit Documentation Feedback 11 ADS5510 www.ti.com SLAS499 – JANUARY 2007 DEFINITION OF SPECIFICATIONS Offset Error Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low frequency value. Aperture Delay The delay in time between the falling edge of the input sampling clock and the actual time at which the sampling occurs. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine wave clock results in a 50% duty cycle. Maximum Conversion Rate The maximum sampling rate at which certified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs. Integral Nonlinearity (INL) The offset error is the difference, given in number of LSBs, between the ADC's actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV. Temperature Drift The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference (TMAX – TMIN). Signal-to-Noise Ratio (SNR) SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and the first eight harmonics. P SNR + 10Log 10 S PN SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference or dBFS (dB to Full-Scale) when the power of the fundamental is extrapolated to the converter's full-scale range. Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. PS SINAD + 10Log 10 PN ) PD The INL is the deviation of the ADC's transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter's full-scale range. Gain Error Effective Number of Bits (ENOB) The gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error does not account for variations in the internal reference voltages (see the Electrical Specifications section for limits on the variation of VREFP and VREFM). The ENOB is a measure of a converter's performance as compared to the theoretical limit based on quantization noise. ENOB + SINAD * 1.76 6.02 12 Submit Documentation Feedback ADS5510 www.ti.com SLAS499 – JANUARY 2007 Total Harmonic Distortion (THD) Two-Tone Intermodulation Distortion (IMD3) THD is the ratio of the power of the fundamental (PS) to the power of the first eight harmonics (PD). P THD + 10Log 10 S PD IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to Full-Scale) when the power of the fundamental is extrapolated to the converter's full-scale range. THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). DC Power Supply Rejection Ration (DC PSRR) The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is typically given in units of mV/V. Reference Error The reference error is the variation of the actual reference voltage (VREFP - VREFM) from its ideal value. The reference error is typically given as a percentage. Voltage Overload Recovery Time The voltage overload recovery time is defined as the time required for the ADC to recover to within 1% of the full-scale range in response to an input voltage overload of 10% beyond the full-scale range. Submit Documentation Feedback 13 ADS5510 www.ti.com SLAS499 – JANUARY 2007 TYPICAL CHARACTERISTICS Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1 dBFS, sampling rate = 125 MSPS, DLL On, and 3-V differential clock, unless otherwise noted SPECTRAL PERFORMANCE (FFT for 20 MHZ input signal) SPECTRAL PERFORMANCE (FFT for 40 MHZ input signal) 0 0 SFDR = 83.8 dBc, SNR = 66.87 dBFS, SINAD = 66.67dBFS -40 -60 -80 -100 SFDR = 80.21 dBc, SNR = 66.84 dBFS, SINAD = 66.47 dBFS -20 Amplitude - dB Amplitude - dB -20 -120 -40 -60 -80 -100 -120 -140 -140 0 10 20 30 40 50 60 10 0 f - Frequency - MHz Figure 6. SPECTRAL PERFORMANCE (FFT for 70 MHZ input signal) SPECTRAL PERFORMANCE (FFT for 100 MHZ input signal) 50 60 0 -40 SFDR = 80.8 dBc, SNR = 67.47 dBFS, SINAD = 66.16 dBFS -20 Amplitude - dB Amplitude - dB 40 Figure 5. SFDR = 80.98 dBc, SNR = 66.76 dBFS, SINAD = 66.46 dBFS -20 -60 -80 -100 -120 -40 -60 -80 -100 -120 -140 -140 0 10 20 30 40 50 60 10 0 f - Frequency - MHz 20 30 40 Figure 7. Figure 8. SPECTRAL PERFORMANCE (FFT for 150 MHZ input signal) SPECTRAL PERFORMANCE (FFT for 170 MHZ input signal) 0 SFDR = 78.62 dBc, SNR = 66.15 dBFS, SINAD = 65.58 dBFS -20 60 -60 -80 -100 -120 50 60 SFDR = 69.93 dBc, SNR = 65.58 dBFS, SINAD = 63.41dBFS -20 Amplitude - dB -40 50 f - Frequency - MHz 0 Amplitude - dB 30 f - Frequency - MHz 0 -40 -60 -80 -100 -120 -140 -140 0 10 20 30 40 50 60 0 f - Frequency - MHz 10 20 30 40 f - Frequency - MHz Figure 9. 14 20 Figure 10. Submit Documentation Feedback ADS5510 www.ti.com SLAS499 – JANUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1 dBFS, sampling rate = 125 MSPS, DLL On, and 3-V differential clock, unless otherwise noted SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY TWO-TONE INTERMODULATION 90 0 fIN1 = 50.1 MHz, -7 dBFS, fIN2 = 46.1 MHz, -7 dBFS, SFDR = -90 dBFS, 2-Tone IMD, -85 dBFS -40 86 82 SFDR - dBc -60 -80 -100 78 74 70 66 -120 62 -140 20 30 40 50 0 60 50 SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY AC PERFORMANCE vs ANALOG SUPPLY VOLTAGE 74 FIN = 70 MHz 86 DRVDD = 3.3 V SFDR - dBc SNR − dBFS Figure 12. 89 70 66 200 50 100 150 fIN − Input Frequency − MHz 68 83 67 80 SNR 66 65 3.1 230 3.2 3.3 3.5 3.6 AVDD - Supply Voltage - V Figure 14. AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE AC PERFORMANCE vs TEMPERATURE 70 86 70 fIN = 70 MHz fIN = 70 MHz AVDD = 3.3 V 69 67 80 SFDR − dBc SFDR 69 83 SNR − dBFS 68 83 SFDR 80 68 77 67 SNR 77 74 3.1 3.4 Figure 13. 89 SFDR − dBc 69 SFDR 74 3 58 0 230 70 77 62 3.0 200 150 Figure 11. 78 86 100 fIN - Input Frequency - MHz f - Frequency - MHz SNR - dBFS 10 0 3.2 3.3 3.4 3.5 3.6 66 74 65 71 −40 SNR −15 10 SNR − dBFS Amplitude - dB -20 66 35 50 65 85 o TA − Free-Air Temperature − C DRVDD − Supply Voltage − V Figure 15. Figure 16. Submit Documentation Feedback 15 ADS5510 www.ti.com SLAS499 – JANUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1 dBFS, sampling rate = 125 MSPS, DLL On, and 3-V differential clock, unless otherwise noted AC PERFORMANCE vs INPUT AMPLITUDE AC PERFORMANCE vs CLOCK AMPLITUDE 105 76 69 66 65 65 55 SFDR (dBc) 45 SFDR - dBc 68 SNR (dBFS) 69 SFDR 72 68 fIN = 70 MHz 67 68 SNR 64 66 64 −10 0 0 0.2 0.4 AC PERFORMANCE vs CLOCK DUTY CYCLE OUTPUT NOISE vs HISTOGRAM 80 65 1.6 100 90 68 64 45 50 55 60 40 30 64 20 60 10 0 1023 SNR 68 60 50 65 Input Clock Duty Cycle − % Output Code Figure 19. Figure 20. POWER DISSIPATION vs SAMPLE RATE 1 0.9 Total Power - W 1027 72 70 1026 72 80 1024 76 Occurence − % SFDR SNR − dBFS 76 80 SFDR − dBc 1 Figure 18. fIN = 10 MHz fIN = 70 MHz 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 10 20 30 40 50 60 70 80 90 100 110 120 130 Sampling Frequency - MSPS Figure 21. 16 0.8 Figure 17. 84 40 0.6 Clock Amplitude - VPP Input Amplitude − dBFS 35 1.4 1030 −20 1029 −30 1.2 60 62 −40 1025 25 −50 1028 63 35 Submit Documentation Feedback SNR - dBFS SFDR (dBFS) 85 75 70 70 SNR − dBFS SFDR − dBc, dBFS 95 80 71 fIN = 70 MHz ADS5510 www.ti.com SLAS499 – JANUARY 2007 TYPICAL CHARACTERISTICS (continued) Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1 dBFS, and 3-V differential clock, unless otherwise noted DLL ON for FS > 80 MSPS DLL OFF for FS ≤ 80 MSPS fS - Sampling Frequency - MSPS 125 120 110 100 90 80 70 60 50 40 20 40 60 80 100 120 140 160 180 200 210 fIN - Input Frequency - MHz 72 76 74 78 80 82 86 84 88 90 SFDR - dBc Figure 22. SFDR Contour in dBc fS - Sampling Frequency - MSPS 125 120 110 100 90 80 70 60 50 40 20 40 60 80 100 120 140 160 180 200 210 fIN - Input Frequency - MHz 64.5 65 65.5 66 66.5 67 SNR - dBFS Figure 23. SNR Contour in dBFS Submit Documentation Feedback 17 ADS5510 www.ti.com SLAS499 – JANUARY 2007 APPLICATION INFORMATION THEORY OF OPERATION The ADS5510 is a low-power, 11-bit, 125 MSPS, CMOS, switched capacitor, pipeline ADC that operates from a single 3.3-V supply. The conversion process is initiated by a falling edge of the external input clock. Once the signal is captured by the input S&H, the input sample is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in a data latency of 17.5 clock cycles, after which the output data is available as a 11-bit parallel word, coded in either straight offset binary or binary two's complement format. INPUT CONFIGURATION The analog input for the ADS5510 consists of a differential sample-and-hold architecture implemented using the switched capacitor technique shown in Figure 24. S3a L1 R1a C1a INP S1a CP1 CP3 S2 R3 CA L2 R1b INM S1b C1b VINCM 1V CP2 CP4 L1, L2: 6 nH − 10 nH effective R1a, R1b: 5W − 8W C1a, C1b: 2.2 pF − 2.6 pF CP1, CP2: 2.5 pF − 3.5 pF CP3, CP4: 1.2 pF − 1.8 pF CA: 0.8 pF − 1.2 pF R3: 80 W − 120 W Swithches: S1a, S1b: On Resistance: 35 W − 50 W S2: On Resistance: 7.5 W − 15 W S3a, S3b: On Resistance: 40 W − 60 W All switches OFF Resistance: 10 GW A. All Switches are ON in sampling phase which is approximately one half of a clock period. Figure 24. Analog Input Stage 18 S3b Submit Documentation Feedback ADS5510 www.ti.com SLAS499 – JANUARY 2007 This differential input topology produces a high level of ac-performance for high sampling rates. It also results in a very high usable input bandwidth, especially important for high intermediate-frequency (IF) or undersampling applications. The ADS5510 requires each of the analog inputs (INP, INM) to be externally biased around the common-mode level of the internal circuitry (CM, pin 17). For a full-scale differential input, each of the differential lines of the input signal (pins 19 and 20) swings symmetrically between CM + 0.575 V and CM – 0.575 V. This means that each input is driven with a signal of up to CM ± 0.575 V, so that each input has a maximum differential signal of 1.15 VPP for a total differential input signal swing of 2.3 VPP. The maximum swing is determined by the two reference voltages, the top reference (REFP, pin 29), and the bottom reference (REFM, pin 30). The ADS5510 obtains optimum performance when the analog inputs are driven differentially. The circuit shown in Figure 25 illustrates one possible configuration using an RF transformer. R0 50Ω Z0 50Ω 25Ω INP 1:1 R 50Ω 25Ω AC Signal Source ADS5510 INM ADT1−1WT CM 10Ω 1nF 0.1µF Figure 25. Transformer Input to Convert Single-Ended Signal to Differential Signal The single-ended signal is fed to the primary winding of an RF transformer. Placing a 25-Ω resistor in series with INP and INM is recommended to dampen ringing due to ADC kickback. Since the input signal must be biased around the common-mode voltage of the internal circuitry, the common-mode voltage (VCM) from the ADS5510 is connected to the center-tap of the secondary winding. To ensure a steady low-noise VCM reference, best performance is attained when the CM output (pin 17) is filtered to ground with a 10-Ω series resistor and parallel 0.1-µF and 0.001-µF low-inductance capacitors, as illustrated in Figure 24. Output VCM (pin 17) is designed to directly drive the ADC input. When providing a custom CM level, be aware that the input structure of the ADC sinks a common-mode current in the order of 600 µA (300 µA per input). Equation 1 describes the dependency of the common-mode current and the sampling frequency: 600mA f S (in MSPS) 125 MSPS (1) Where: fS > 2 MSPS. This equation helps to design the output capability and impedance of the driving circuit accordingly. When it is necessary to buffer or apply a gain to the incoming analog signal, it is possible to combine single-ended operational amplifiers with an RF transformer, or to use a differential input/output amplifier without a transformer, to drive the input of the ADS5510. Texas Instruments offers a wide selection of single-ended operational amplifiers (including the THS3201, THS3202, OPA695, and OPA847) that can be selected depending on the application. An RF gain block amplifier, such as Texas Instruments THS9001, can also be used with an RF transformer for high input frequency applications. The THS4503 is a recommended differential input/output amplifier. Table 4 lists the recommended amplifiers. Submit Documentation Feedback 19 ADS5510 www.ti.com SLAS499 – JANUARY 2007 Table 4. Recommended Amplifiers to Drive the Input of the ADS5510 INPUT SIGNAL FREQUENCY RECOMMENDED AMPLIFIER TYPE OF AMPLIFIER DC to 20 MHz THS4503 Differential In/Out Amp No DC to 50 MHz OPA847 Operational Amp Yes DC to 100 MHz THS4509 Differential In/Out Amp No OPA695 Operational Amp Yes THS3201 Operational Amp Yes THS3202 Operational Amp Yes THS9001 RF Gain Block Yes 10 MHz to 120 MHz Over 100 MHz USE WITH TRANSFORMER? When using single-ended operational amplifiers (such as the THS3201, THS3202, OPA695, or OPA847) to provide gain, a three-amplifier circuit is recommended with one amplifier driving the primary of an RF transformer and one amplifier in each of the legs of the secondary driving the two differential inputs of the ADS5510. These three amplifier circuits minimize even-order harmonics. For high frequency inputs, an RF gain block amplifier can be used to drive a transformer primary; in this case, the transformer secondary connections can drive the input of the ADS5510 directly, as shown in Figure 25, or with the addition of the filter circuit shown in Figure 26. Figure 26 illustrates how RIN and CIN can be placed to isolate the signal source from the switching inputs of the ADC and to implement a low-pass RC filter to limit the input noise in the ADC. It is recommended that these components be included in the ADS5510 circuit layout when any of the amplifier circuits discussed previously are used. The components allow fine-tuning of the circuit performance. Any mismatch between the differential lines of the ADS5510 input produces a degradation in performance at high input frequencies, mainly characterized by an increase in the even-order harmonics. In this case, special care should be taken to keep as much electrical symmetry as possible between both inputs. Another possible configuration for lower-frequency signals is the use of differential input/output amplifiers that can simplify the driver circuit for applications requiring dc-coupling of the input. Flexible in their configurations (see Figure 27), such amplifiers can be used for single-ended-to-differential conversion signal amplification. +5V −5V RS 100Ω VIN 0.1µF OPA695 1000pF R1 400Ω R2 57.5Ω RIN 1:1 INP RT 100Ω RIN CIN ADS5510 INM CM 10Ω AV = 8V/V (18dB) 0.1µF Figure 26. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer 20 Submit Documentation Feedback ADS5510 www.ti.com SLAS499 – JANUARY 2007 RS RG RF +5V RT +3.3V 10mF 0.1mF RIN VOCM 1mF INP ADS5510 11-Bit / 125MSPS INM CM RIN THS4503 10mF 0.1mF 10 W RG -5V RF 0.1mF Figure 27. Using the THS4503 with the ADS5510 POWER-SUPPLY SEQUENCE The preferred power-up sequence is to ramp AVDD first, followed by DRVDD, including a simultaneous ramp of AVDD and DRVDD. In the event that DRVDD ramps up first in the system, care must be taken to ensure that AVDD ramps up within 10 ms. Optionally, it is recommended to put a 2-kΩ resistor from REFP (pin 29) to AVDD as shown in Figure 28. This helps to make the device more robust to power supply ramp-up timings. 28 AVDD 29 REFP 2 kW 1W 1 mF Figure 28. POWER-DOWN The device enters power-down in one of two ways: either by reducing the clock speed or by setting the PDN bit throughout the serial programming interface. Using the reduced clock speed, power-down may be initiated for clock frequency below 2 MSPS. The exact frequency at which the power down occurs varies from device to device. Using the serial interface PDN bit to power down the device places the outputs in a high-impedance state and only the internal reference remains on to reduce the power-up time. The power-down mode reduces power dissipation to approximately 180 mW. Submit Documentation Feedback 21 ADS5510 www.ti.com SLAS499 – JANUARY 2007 REFERENCE CIRCUIT The ADS5510 has built-in internal reference generation, requiring no external circuitry on the printed circuit board (PCB). For optimum performance, it is best to connect both REFP and REFM to ground with a 1-µF decoupling capacitor (the 1-Ω resistor shown in Figure 29 is optional). In addition, an external 56.2-kΩ resistor should be connected from IREF (pin 31) to AGND to set the proper current for the operation of the ADC, as shown in Figure 29. No capacitor should be connected between pin 31 and ground; only the 56.2-kΩ resistor should be used. 1W 29 R EF P 30 R EF M 31 IR EF 1 mF 1W 1 mF 56.2 kW Figure 29. REFP, REFM, and IREF Connections for Optimum Performance CLOCK INPUT The ADS5510 clock input can be driven with either a differential clock signal or a single-ended clock input, with little or no difference in performance between both configurations. The common-mode voltage of the clock inputs is set internally to CM (pin 17) using internal 5-kΩ resistors that connect CLKP (pin 10) and CLKM (pin 11) to CM (pin 17), as shown in Figure 30. CM CM 5 kW 5 kW CLKM CLKP 6 pF 3 pF 3 pF Figure 30. Clock Inputs When driven with a single-ended CMOS clock input, it is best to connect CLKM (pin 11) to ground with a 0.01-µF capacitor, while CLKP is ac-coupled with a 0.01-µF capacitor to the clock source, as shown in Figure 31. 22 Submit Documentation Feedback ADS5510 www.ti.com SLAS499 – JANUARY 2007 Square Wave or Sine Wave (3VPP) 0.01µF CLKP ADS5510 CLKM 0.01µF Figure 31. AC-Coupled, Single-Ended Clock Input The ADS5510 clock input can also be driven differentially, reducing susceptibility to common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with 0.01-µF capacitors, as shown in Figure 32. 0.01µF CLKP Differential Square Wave or Sine Wave (3VPP) ADS5510 0.01µF CLKM Figure 32. AC-Coupled, Differential Clock Input For high input frequency sampling, it is recommended to use a clock source with low jitter. Additionally, the internal ADC core uses both edges of the clock for the conversion process. This means that, ideally, a 50% duty cycle should be provided. Figure 19 shows the performance variation of the ADC versus clock duty cycle. Bandpass filtering of the source can help produce a 50% duty cycle clock and reduce the effect of jitter. When using a sinusoidal clock, the clock jitter further improves as the amplitude is increased. In that sense, using a differential clock allows for the use of larger amplitudes without exceeding the supply rails and absolute maximum ratings of the ADC clock input. Figure 18 shows the performance variation of the device versus input clock amplitude. For detailed clocking schemes based on transformer or PECL-level clocks, see the ADS55xxEVM User's Guide (SLWU010), available for download from www.ti.com. INTERNAL DLL In order to obtain the fastest sampling rates achievable with the ADS5510, the device uses an internal digital delay lock loop (DLL). Nevertheless, the limited frequency range of operation of DLL degrades the performance at clock frequencies below 60 MSPS. In order to operate the device below 60 MSPS, the internal DLL must be shut off using the DLL OFF mode described in the Serial Interface Programming section. The Typical Performance Curves show the performance obtained in both modes of operation: DLL ON (default) and DLL OFF. In either of the two modes, the device enters power-down mode if no clock or slow clock is provided. The limit of the clock frequency where the device functions properly with default settings is ensured to be over 2 MHz. OUTPUT INFORMATION The ADC provides 11 data outputs (D10 to D0, with D10 being the MSB and D0 the LSB), a data-ready signal (CLKOUT, pin 43), and an out-of-range indicator (OVR, pin 64) that equals 1 when the output reaches the full-scale limits. Two different output formats (straight offset binary or two's complement) and two different output clock polarities (latching output data on rising or falling edge of the output clock) can be selected by setting DFS (pin 40) to one of four different voltages. Table 3 details the four modes. In addition, output enable control (OE, pin 41, active high) is provided to put the outputs into a high-impedance state. Submit Documentation Feedback 23 ADS5510 www.ti.com SLAS499 – JANUARY 2007 In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive overdrive, the output code is 0x7FF in straight offset binary output format and 0x3FF in two's complement output format. For a negative input overdrive, the output code is 0x000 in straight offset binary output format and 0x400 in two's complement output format. These outputs to an overdrive signal are ensured through design and characterization. The output circuitry of the ADS5510, by design, minimizes the noise produced by the data switching transients, and, in particular, its coupling to the ADC analog circuitry. Output D1 (pin 51) senses the load capacitance and adjusts the drive capability of all the output pins of the ADC to maintain the same output slew rate described in the timing diagram of Figure 1. Care should be taken to ensure that all output lines (including CLKOUT) have nearly the same load as D1 (pin 51). This circuit also reduces the sensitivity of the output timing versus supply voltage or temperature. Placing external resistors in series with the outputs is not recommended. The timing characteristics of the digital outputs change for sampling rates below the 125 MSPS maximum sampling frequency. Table 5 and Table 6 show the setup, hold, input clock to output data delays, and rise and fall times for different sampling frequencies with the DLL on and off, respectively. Table 7 and Table 8 show the rise and fall times at additional sampling frequencies with DLL on and off, respectively. To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay, td, that results in the desired setup or hold time. Use either Equation 2or Equation 3 to calculate the value of td. Desired setup time = td – tSTART Desired hold time = tEND – td Table 5. Timing Characteristics at Additional Sampling Frequencies (DLL ON) tSETUP (ns) fS (MSPS) MIN TYP 105 2.4 93 3.2 80 65 tHOLD (ns) MAX MIN TYP 3.1 2.2 2.6 4.6 2.3 3.7 2.8 3.7 2.8 3.8 4.6 3.6 tSTART (ns) MAX MIN tEND (ns) TYP MAX MIN TYP 1.7 2.6 5.8 3.3 0.5 1.7 4.1 –0.5 0.8 tr (ns) MAX MIN tf (ns) TYP MAX 7.3 4.4 5.3 7.9 5.3 8.5 MIN TYP MAX 5.1 3.3 3.8 5.8 6.6 4.4 5.3 6.7 7.2 5.5 6.4 Table 6. Timing Characteristics at Additional Sampling Frequencies (DLL OFF) tSETUP (ns) fS (MSPS) MIN TYP 80 3.2 4.2 65 4.3 5.7 40 8.5 11 20 17 25.7 tHOLD (ns) MAX MIN TYP 1.8 tSTART (ns) MAX MIN tEND (ns) TYP MAX MIN TYP 3 3.8 5 8.4 2 3 2.8 4.5 2.6 3.5 –1 1.5 2.5 4.7 –9.8 tr (ns) MAX TYP MAX 11 5.8 6.6 4.4 5.3 8.3 11.8 6.6 7.2 5.5 6.4 8.9 14.5 7.5 8 7.3 7.8 2 9.5 21.6 7.5 8 7.6 8 50 82 75 150 27 51 4 6.5 -30 -3 11.5 31 2 284 370 8 19 185 320 515 576 MIN tf (ns) TYP 10 MAX MIN Table 7. Timing Characteristics at Additional Sampling Frequencies (DLL ON) fS (MSPS) CLKOUT, Rise Time tr (ns) MIN 24 CLKOUT Jitter, Peak-to-Peak tJIT (ps) CLKOUT, Fall Time tf (ns) MIN MIN Input-to-Output Clock Delay tPDI (ns) TYP MAX TYP MAX TYP MAX MIN TYP MAX 105 2 2.2 1.7 1.8 175 250 4 4.7 5.5 80 2.5 2.8 2.1 2.3 210 315 3.7 4.3 5.1 65 3.1 3.5 2.6 2.9 260 380 3.5 4.1 4.8 Submit Documentation Feedback ADS5510 www.ti.com SLAS499 – JANUARY 2007 Table 8. Timing Characteristics at Additional Sampling Frequencies (DLL OFF) fS (MSPS) CLKOUT, Rise Time tr (ns) MIN CLKOUT Jitter, Peak-to-Peak tJIT (ps) CLKOUT, Fall Time tf (ns) MIN MIN Input-to-Output Clock Delay tPDI (ns) TYP MAX TYP MAX TYP MAX MIN TYP MAX 80 2.5 2.8 2.1 2.3 210 315 7.1 8 8.9 65 3.1 3.5 2.6 2.9 260 380 7.8 8.5 9.4 40 4.8 5.3 4 4.4 445 650 9.5 10.4 11.4 20 8.3 9.5 7.6 8.2 800 1200 13 15.5 18 16 20.7 25.5 31 52 36 65 2610 4400 537 551 567 10 2 SERIAL PROGRAMMING INTERFACE The ADS5510 has internal registers for the programming of some of the modes described in the previous sections. The registers should be reset after power-up by applying a 2 µs (minimum) high pulse on RESET (pin 35); this also resets the entire ADC and sets the data outputs to low. This pin has a 200-kΩ internal pullup resistor to AVDD. The programming is done through a three-wire interface. The timing diagram and serial register setting in the Serial Programing Interface section describe the programming of this register. Table 2 shows the different modes and the bit values to be written to the register to enable them. Note that some of these modes may modify the standard operation of the device and possibly vary the performance with respect to the typical data shown in this data sheet. Applying a RESET signal is must to set the internal registers to their default states for normal operation. If the hardware RESET function is not used in the system, the RESET pin must be tied to ground and it is necessary to write the default values to the internal registers through the serial programming interface. The registers must be written in the following order. Write 9000h (Address 9, Data 000) Write A000h (Address A, Data 000) Write B000h (Address B, Data 000) Write C000h (Address C, Data 000) Write D000h (Address D, Data 000) Write E000h (Address E, Data 804) Write 0000h (Address 0, Data 000) Write 1000h (Address 1, Data 000) Write F000h (Address F, Data 000) NOTE: This procedure is only required if a RESET pulse is not provided to the device. Submit Documentation Feedback 25 ADS5510 www.ti.com SLAS499 – JANUARY 2007 PowerPAD PACKAGE The PowerPAD package is a thermally enhanced standard size IC package designed to eliminate the use of bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using standard printed circuit board (PCB) assembly techniques and can be removed and replaced using standard repair procedures. The PowerPAD package is designed so that the lead frame die pad (or thermal pad) is exposed on the bottom of the IC. This provides a low thermal resistance path between the die and the exterior of the package. The thermal pad on the bottom of the IC can then be soldered directly to the printed circuit board (PCB), using the PCB as a heatsink. Assembly Process 1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as illustrated in the Mechanical Data section. The recommended thermal pad dimension is 8 mm x 8 mm. 2. Place a 5-by-5 array of thermal vias in the thermal pad area. These holes should be 13 mils in diameter. The small size prevents wicking of the solder through the holes. 3. It is recommended to place a small number of 25 mil diameter holes under the package, but outside the thermal pad area to provide an additional heat path. 4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as a ground plane). 5. Do not use the typical web or spoke via connection pattern when connecting the thermal vias to the ground plane. The spoke pattern increases the thermal resistance to the ground plane. 6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area. 7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking. 8. Apply solder paste to the exposed thermal pad area and all of the package terminals. For more detailed information regarding the PowerPAD package and its thermal properties, see either the application brief SLMA004B (PowerPAD Made Easy) or technical brief SLMA002 (PowerPAD Thermally Enhanced Package). 26 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 30-Jan-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS5510IPAP ACTIVE HTQFP PAP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS5510IPAPR ACTIVE HTQFP PAP 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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