ADS8504 SLAS434 – JUNE 2005 12-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • 250-kHz Sampling Rate Standard ±10-V Input Range 73-dB SINAD With 45-kHz Input ±0.45 LSB Max INL ±0.45 LSB Max DNL 12 Bit No Missing Code ±1 LSB Bipolar Zero Errors ±0.4 PPM/°C Bipolar Zero Error Drift Single 5-V Supply Operation Pin-Compatible With ADS7804/05 (Low Speed) and 16-Bit ADS8505 Uses Internal or External Reference Full Parallel Data Output 70-mW Typ Power Dissipation at 250 KSPS 28-Pin SOIC Package Industrial Process Control Data Acquisition Systems Digital Signal Processing Medical Equipment Instrumentation DESCRIPTION The ADS8504 is a complete 12-bit sampling A/D converter using state-of-the-art CMOS structures. It contains a complete 12-bit, capacitor-based, SAR A/D with S/H, reference, clock, interface for microprocessor use, and 3-state output drivers. The ADS8504 is specified at a 250-kHz sampling rate over the full temperature range. Precision resistors provide an industry standard ±10-V input range, while the innovative design allows operation from a single +5-V supply, with power dissipation under 100 mW. The ADS8504 is available in a 28-pin SOIC package and is fully specified for operation over the industrial -40°C to 85°C temperature range. Clock Successive Approximation Register and Control Logic R/C CS BYTE BUSY CDAC 9.8 kΩ ± 10 V Input 5 kΩ 2 kΩ Comparator Output Latches and Three State Drivers Three State Parallel Data Bus CAP Buffer Internal +2.5 V Ref 4 kΩ REF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated ADS8504 www.ti.com SLAS434 – JUNE 2005 PACKAGE/ORDERING INFORMATION (1) PRODUCT MINIMUM RELATIVE ACCURACY (LSB) NO MISSING CODE MINIMUM SINAD (dB) SPECIFICATION TEMPERATURE RANGE PACKAGE LEAD PACKAGE DESIGNATOR ADS8504IB ±0.45 12 72 -40°C to 85°C SO-28 DW (1) ORDERING NUMBER ADS8504IBDW ADS8504IBDWR TRANSPORT MEDIA, QTY Tube, 20 Tape and Reel, 1000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) (2) ADS8504 Analog inputs VIN Ground voltage differences ±25V CAP +VANA + 0.3 V to AGND2 - 0.3 V REF Indefinite short to AGND2, momentary short to VANA DGND, AGND1, AGND2 ±0.3 V VANA 6V VDIG to VANA 0.3 V VDIG 6V Digital inputs -0.3 V to +VDIG + 0.3 V Maximum junction temperature 165°C Internal power dissipation 825 mW Lead temperature (soldering, 1,6mm from case, 10 seconds) (1) (2) 260°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. ELECTRICAL CHARACTERISTICS TA = -40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP Resolution MAX 12 UNIT Bits ANALOG INPUT Voltage range ±10 V Impedance 11.5 kΩ 50 pF Capacitance THROUGHPUT SPEED Conversion cycle Acquire and convert Throughput rate 4 250 µs kHz DC ACCURACY INL Integral linearity error -0.45 0.45 LSB (1) DNL Differentiall linearity error -0.45 0.45 LSB (1) No missing codes Transition (1) (2) (3) (4) 2 12 noise (2) Bits 0.1 Full-scale error (3) (4) Int. Ref. Full-scale error drift Int. Ref. -0.25 LSB 0.25 ±7 %FSR ppm/°C LSB means least significant bit. For the 12-bit, ±10-V input ADS8504, one LSB is 4.88 mV. Typical rms noise at worst case transitions and temperatures. As measured with fixed resistors shown in Figure 23. Adjustable to zero with external potentiometer. Full-scale error is the worst case of -full-scale or +full-scale deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. ADS8504 www.ti.com SLAS434 – JUNE 2005 ELECTRICAL CHARACTERISTICS (continued) TA = -40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise noted) PARAMETER TEST CONDITIONS Full-scale error (3) (4) Ext. 2.5-V Ref. Full-scale error drift Ext. 2.5-V Ref. Bipolar zero error (3) MIN MAX UNIT 0.25 %FSR ±2 -1 Bipolar zero error drift Power supply sensitivity (VDIG = VANA = VD) TYP -0.25 ppm/°C 1 ±0.4 +4.75 V < VD < +5.25 V -0.5 LSB ppm/°C 0.5 LSB AC ACCURACY SFDR Spurious-free dynamic range fI = 45 kHz THD Total harmonic distortion fI = 45 kHz SINAD Signal-to-(noise+distortion) SNR Signal-to-noise ratio Full-power fI = 45 kHz 86 -95 72 –60-dB Input fI = 45 kHz 72 bandwidth (6) dB (5) 94 -86 dB 73 dB 32 dB 73 dB 500 kHz SAMPLING DYNAMICS Aperture delay Transient response 5 FS Step ns 2 Overvoltage recovery (7) 150 µs ns REFERENCE Internal reference voltage 2.48 2.5 2.52 V Internal reference source current (must use external buffer) 1 µA Internal reference drift 8 ppm/°C External reference voltage range for specified linearity External reference current drain 2.3 Ext. 2.5-V Ref. 2.5 2.7 V 100 µA DIGITAL INPUTS Logic levels VIL Low-level input voltage -0.3 0.8 V VIH High-level input voltage 2.0 VDIG +0.3 V V IIL Low-level input current ±10 µA IIH High-level input current ±10 µA 0.4 V DIGITAL OUTPUTS Data format (Parallel 12-bits) Data coding (Binary 2's complement) VOL Low-level output voltage ISINK = 1.6 mA VOH High-level output voltage ISOURCE = 500 µA Leakage current Hi-Z state, VOUT = 0 V to VDIG ±5 µA Output capacitance Hi-Z state 15 pF Bus access timing 83 ns Bus relinquish timing 83 ns 4 V DIGITAL TIMING (5) (6) (7) All specifications in dB are referred to a full-scale ±10-V input. Full-power bandwidth is defined as the full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB, or 10 bits of accuracy. Recovers to specified performance after 2 x FS input overvoltage. 3 ADS8504 www.ti.com SLAS434 – JUNE 2005 ELECTRICAL CHARACTERISTICS (continued) TA = -40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4.75 5 5.25 V 4.75 5 5.25 POWER SUPPLIES VDIG Digital input voltage VANA Analog input voltage IDIG Digital input current IANA Analog input current Power dissipation Must be ≤ VANA fS = 250 kHz V 4 mA 10 mA 70 100 mW TEMPERATURE RANGE Specified performance -40 85 °C Derated performance (8) -55 125 °C Storage -65 150 °C THERMAL RESISTANCE (ΘJA) SO (8) 46 The internal reference may not be started correctly beyond the industrial temperature range (-40°C to 85°C), therefore use of an external reference is recommended. DEVICE INFORMATION DW PACKAGE (TOP VIEW) VIN 1 AGND1 2 28 VDIG 27 VANA REF 3 26 BUSY CAP 4 25 CS AGND2 5 D11 (MSB) 6 4 °C/W 24 R/C 23 BYTE D10 7 22 DZ D9 8 21 DZ D8 9 20 DZ D7 10 19 DZ D6 11 18 D0 (LSB) D5 12 17 D1 D4 13 16 D2 DGND 14 15 D3 ADS8504 www.ti.com SLAS434 – JUNE 2005 DEVICE INFORMATION (continued) Terminal Functions TERMINAL NAME DW NO. DIGITAL I/O DESCRIPTION AGND1 2 Analog ground. Used internally as ground reference point. AGND2 5 Analog ground. BUSY 26 O At the start of a conversion, BUSY goes low and stays low until the conversion is completed and the digital outputs have been updated. BYTE 23 I Selects 8 most significant bits (low) or 8 least significant bits (high). CAP 4 CS 25 Reference buffer capacitor. 2.2-µF tantalum capacitor to ground. DGND 14 D11 (MSB) 6 O Data bit 11. Most significant bit (MSB) of conversion results. Hi-Z state when CS is high, or when R/C is low. D10 7 O Data bit 10. Hi-Z state when CS is high, or when R/C is low. D9 8 O Data bit 9. Hi-Z state when CS is high, or when R/C is low. D8 9 O Data bit 8. Hi-Z state when CS is high, or when R/C is low. D7 10 O Data bit 7. Hi-Z state when CS is high, or when R/C is low. D6 11 O Data bit 6. Hi-Z state when CS is high, or when R/C is low. D5 12 O Data bit 5. Hi-Z state when CS is high, or when R/C is low. D4 13 O Data bit 4. Hi-Z state when CS is high, or when R/C is low. D3 15 O Data bit 3. Hi-Z state when CS is high, or when R/C is low. D2 16 O Data bit 2. Hi-Z state when CS is high, or when R/C is low. D1 17 O Data bit 1. Hi-Z state when CS is high, or when R/C is low. D0 (LSB) 18 O Data bit 0. Least significant bit (LSB) of conversion results. Hi-Z state when CS is high, or when R/C is low. DZ 19 O Low when CS low, R/C high. Hi-Z state when CS is high, or when R/C is low. DZ 20 O Low when CS low, R/C high. Hi-Z state when CS is high, or when R/C is low. DZ 21 O Low when CS low, R/C high. Hi-Z state when CS is high, or when R/C is low. DZ 22 O Low when CS low, R/C high. Hi-Z state when CS is high, or when R/C is low. R/C 24 I With CS low and BUSY high, a falling edge on R/C initiates a new conversion. With CS low, a rising edge on R/C enables the parallel output. REF 3 Reference input/output. 2.2-µF tantalum capacitor to ground. VANA 27 Analog supply input. Nominally +5 V. Decouple to ground with 0.1-µF ceramic and 10-µF tantalum capacitors. VDIG 28 Digital supply input. Nominally +5 V. Connect directly to pin 27. Must be ≤ VANA. VIN 1 Analog input. I Internally ORed with R/C. If R/C low, a falling edge on CS initiates a new conversion. Digital ground. 5 ADS8504 www.ti.com SLAS434 – JUNE 2005 Typical Characteristics TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE 110 90 80 70 −20 0 20 40 60 −95 −90 −85 −80 −70 −40 80 50 fi = 45 kHz −20 0 20 40 60 40 −40 80 −20 0 20 40 60 Figure 2. Figure 3. SIGNAL-TO-NOISE AND DISTORTION vs FREE-AIR TEMPERATURE SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY 60 50 SINAD − Signal-to-Noise and Distortion − dB 80 70 75 70 65 60 55 fi = 45 kHz 50 −20 0 20 40 60 80 1 10 100 1000 80 75 70 65 60 55 50 1 fi − Input Frequency − kHz TA − Free-Air-Temperature − C 10 100 1000 fi − Input Frequency − kHz Figure 4. Figure 5. Figure 6. SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY BIPOLAR ZERO ERROR vs FREE-AIR TEMPERATURE 90 80 70 60 50 −100 5 −90 4 BPZ − Bipolar Zero Error −mV THD − Total Harmonic Distortion − dB 100 −80 −70 −60 −50 −40 −30 −20 −10 10 100 fi − Input Frequency − kHz Figure 7. 1000 3 2 1 0 −1 −2 −3 −4 0 1 80 TA − Free-Air-Temperature − C Figure 1. SNR − Signal-to-Noise − dB SINAD − Signal-to-Noise and Distortion − dB 60 TA − Free-Air-Temperature − C 80 40 −40 70 −75 TA − Free-Air-Temperature − C SFDR − Spurious Free Dynamic Range − dB 80 SNR − Signal-to-Noise − dB 100 −40 6 SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE −100 fi = 45 kHz THD − Total Harmonic Distortion − dB SFDR − Spurious Free Dynamic Range − dB SPURIOUS FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 1 10 100 fi − Input Frequency − kHz Figure 8. 1000 −5 −40 −20 0 20 40 60 TA− Free-Air Temperature − C Figure 9. 80 ADS8504 www.ti.com SLAS434 – JUNE 2005 Typical Characteristics (continued) POSITIVE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 20 0.2 19 0.15 0.1 0.05 0 −0.05 −0.1 −0.15 0.15 0.1 0.05 0 −0.05 −0.1 −20 0 20 40 60 80 17 16 15 14 13 11 −0.25 −40 TA− Free-Air Temperature − C 10 −20 0 20 40 60 −40 80 −20 0 20 40 60 80 TA− Free-Air Temperature − C TA − Free-Air Temperature − C Figure 10. Figure 11. Figure 12. INL 0.5 fs = 250 KSPS 0.4 0.3 0.2 INL − LSBs −40 18 12 −0.15 −0.2 −0.2 −0.25 I DD − Supply Current − mA 0.25 0.2 Positive Full−Scale Error − %FSR 0.25 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 0 512 1024 1536 2048 2560 3072 3584 4096 3072 3584 4096 Code (Binary 2’s Complement in Decimal) Figure 13. DNL 0.5 fs = 250 KSPS 0.4 0.3 0.2 DNL − LSBs Negative Full−Scale Error − FSR% NEGATIVE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 0 512 1024 1536 2048 2560 Code (Binary 2’s Complement in Decimal) Figure 14. 7 ADS8504 www.ti.com SLAS434 – JUNE 2005 Typical Characteristics (continued) FFT 20 8192 Points fs = 250 KSPS fi = 1 kHz, 0dB SINAD = 73.47 dB THD = −94.03 dB 0 Amplitude − dB −20 −40 −60 −80 −100 −120 −140 −160 0 25 50 75 100 125 75 100 125 f − Frequency − Hz Figure 15. FFT 20 8192 Points fs = 250 KSPS fi = 45 kHz, 0dB SINAD = 73.62 dB THD = −94.03 dB 0 Amplitude − dB −20 −40 −60 −80 −100 −120 −140 −160 0 25 50 f − Frequency − Hz Figure 16. BASIC OPERATION Figure 17 shows a basic circuit to operate the ADS8504 with a full parallel data output. Taking R/C (pin 24) low for a minimum of 40 ns (1.75 µs max if BUSY is used to latch the data) initiates a conversion. BUSY (pin 26) goes low and stays low until the conversion is completed and the output registers are updated. Data is output in binary 2's complement with the MSB on pin 6. BUSY going high can be used to latch the data. All convert commands are ignored while BUSY is low. The ADS8504 begins tracking the input signal at the end of the conversion. Allowing 4 µs between convert commands assures accurate acquisition of a new signal. The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the Calibration section). STARTING A CONVERSION The combination of CS (pin 25) and R/C (pin 24) low for a minimum of 40 ns immediately puts the sample/hold of the ADS8504 in the hold state and starts conversion n. BUSY (pin 26) goes low and stays low until conversion n is completed and the internal output register has been updated. All new convert commands during BUSY low are ignored. CS and/or R/C must go high before BUSY goes high or a new conversion is initiated without sufficient time to acquire a new signal. The ADS8504 begins tracking the input signal at the end of the conversion. Allowing 4 µs between convert commands assures accurate acquisition of a new signal. Refer to Table 1 for a summary of CS, R/C, and BUSY states and Figure 19, Figure 20, and Figure 21 for the timing diagrams. 8 ADS8504 www.ti.com SLAS434 – JUNE 2005 BASIC OPERATION (continued) CS and R/C are internally ORed and level triggered. There is not a requirement which input goes low first when initiating a conversion. If, however, it is critical that CS or R/C initiates conversion n, be sure the less critical input is low at least 10 ns prior to the initiating input. To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. The parallel output becomes active whenever R/C goes high. Refer to the READING DATA section. Table 1. Control Line Functions for Read and Convert (1) CS R/C BUSY 1 X X None. Databus is in Hi-Z state. OPERATION ↓ 0 1 Initiates conversion n. Databus remains in Hi-Z state. 0 ↓ 1 Initiates conversion n. Databus enters Hi-Z state. 0 1 ↑ Conversion n completed. Valid data from conversion n on the databus. ↓ 1 1 Enables databus with valid data from conversion n. ↓ 1 0 Enables databus with valid data from conversion n-1 (1). Conversion n in progress. 0 ↑ 0 Enables databus with valid data from conversion n-1 (1). Conversion n in progress. 0 0 ↑ New conversion initiated without acquisition of a new signal. Data is invalid. CS and/or R/C must be high when BUSY goes high. X X 0 New convert commands ignored. Conversion n in progress. See Figure 19 and Figure 20 for constraints on data valid from conversion n-1. 200 Ω 1 28 2 27 3 26 4 25 5 24 D11 (MSB) 6 23 D10 7 D9 33.2 kΩ + 2.2 µF 2.2 µF + + 0.1 µF +5V + 10 µF BUSY Convert Pulse R/C 22 DZ Low 8 21 DZ Low D8 9 20 DZ Low D7 10 19 DZ Low D6 11 18 D0 (LSB) D5 12 17 D1 D4 13 16 D2 14 15 D3 ADS8504 40 ns Min Figure 17. Basic Operation READING DATA The ADS8504 outputs full or byte-reading parallel data in binary 2's complement data output format. The parallel output is active when R/C (pin 24) is high and CS (pin 25) is low. Any other combination of CS and R/C 3-states the parallel output. Valid conversion data can be read in a full parallel, 12-bit word or two 8-bit bytes on pins 6-13 and pins 15-22. BYTE (pin 23) can be toggled to read both bytes within one conversion cycle. Refer to Table 2 for ideal output codes and Figure 18 for bit locations relative to the state of BYTE. 9 ADS8504 www.ti.com SLAS434 – JUNE 2005 Table 2. Ideal Input Voltages and Output Codes DESCRIPTION ANALOG INPUT Full-scale range ±10 V DIGITAL OUTPUT BINARY 2's COMPLEMENT BINARY CODE HEX CODE 7FF Least significant bit (LSB) 4.88 mV Full scale (10 V-1 LSB) 9.99512 V 0111 1111 1111 Midscale 0V 0000 0000 0000 000 One LSB below midscale -4.88 mV 1111 1111 1111 FFF -Full scale -10 V 1000 0000 0000 800 PARALLEL OUTPUT (After a Conversion) After conversion n is completed and the output registers have been updated, BUSY (pin 26) goes high. Valid data from conversion n is available on D11-D0 (pins 6-13 and 15-18). BUSY going high can be used to latch the data. Refer to Table 3 and Figure 19, Figure 20, and Figure 21 for timing specifications. PARALLEL OUTPUT (During a Conversion) After conversion n has been initiated, valid data from conversion n-1 can be read and is valid up to t2 (2.2 µs typ) after the start of conversion n. Do not attempt to read data from t2 (2.2 µs typ) after the start of conversion n until BUSY (pin 26) goes high; this may result in reading invalid data. Refer to Table 3 and Figure 19, Figure 20, and Figure 21 for timing specifications. Note: For the best possible performance, data should not be read during a conversion. The switching noise of the asynchronous data transfer can cause digital feedthrough degrading the converter's performance. The number of control lines can be reduced by tying CS low while using the falling edge of R/C to initiate conversions and the rising edge of R/C to activate the output mode of the converter. See Figure 19. Table 3. Conversion Timing SYMBOL MIN TYP 40 MAX UNITS tw1 Pulse duration, convert 1750 ns ta Access time, data valid after R/C low 2.2 3.2 µs tpd Propagation delay time, BUSY from R/C low 15 25 ns tw2 Pulse duration, BUSY low 2.2 µs td1 Delay time, BUSY after end of conversion 5 td2 Delay time, aperture 5 tconv Conversion time tacq Acquisition time 1.8 tdis Disable time, bus 10 30 td3 Delay time, BUSY after data valid 35 50 tv Valid time, previous data remains valid after R/C low 1.5 2 tconv + tacq 10 DESCRIPTION Setup time, R/C to CS ns 2.2 µs µs Throughput time tsu ns 83 ns ns µs 4 10 µs ns tc Cycle time between conversions 4 ten Enable time, bus 10 30 83 µs ns td4 Delay time, BYTE 5 10 30 ns ADS8504 www.ti.com SLAS434 – JUNE 2005 BYTE LOW BYTE HIGH +5 V Bit 11 (MSB) 6 23 Bit 3 6 22 Low Bit 2 7 Bit 9 8 21 Low Bit 1 8 21 Bit 5 Bit 8 9 20 Low Bit 0 9 20 Bit 6 Bit 7 10 19 Low Low 10 19 Bit 7 Bit 6 11 18 Bit 0 (LSB) Low 11 18 Bit 8 Bit 5 12 17 Bit 1 Low 12 17 Bit 9 Bit 4 13 16 Bit 2 Low 13 16 Bit 10 14 15 Bit 3 14 Bit 10 7 ADS8504 23 22 Bit 4 ADS8504 15 Bit 11 (MSB) Figure 18. Bit Locations Relative to State of BYTE (Pin 23) tw1 R/C tc ta1 tw2 BUSY tpd td2 td1 Acquire MODE Convert Acquire tconv DATA BUS Previous Data Valid Previous Data Valid Hi−Z Convert tacq Not Valid Data Valid Hi−Z Data Valid td3 tdis tv Figure 19. Conversion Timing with Outputs Enabled after Conversion (CS Tied Low) tsu tsu tsu tsu R/C tw1 CS tpd tw2 BUSY td2 MODE Acquire Convert Acquire tconv DATA BUS Hi−Z State Data Valid ten Hi−Z State tdis Figure 20. Using CS to Control Conversion and Read Timing 11 ADS8504 www.ti.com SLAS434 – JUNE 2005 tsu tsu R/C CS BYTE Pins 6 − 13 Hi−Z Pins 15 − 18 Hi−Z High Byte Low Byte ten td4 Low Byte High Byte Hi−Z tdis Hi−Z Figure 21. Using CS and BYTE to Control Data Bus INPUT RANGES The ADS8504 offers a standard ±10-V input range. Figure 23 shows the necessary circuit connections for the ADS8504 with and without hardware trim. Offset and full-scale error specifications are tested and specified with the fixed resistors shown in Figure 23(b). Full-scale error includes offset and gain errors measured at both +FS and -FS. Adjustments for offset and gain are described in the Calibration section of this data sheet. The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the Calibration section). The nominal input impedance of 11.5 kΩ results from the combination of the internal resistor network shown on the front page of the product data sheet and the external resistors. The input resistor divider network provides inherent overvoltage protection assured to at least ±25 V. The 1% resistors used for the external circuitry do not compromise the accuracy or drift of the converter. They have little influence relative to the internal resistors, and tighter tolerances are not required. The input signal must be referenced to AGND1. This will minimize the ground loop problem typical to analog designs. The analog input should be driven by a low impedance source. A typical driving circuit using OPA627 or OPA132 is shown in Figure 6. +15V 2.2 F 22 pF ADS8504 200 100 nF GND VIN 2 k Pin 7 2 k Vin Pin 2 22 pF Pin3 Pin 1 − OPA 627 or OPA 132 + REF 2.2 F 33.2 k Pin 6 AGND1 Pin4 GND CAP 2.2 F GND 100 nF 2.2 F DGND GND AGND2 −15 V GND Figure 22. Typical Driving Circuitry (±10 V, No Trim) 12 GND ADS8504 www.ti.com SLAS434 – JUNE 2005 APPLICATION INFORMATION CALIBRATION The ADS8504 can be trimmed in hardware or software. The offset should be trimmed before the gain since the offset directly affects the gain. To achieve optimum performance, several iterations may be required. Hardware Calibration To calibrate the offset and gain of the ADS8504, install the proper resistors and potentiometers as shown in Figure 23(a). Software Calibration To calibrate the offset and gain of the ADS8504 in software, no external resistors are required. See the No Calibration section for details on the effects of the external resistors. Refer to Table 4 for range of offset and gain errors with and without external resistors. No Calibration See Figure 23(b) for circuit connections. The external resistors shown in Figure 23(b) may not be necessary in some applications. These resistors provide compensation for an internal adjustment of the offset and gain which allows calibration with a single supply. Refer to Table 4 for range of offset and gain errors with and without external resistors. Table 4. Typical Offset (Bipolar Zero Error, BPZ) and Gain Errors With and Without External Resistors WITH EXTERNAL RESISTORS WITHOUT EXTERNAL RESISTORS -4.88 < BPZ < 4.88 -56.6 < BPZ < -32.2 mV -1 < BPZ < 1 -11.6 < BPZ < -6.6 LSBs +Full scale -0.25 < Error < 0.25 -2.5 < Error < -1.25 –Full scale -0.25 < Error < 0.25 -3.5 < Error < -2.25 BPZ Gain error 200 Ω 1 ±10 V 2 33.2 kΩ +5 V 2.2 µF + 50 kΩ Offset 50 kΩ Gain 576 kΩ 3 4 + 2.2 µF 5 (a) ±10 V With Hardware Trim VIN ±10 V % of FSR 200 Ω 1 2 AGND1 33.2 kΩ 2.2 µF + REF 2.2 µF AGND2 3 4 CAP UNITS VIN AGND1 REF CAP + 5 AGND2 (b) ±10 V Without Hardware Trim Note: Use 1% metal film resistors. Figure 23. Circuit Diagram With and Without External Trim Hardware REFERENCE The ADS8504 can operate with its internal 2.5-V reference or an external reference. By applying an external reference to pin 5, the internal reference can be bypassed. The reference voltage at REF is buffered internally with the output on CAP (pin 4). The internal reference has an 8 ppm/°C drift (typical) and accounts for approximately 20% of the full-scale error (FSE = ±0.5%). 13 ADS8504 www.ti.com SLAS434 – JUNE 2005 REF REF (pin 3) is an input for an external reference or the output for the internal 2.5-V reference. A 2.2-µF capacitor should be connected as close to the REF pin as possible. The capacitor and the output resistance of REF create a low-pass filter to bandlimit noise on the reference. Using a smaller value capacitor introduces more noise to the reference degrading the SNR and SINAD. The REF pin should not be used to drive external ac or dc loads. The range for the external reference is 2.3 V to 2.7 V and determines the actual LSB size. Increasing the reference voltage increases the full-scale range and the LSB size of the converter which can improve the SNR. CAP CAP (pin 4) is the output of the internal reference buffer. A 2.2-µF capacitor should be placed as close to the CAP pin as possible to provide optimum switching currents for the CDAC throughout the conversion cycle and compensation for the output of the internal buffer. Using a capacitor any smaller than 1 µF can cause the output buffer to oscillate and may not have sufficient charge for the CDAC. Capacitor values larger than 2.2 µF have little affect on improving performance. The ESR (equivalent series resistance) of these compensation capacitors is also critical. Keep the total ESR under 3 Ω. See the TYPICAL CHARACTERISTICS section for how performance is affected by ESR. The output of the buffer is capable of driving up to 2 mA of current to a dc load. A dc load requiring more than 2 mA of current from the CAP pin begins to degrade the linearity of the ADS8504. Using an external buffer allows the internal reference to be used for larger dc loads and ac loads. Do not attempt to directly drive an ac load with the output voltage on CAP. This causes performance degradation of the converter. LAYOUT POWER For optimum performance, tie the analog and digital power pins to the same +5-V power supply and tie the analog and digital grounds together. As noted in the electrical specifications, the ADS8504 uses 90% of its power for the analog circuitry. The ADS8504 should be considered as an analog component. The +5-V power for the A/D should be separate from the +5 V used for the system's digital logic. Connecting VDIG (pin 28) directly to a digital supply can reduce converter performance due to switching noise from the digital logic. For best performance, the +5-V supply can be produced from whatever analog supply is used for the rest of the analog signal conditioning. If +12-V or +15-V supplies are present, a simple +5-V regulator can be used. Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter the supply. Either using a filtered digital supply or a regulated analog supply, both VDIG and VANA should be tied to the same +5-V source. GROUNDING Three ground pins are present on the ADS8504. DGND is the digital supply ground. AGND2 is the analog supply ground. AGND1 is the ground which all analog signals internal to the A/D are referenced. AGND1 is more susceptible to current induced voltage drops and must have the path of least resistance back to the power supply. All the ground pins of the A/D should be tied to the analog ground plane, separated from the system's digital logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to the system ground as near to the power supplies as possible. This helps to prevent dynamic digital ground currents from modulating the analog ground through a common impedance to power ground. SIGNAL CONDITIONING The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of charge injection which can cause the driving op amp to oscillate. The FET switch on the ADS8504, compared to the FET switches on other CMOS A/D converters, releases 5%-10% of the charge. There is also a resistive front end which attenuates any charge which is released. The end result is a minimal requirement for the anti-alias filter on the front end. Any op amp sufficient for the signal in an application is sufficient to drive the ADS8504. The resistive front end of the ADS8504 also provides an assured ±25-V overvoltage protection. In most cases, this eliminates the need for external input protection circuitry. 14 ADS8504 www.ti.com SLAS434 – JUNE 2005 LAYOUT (continued) INTERMEDIATE LATCHES The ADS8504 does have 3-state outputs for the parallel port, but intermediate latches should be used if the bus is to be active during conversions. If the bus is not active during conversion, the 3-state outputs can be used to isolate the A/D from other peripherals on the same bus. The 3-state outputs can also be used when the A/D is the only peripheral on the data bus. Intermediate latches are beneficial on any monolithic A/D converter. The ADS8504 has an internal LSB size of 610 µV. Transients from fast switching signals on the parallel port, even when the A/D is 3-stated, can be coupled through the substrate to the analog circuitry causing degradation of converter performance. 15 PACKAGE OPTION ADDENDUM www.ti.com 8-Aug-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS8504IBDW ACTIVE SOIC DW 28 ADS8504IBDWR ACTIVE SOIC DW ADS8504IBDWRG4 ACTIVE SOIC DW 20 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS8504IBDW ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8504IBDWG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8504IBDWR ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8504IBDWRG4 ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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