OPA2107 OPA 210 7 OPA 210 7 SBOS161A – JANUARY 1989 – REVISED JULY 2003 Precision Dual Difet ® Operational Amplifier FEATURES APPLICATIONS ● ● ● ● ● ● ● ● ● ● ● ● Very Low Noise: 8nV/√Hz at 10kHz Low VOS: 1mV max Low Drift: 10µV/°C max Low IB: 10pA max Fast Settling Time: 2µs to 0.01% Unity-Gain Stable Data Acquisition DAC Output Amplifiers Optoelectronics High-Impedance Sensor Amps High-Performance Audio Circuitry Medical Equipment, CT Scanners DESCRIPTION +V S The OPA2107 dual operational amplifier provides precision Difet performance with the cost and space savings of a dual op amp. It is useful in a wide range of precision and low-noise analog circuitry and can be used to upgrade the performance of designs currently using BIFET® type amplifiers. The OPA2107 is fabricated on a proprietary dielectrically isolated (Difet ) process. This holds input bias currents to very low levels without sacrificing other important parameters, such as input offset voltage, drift and noise. Lasertrimmed input circuitry yields excellent dc performance. Superior dynamic performance is achieved, yet quiescent current is held to under 2.5mA per amplifier. The OPA2107 is unity-gain stable. The OPA2107 is available in DIP-8 and SO-8 packages. (8) –In (2, 6) +In (3, 5) Cascode Output (1, 7) –V S (4) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 1989-2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Supply Voltage ................................................................................... ±18V Input Voltage Range ..................................................................... ±VS ±2V Differential Input Voltage ....................................................... Total VS ±4V Operating Temperature P and U Packages ........................................................ –25°C to + 85°C Storage Temperature P and U Packages ....................................................... –40°C to +125°C Output Short Circuit to Ground (TA = +25°C) ........................... Continuous Junction Temperature .................................................................... +175°C Lead Temperature P Package (soldering, 10s) ......................................................... +300°C U Package, SOIC (3s) ................................................................ +260°C Top View DIP, SO 8 +V S Out A 1 –In A 2 A 7 Out B NOTE: Stresses above these ratings may cause permanent damage. +In A 3 ELECTROSTATIC DISCHARGE SENSITIVITY B 6 –In B 5 +In B –VS 4 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY OPA2107 DIP-8 P –25°C to +85°C OPA2107AP OPA2107AP Tube, 50 OPA2107 SO-8 D –25°C to +85°C OPA2107AU " " " " OPA2107AU OPA2107AU/2K5 Tube, 100 Tape and Reel, 2500 " NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. 2 OPA2107 www.ti.com SBOS161A ELECTRICAL CHARACTERISTICS At TA = +25°C, VS = ±15V, unless otherwise noted. OPA2107AP, AU PARAMETER CONDITION MIN TYP MAX UNITS 1 2 10 80 0.1 0.5 3 96 mV mV µV/°C dB 4 0.25 1 10 1.5 8 1 pA nA pA nA VOLTAGE(1) OFFSET Input Offset Voltage Over Specified Temperature Average Drift Over Specified Temperature Power Supply Rejection INPUT BIAS CURRENT(1) Input Bias Current Over Specified Temperature Input Offset Current Over Specified Temperature INPUT NOISE Voltage: f = 10Hz f = 100Hz f = 1kHz f = 10kHz BW = 0.1 to 10Hz BW = 10 to 10kHz Current: f = 0.1Hz thru 20kHz BW = 0.1Hz to 10Hz VCM = 0V VS = ±10 to ±18V VCM = 0V VCM = 0V RS = 0 30 12 9 8 1.2 0.85 1.2 23 nV/√Hz nV/√Hz nV/√Hz nV/√Hz µVp-p µVrms fA/√Hz fAp-p 1013 || 2 1014 || 4 Ω || pF Ω || pF ±10.5 ±10.2 80 ±11 ±10.5 94 V V dB VO = ±10V, RL = 2kΩ 82 80 96 94 dB dB G = +1 G = –1, 10V Step 13 18 1.5 2 4.5 0.001 120 V/µs µs µs MHz % dB ±15 ±4.5 V V mA ±12 ±11.5 ±40 70 1000 V V mA Ω pF INPUT IMPEDANCE Differential Common-Mode INPUT VOLTAGE RANGE Common-Mode Input Range Over Specified Temperature Common-Mode Rejection OPEN-LOOP GAIN Open-Loop Voltage Gain Over Specified Temperature DYNAMIC RESPONSE Slew Rate Settling Time: 0.1% 0.01% Gain Bandwidth Product THD + Noise Channel Separation VCM = ±10V G = 100 G = +1, f = 1kHz f = 100Hz, RL = 2kΩ POWER SUPPLY Specified Operating Voltage Operating Voltage Range Current OUTPUT Voltage Output Over Specified Temperature Short Circuit Current Output Resistance, Open-Loop Capacitive Load Stability ±4.5 RL = 2kΩ ±11 ±10.5 ±10 1MHz G = +1 TEMPERATURE RANGE Specification Operating Storage Thermal Resistance (θJ-A) DIP-8 SO-8 –25 –25 –40 +85 +85 +125 90 175 °C °C °C °C/W °C/W NOTE: (1) Specified with devices fully warmed up. OPA2107 SBOS161A www.ti.com 3 TYPICAL CHARACTERISTICS TA = +25°C, VS = ±15V unless otherwise noted. INPUT VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs FREQUENCY TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY at 1kHz vs SOURCE RESISTANCE 100 Current Noise 10 10 1 Current Noise Voltage Noise Voltage Noise, E O (n/V/ Hz) Voltage Noise 100 1k Current Noise (ƒA/ Hz) Voltage Noise (nV/ Hz) 1k EO RS 100 OPA2107 + Resistor 10 Resistor Noise Only 1 0.1 10 100 1k 10k 100k 1M 100 1k 1nA 1nA 100 100 Bias Current 10 10 0 +25 +50 10M 100M +75 10 Offset Current 1 1 0.1 0.1 1 Offset Current –25 1M 10 Bias Current (pA) 10nA Offset Current (pA) Bias Current (pA) 10nA 1 0.1 –50 100k INPUT BIAS AND OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE INPUT BIAS AND OFFSET CURRENT vs TEMPERATURE 1 10k Source Resistance ( Ω) Frequency (Hz) Offset Current (pA) 1 1 +100 0.01 0.1 +125 0.01 –15 –10 –5 0 +5 +10 Ambient Temperature (°C) Common-Mode Voltage (V) POWER SUPPLY AND COMMON-MODE REJECTION vs FREQUENCY COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE 110 120 120 +15 100 PSR, CMR (dB) 100 80 80 –PSR 60 60 CMR 40 40 20 20 Common-Mode Rejection (dB) +PSR 100 10 100 1k 10k 100k 1M –15 10M –10 –5 0 +5 +10 +15 Common-Mode Voltage (V) Frequency (Hz) 4 80 70 0 0 90 OPA2107 www.ti.com SBOS161A TYPICAL CHARACTERISTICS (Cont.) TA = +25°C, VS = ±15V unless otherwise noted. MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY OPEN-LOOP FREQUENCY RESPONSE 0 Voltage Gain (dB) –45 80 φ 60 40 –90 AOL –135 Output Voltage (Vp-p) RL = 2kΩ CL = 100pF 100 30 Phase Shift (Degrees) 120 20 R L = 2k Ω 10 20 0 10k –180 1 10 100 1k 10k 100k 1M 10M 100k 1M 10M Frequency (Hz) Frequency (Hz) GAIN-BANDWIDTH AND SLEW RATE vs TEMPERATURE GAIN-BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE 8 25 6 22 20 Slew Rate Gain-Bandwidth 4 15 2 10 Gain-Bandwidth (MHz) 6 Slew Rate (V/µs) Gain-Bandwidth (MHz) A V = +100 RL = 2k Ω 20 5 18 Slew Rate Slew Rate (V/µs) 0 16 Gain-Bandwidth 0 –50 –25 0 +25 +50 +75 5 +125 +100 14 4 5 10 Ambient Temperature (°C) 15 20 Supply Voltage (±VS ) SETTLING TIME vs CLOSED-LOOP GAIN SUPPLY CURRENT vs TEMPERATURE 5 7 0.01% 3 VO = 10V Step RL = 2k Ω 2 0.1% CL = 100pF Supply Current (mA) Settling Time (µs) 4 1 6 Total of Both Op Amps 5 4 3 0 –1 –10 –100 –50 –1000 OPA2107 SBOS161A –25 0 +25 +50 +75 +100 +125 Ambient Temperature (°C) Closed-Loop Gain (V/V) www.ti.com 5 TYPICAL CHARACTERISTICS (Cont.) TA = +25°C, VS = ±15V unless otherwise noted. OPEN-LOOP GAIN vs SUPPLY VOLTAGE 120 140 110 RL = ∞ Voltage Gain (dB) Channel Separation (dB) CHANNEL SEPARATION vs FREQUENCY 150 130 RL = 2k Ω 120 100 90 80 110 70 10 100 1k 10k 100k 5 10 Frequency (Hz) 15 THD + NOISE vs FREQUENCY AND OUTPUT VOLTAGE TOTAL HARMONIC DISTORTION vs FREQUENCY 1 1 A V = +11V/V THD + Noise (%rms) THD + Noise (%rms) 6.5Vrms 2k Ω RS 0.1 A V = +101V/V 0.01 RS A V = +1V/V Noise Limited 0.01 10Vp-p Noise Limited 20Vp-p 0.001 100 1k 10k 1 100k 10 100 1k Frequency (Hz) Frequency (Hz) LARGE-SIGNAL RESPONSE SMALL-SIGNAL RESPONSE Time (2µs/div) 6 Noise Limited 2Vp-p 10k 100k Output Voltage (20mV/div) 10 Output Voltage (5V/div) 1 2k Ω 0.1 A V = +11V/V 0.001 20 Supply Voltage (±VS ) Time (200ns/div) OPA2107 www.ti.com SBOS161A APPLICATIONS INFORMATION AND CIRCUITS –In The OPA2107 is unity-gain stable and has an excellent phase margin. This makes it easy to use in a wide variety of applications. INA105 RF 2 RG 6 3 25kΩ 5 1 1/2 OPA2107 FIGURE 2. FET Input Instrumentation Amplifier. E1 –In 1/2 OPA2107 3 1 A 2 INA106 RF 2 In 3 E2 +In 2 A 3 In A Out A 1 FIGURE 1. Connection of Input Guard. Out 202Ω 6 5 3 EO Output 10kΩ 10kΩ 100kΩ B 7 1 Using the INA106 for an output difference amplifier extends the input common-mode range of an instrumentation amplifier (IA) to ±10V. A conventional IA with a unity-gain difference amplifier has an input common-mode range limited to ±5V for an output swing of ±10V. This is because a unity-gain difference amplifier needs ±5V at the input for 10V at the output, allowing only 5V additional for common-mode range. FIGURE 3. Precision Instrumentation Amplifier. OPA2107 SBOS161A 5 EO = [10 (1 + 2RF /RG) (E2 – E1)] = 1000 (E2 – E1) 2 3 100kΩ 1/2 OPA2107 Non-Inverting In 10kΩ 10kΩ 6 1 IB = 5pA Max Gain = 100 CMRR ~ 95dB RIN = 1013Ω ~ Differential Voltage Gain = 1 + 2RF/RG = 100 Buffer 1 Output 25kΩ 7 B RF Out 5 5kΩ 6 RG 2 25kΩ 101Ω RF A circuit-board guard pattern effectively reduces errors due to circuit-board leakage (Figure 1). By encircling critical highimpedance nodes with a low-impedance connection at the same circuit potential, any leakage currents will flow harmlessly to the low-impedance node. Guard traces should be placed on all levels of a multiple-layer circuit board. Inverting 25kΩ 5kΩ +In The OPA2107 Difet input stages have very low input bias current—an order of magnitude lower than BIFET op amps. Circuit-board leakage paths can significantly degrade performance. This is especially evident with the SO-8 surfacemount package where pin-to-pin dimensions are particularly small. Residual soldering flux, dirt, and oils, which conduct leakage current, can be removed by proper cleaning. In most instances, a two-step cleaning process is adequate using a clean organic solvent rinse followed by deionized water. Each rinse should be followed by a 30-minute bake at 85°C. 1 A 2 Power-supply connections should be bypassed with capacitors positioned close to the amplifier pins. In most cases, 0.1µF ceramic capacitors are adequate. Applications with larger load currents and fast transient signals may need up to 1µF tantalum bypass capacitors. INPUT BIAS CURRENT 1/2 OPA2107 3 www.ti.com 7 PACKAGE OPTION ADDENDUM www.ti.com 26-Mar-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty OPA2107AP ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type OPA2107APG4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type OPA2107AU ACTIVE SOIC D 8 100 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA2107AU/2K5 ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA2107AU/2K5E4 ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR OPA2107AUE4 ACTIVE SOIC D 8 100 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 MECHANICAL DATA MPDI001A – JANUARY 1995 – REVISED JUNE 1999 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gage Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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