SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS160C – DECEMBER 1992 – REVISED MAY 1997 D D D D D D D D D SN54ABT16373A . . . WD PACKAGE SN74ABT16373A . . . DGG OR DL PACKAGE (TOP VIEW) Members of the Texas Instruments Widebus Family State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up and Power Down Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout High-Drive Outputs (–32-mA IOH, 64-mA IOL) Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings description The ’ABT16373A are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2LE These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16373A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT16373A is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS160C – DECEMBER 1992 – REVISED MAY 1997 FUNCTION TABLE (each 8-bit section) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic symbol† 1OE 1LE 2OE 2LE 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 1 1EN 48 C3 24 2EN 25 C4 47 3D 2 1 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 4D 2 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1OE 1LE 1D1 1 2OE 48 47 2LE C1 2 1D 1Q1 24 25 C1 2D1 36 To Seven Other Channels To Seven Other Channels 2 POST OFFICE BOX 655303 1D • DALLAS, TEXAS 75265 13 2Q1 SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS160C – DECEMBER 1992 – REVISED MAY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT16373A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT16373A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51. recommended operating conditions (see Note 3) SN54ABT16373A MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 High-level input voltage SN74ABT16373A MIN 2 2 0.8 Input voltage 0 Low-level output current Outputs enabled VCC –24 V V 0.8 0 UNIT VCC –32 V V mA 48 64 mA 10 10 ns/V µs/V 200 125 –40 85 °C NOTE 3: Unused inputs must be held high or low to prevent them from floating. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS160C – DECEMBER 1992 – REVISED MAY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOL VCC = 4 4.5 5V MIN TA = 25°C TYP† MAX SN54ABT16373A MIN –1.2 MAX SN74ABT16373A MIN –1.2 –1.2 2.5 2.5 2.5 IOH = –3 mA IOH = –24 mA 3 3 3 2 2 IOH = –32 mA IOL = 48 mA 2* II IOZPU‡ V V IOL = 64 mA 0.55 0.55* 0.55 100 VCC = 0 to 5.5 V, VI = VCC or GND UNIT 2 0.55 Vhys MAX V mV ±1 ±1 ±1 µA VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 µA IOZPD‡ VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 µA IOZH VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE ≥ 2 V 10 10 10 µA IOZL VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE ≥ 2 V –10 –10 –10 µA ±100 µA Ioff ICEX IO§ Outputs high VCC = 0, VI or VO ≤ 4.5 V VCC = 5.5 V, VO = 5.5 V VCC = 5.5 V, VO = 2.5 V ±100 50 –50 –100 –180 Outputs high 50 –50 –180 –50 50 µA –180 mA 2 2 2 5 5 V, V IO = 0, 0 VCC = 5.5 VI = VCC or GND 85 85 85 2 2 2 ∆ICC¶ VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 1.5 1.5 1.5 Ci VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V ICC Outputs low Outputs disabled Co mA mA 3.5 pF 9.5 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ This parameter is characterized, but not production tested. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C# MIN tw tsu MIN MAX SN74ABT16373A MIN UNIT MAX Pulse duration, LE high 3.3 3.3 3.3 ns Setup time, data before LE↓ 1.5 2.4 1.5 ns 1 2.2 1 ns th Hold time, data after LE↓ # These values apply only to the SN74ABT16373A. 4 MAX SN54ABT16373A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS160C – DECEMBER 1992 – REVISED MAY 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54ABT16373A PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q VCC = 5 V, TA = 25°C MIN MAX MIN TYP MAX 1.4 3.7 5.3 1.4 6.5 2 4 5.4 2 6.5 1.7 4.1 5.7 1.7 7 2.3 4.3 5.6 2.3 6.3 1.1 3.4 5 1.1 6.4 1.5 3.5 4.9 1.5 5.8 2.4 5.1 7.1 2.4 8.3 1.6 4.4 6.3 1.6 8 UNIT ns ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74ABT16373A PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC = 5 V, TA = 25°C MIN MAX MIN TYP MAX 1.4 3.7 5.3 1.4 6.3 2 4 5.4 2 6.2 1.7 4.1 5.7 1.7 6.7 2.3 4.3 5.6 2.3 6.1 1.1 3.4 5 1.1 6.1 1.5 3.5 4.9 1.5 5.6 2.4 5.1 7.1 2.4 8.1 1.6 4.4 5.8 1.6 6.5 UNIT ns ns ns ns 5 SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS160C – DECEMBER 1992 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V 1.5 V Input 1.5 V 0V Data Input 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 3V 1.5 V Input 1.5 V 0V VOH 1.5 V Output 1.5 V VOL VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ Output Waveform 1 S1 at 7 V (see Note B) tPLH tPHL Output 3V Output Control tPHL tPLH 1.5 V Output Waveform 2 S1 at Open (see Note B) 1.5 V 3.5 V VOL + 0.3 V VOL tPHZ tPZH 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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