PRELIMINARY CM3132 Triple Linear Voltage Regulator for DDR-I Memory and CPU Features Product Description • The CM3132 provides an integrated power solution for a CPU core and DDR-I memory for consumer and other embedded applications. It features three independent linear regulators for VCORE, VDDQ and VTT supply regulation. The default voltage for VCORE is 1.5V. The SENSE_CORE pin can be tied to GND for the default voltage, or through a resistor divider for setting the CPU core in the range 1.2V to 1.8V. VDDQ is internally set to 2.50V and the VTT voltage is always half the VDDQ voltage. A capacitor should be connected to each of the three outputs. • • • • • • • • Fully integrated power solution for a CPU/SOC core and DDR-I memory ICs Lowest system cost and smallest footprint with just three external output capacitors Three linear regulators for VCORE (1.5A), VDDQ (1.5A), and VTT (0.5A, source-sink) VDDQ = 2.5V, VTT = VDDQ/2 ±25mV VCORE is adjustable, with a default output of 1.5V Over-temperature and reverse current protection Overcurrent protection for all regulators PSOP-8 package with integrated heat spreader Lead-free version available Applications • Core CPU and DDR-I memory power for: − Set Top Boxes, DVD Players, Games − Digital TVs, Flat Panel Displays − Printers, Digital Projectors − Embedded systems − Communications systems There are two enable pins, EN_CORE and EN_DDR. When EN_CORE is set high, the CORE regulator is disabled. When EN_DDR is set high, the two DDR regulators are disabled to minimize overall system power dissipation when memory is in standby mode. These two enable pins allow power sequencing of the DDR and CORE regulator blocks independently. The CM3132 is available in a PSOP-8 package that has excellent thermal dissipation. It is available with optional lead-free finishing. Typical Application Circuit Circuit Schematic VCC 2.8V to 3.3V CVCC VDDQ REGULATOR VREF VCC VDDQ REGULATOR VREF VDDQ VDDQ = 2.5V EN_DDR Enable DDR Memory # CDDQ EN_DDR DDR MEMORY VTT REGULATOR R VTT REGULATOR R VREF=1.25V VTT R VTT=1.25V R CTT VREF CCORE EN_CORE SENSE_CORE VCORE CPU CORE + I/O VCORE R3 Enable CORE# VCORE REGULATOR VREF VCORE REGULATOR EN_CORE SENSE_CORE R4 GND GND © 2004 California Micro Devices Corp. All rights reserved. 10/13/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 1 PRELIMINARY CM3132 PACKAGE / PINOUT DIAGRAM TOP VIEW VCORE 1 8 SENSE_CORE VCC 2 7 GND VDDQ 3 6 EN_CORE VTT 4 5 EN_DDR 8-Lead PSOP Note: This drawing is not to scale. PIN DESCRIPTIONS PSOP-8 LEAD NAME DESCRIPTION 1 VCORE VCORE output. 2 VCC Input supply. 3 VDDQ VDDQ output. 4 VTT 5 EN_DDR 6 EN_CORE 7 GND 8 SENSE_CORE PAD GND VTT output for termination resistors or VREF Enable DDR power. Active low input. Enable VCORE. Active low input. Ground reference. Sense input. Adjusts VCORE output voltage using external resistor divider. When tied to GND, VCORE = 1.5V. Tied to ground reference. Ordering Information PART NUMBERING INFORMATION Standard Finish Lead-free Finish Leads Package Ordering Part Number1 Part Marking Ordering Part Number1 Part Marking 8 PSOP-8 CM3132-02SB CM3132 02SB CM3132-02SH CM3132 02SH Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. © 2004 California Micro Devices Corp. All rights reserved. 2 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 10/13/04 PRELIMINARY CM3132 Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS ±2000 V [GND - 0.6] to [+6.5] [GND - 0.6] to [VCC + 0.6] [GND - 0.6] to [VCC + 0.6] V V V -40 to +150 °C 0 to +85 0 to +125 °C °C PARAMETER RATING UNITS Ambient Operating Temperature Range 0 to +85 °C [VDDQ + 0.3] to 3.6 V 0 to 1500 mA 10, 10 µF DDR-I Supply Voltage VDDQ 2.3 to 2.8 V DDR-I Load Current 0 to ±500 mA 47 µF [VDDQ or VCORE + 0.3] to 3.6 V 0 to 1500 mA 10 µF ESD (Human Body Model) Pin Voltages VCC EN_CORE, EN_DDR, SENSE_CORE VDDQ, VTT Storage Temperature Range Operating Temperature Range Ambient Junction STANDARD OPERATING CONDITIONS 1. VDDQ Regulator DDR-I Supply Voltage VCC Load Current CCC, CDDQ 2. VTT Regulator CTT 3. VCORE Regulator Core Supply Voltage VCC DDR-I Load Current CCORE © 2004 California Micro Devices Corp. All rights reserved. 10/13/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 3 PRELIMINARY CM3132 Specifications (cont’d) ELECTRICAL OPERATING CHARACTERISTICS SYMBOL PARAMETER CONDITIONS (SEE NOTE1) MIN TYP MAX UNITS - 150 - °C - 25 - °C General Parameters TOVER Shutdown Junction Temperature THYST Junction Temp Hysterisis IC in shutdown ICCN Normal Mode VCC Supply Current EN_DDR = logic "0", EN_CORE =logic "0" 400 800 µA ICCQ Shutdown Mode VCC Supply Current EN_DDR = logic "1", EN_CORE =logic "1" 2 10 µA ISENSE IN SENSE_CORE Input Current VSENSE_CORE=0.6V 0.1 1.0 µA VIH EN_DDR, EN_CORE Input High Threshold VCORE=3.3V VIL EN_DDR, EN_CORE Input Low Threshold VCORE=3.3V 0.4 V UVLO Under Voltage Lock-Out IDDQ = 10mA 1.8 V tRISE VDDQ, VCORE Rise TIme VCC = 3.3V, CLOAD = 10µF 2.0 V 0.5 ms VDDQ Regulator Parameters VCC MIN Input Voltage VDDQ = 2.5V, IDDQ = 1.5A, Note 2 2.80 V VDDQ DEF Default Output Voltage IDDQ = 0.01A, 2.8V ≤ VCC ≤ 3.6V, Note 2 2.45 2.50 2.55 V VDDQ LD Load Regulation TA = 25°C, VCC = 3.3V, - - 2.5 % VDDQ LINE Line Regulation -1.0 - 1.0 % 0.01A ≤ IDDQ ≤ 1.5A, Note 2 TA = 25°C, IDDQ = 0.01A, 2.8V ≤ VCC ≤ 3.6V, Note 2 eN DDQ Output Noise Voltage BW = 10Hz - 100kHz, CDDQ = 10µF IDDQ LIM Current Limit Note 2 IDDQ SC Short Circuit Current VDDQ < 0.3V 1.7 49 µVrms 2.0 A 0.5 A www.calmicro.com 10/13/04 © 2004 California Micro Devices Corp. All rights reserved. 4 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● PRELIMINARY CM3132 ELECTRICAL OPERATING CHARACTERISTICS (CONT’D) (SEE NOTE1) VTT Regulator Parameters VTT Output Voltage Range VDDQ = 2.5V, ITT = 0.01A, IDDQ = 0A 1.20 1.25 1.30 V VTT REF Output Voltage Range VCC = 0V, VDDQ = 2.500V, ITT = 0.01A 1.225 1.250 1.275 V VTT LD Load Regulation TA = 25°C, VDDQ = 2.5V, -1.0 - 1.0 % eN TT Output Noise Voltage ITT LIM Current Limit ITT SC Short Circuit Current 0.01A ≤ ITT ≤ ±0.5A BW = 10Hz - 100kHz, CTT = 10µF 0.6 VTT < 0.7V 51 µVrms 0.8 A 0.3 A VCORE Regulator Parameters Input Voltage VCORE = 1.5V, ICORE = 1.5A, SENSE_CORE = 0V, Note 3 2.2 VCORE DEF Default Output Voltage Range VCC = 3.3V, ICORE = 0.01A, SENSE_CORE = 0V 1.45 VCORE ADJ Adjustable Output Voltage Range VCC = 3.3V, SENSE_CORE from resistors R3 & R4, Note 4 1.2 VCORE LD Load Regulation TA = 25°C, VCC = 3.3V, VCC MIN V 1.50 1.55 V 1.8 V - - 2.5 % -1.0 - 1.0 % 0.01A ≤ ICORE ≤ ±1.5 TA = 25°C, 2.8V ≤ VCC ≤ 3.6V, ICORE = 0.01A VCORE LINE Line Regulation eN CORE Output Noise Voltage ICORE LIM Current Limit ICORE SC Short Circuit Current BW = 10Hz - 100kHz, CCORE = 47µF 1.7 VCORE < 0.3V 59 µVrms 2.0 A 0.5 A Note 1: All parameters specified at TA = 0°C to +85°C unless otherwise noted. Note 2: Note that the IDDQ current specified is the load current output from the VDDQ pin. VDDQ also supplies current internally to the VTT regulator when it is sourcing current. The maximum source current can be up to 0.5A.The maximum total current from the VDDQ regulator is the external VDDQ current IDDQ added to the maximum VTT sourcing current ITT. All load currents are specified as such, but the VDDQ current limit is specified at a current just above the total maximum current. Note 3: VCORE regulator only. Refer to VDDQ regulator parameters for VDDQ regulator. R3 R4 Note 4: VCORE = 1.15V X (1 + -------- ) VCC(1) EN_DDR VDDQ OUT VTT OUT 2.8V to 3.6V Low VDDQ VDDQ / 2 X High 0V 0V Table 1: Truth Table for CM3132 © 2004 California Micro Devices Corp. All rights reserved. 10/13/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 5 PRELIMINARY CM3132 Performance Information Power Supply Ripple Rejection CCC = 10µF, VCC = 3.3V, ILOAD = 50mA, PSRR measured with 50mV pk-pk sin wave on VCC. 50 45 40 PSRR (dB) 35 30 25 20 15 10 5 0 10 100 1000 10000 100000 Frequency (Hz) Figure 1. VCORE PSRR (VCORE = 1.5V) 50 45 40 PSRR (dB) 35 30 25 20 15 10 5 0 10 100 1000 10000 100000 Frequency (Hz) Figure 2. VDDQ PSRR (VDDQ = 2.5V) © 2004 California Micro Devices Corp. All rights reserved. 6 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 10/13/04 PRELIMINARY CM3132 60 50 PSRR (dB) 40 30 20 10 0 10 100 1000 10000 100000 Frequency (Hz) Figure 3. VTT PSRR (VTT = 1.25V) © 2004 California Micro Devices Corp. All rights reserved. 10/13/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 7 PRELIMINARY CM3132 Performance Information (cont’d) Typical Thermal Characteristics PCB Layout Considerations The overall junction to ambient thermal resistance (θJA) for device power dissipation (PD) consists primarily of two paths in series. The first path is the junction to the case (θJC) which is defined by the package style, and the second path is case to ambient (θCA) thermal resistance which is dependent on board layout. The final operating junction temperature for any set of conditions can be estimated by the following thermal equation: The CM3132-02SB/SH has a heat spreader attached to the bottom of the PSOP-8 package in order for heat to be transferred more easily from the package to the PCB. The heat spreader is a copper pad of dimensions just smaller than the package itself. By positioning the matching pad on the PCB top layer to connect to the spreader during manufacturing, the heat will be transferred between the two pads. The drawing below shows the recommended PCB layout. Note that there are six vias on either side to allow the heat to dissipate into the ground and power planes on the inner layers of the PCB. Vias can be placed underneath the chip, but this can cause blockage of the solder. The ground and power planes should be at least 2 sq in. of copper by the vias. It also helps dissipation if the chip is positioned away from the edge of the PCB, and not near other heat-dissipating devices. A good thermal link from the PCB pad to the rest of the PCB will assure the best heat transfer from the CM3132 package to ambient, θJA, of around 40°C/W. TJUNC = TAMB + PD ( θJC ) + PD ( θCA ) = TAMB + PD ( θJA) When a CM3132-02SB (PSOP-8) is mounted on a double-sided printed circuit board with two square inches of copper allocated for "heat spreading," the resulting θJA is 40°C/W. Based on the over temperature limit of 150° C with an ambient of 70°C, the available power of this package will be: 150° C – 70° C PD = --------------------------------------- = 2W 40° C/ W Figure 4. Recommended Heat Sink PCB Layout © 2004 California Micro Devices Corp. All rights reserved. 8 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 10/13/04 PRELIMINARY CM3132 Application Information Other Applications The CM3132 can be used without any external resistors if a core voltage of 1.5V is required, the SENSE_CORE pin is connected to GND. In applications where a reference voltage (VREF) is required, the VTT pin can be used. The VTT output pin has an error relative to VDDQ/2 of up to ±25mV, which is well within most DDR system specs of ±50mV. This is because the VTT output internally tracks the VDDQ output very closely due to the matched on-chip resistors R that tap down from the VDDQ rail, and the low offset voltage of the VTT regulator. It is recommended that the VREF trace be connected directly to the VTT pin, as shown in Figure 5, to eliminate noise and ripple on the VTT trace caused by current switching. VCC 2.8V to 3.3V CVCC Enable DDR Memory VDDQ REGULATOR VREF VDDQ = 2.5V CDDQ EN_DDR DDR-I MEMORY VTT REGULATOR R VREF=1.25V VTT=1.25V R CTT VCORE REGULATOR VREF Enable CORE VCORE=1.5V CPU CORE + I/O CCORE EN_CORE SENSE_CORE GND Figure 5. Minimal cost solution for CM3132 supplying DDR memory and core CPU. © 2004 California Micro Devices Corp. All rights reserved. 10/13/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 9 PRELIMINARY CM3132 Application Information (cont’d) 1 PSOP-8 IC drives 1-DIMM single channel DDR-I and CPU Core VCORE rail VCC VCC VDDQ REGULATOR VREF VDDQ=2.5V, 1A MAX, 1A CONTINUOUS CDDQ EN_DDR Enable DDR Memory DDR-I MEMORY VTT REGULATOR R VREF=1.25V, 0.5A MAX, 0.1A CONTINUOUS R CM3132-02 PSOP-8 CTT VCORE REGULATOR VREF VCORE=1.5V, 1A MAX, 1A CONTINUOUS CCORE EN_CORE Enable CORE CPU CORE + I/O SENSE_CORE GND With 3.3VCC @ 1A (VDDQ), 0.1A (VTT), 1A (VCORE), PD = (3.3-2.5) * 1.05 + (2.5-1.25) * 0.1 + (3.3-1.5) * 1 = 0.84 + 0.125 + 1.8 = 2.765W With 3.0VCC @ 1A (VDDQ), 0.1A (VTT), 1A (VCORE), PD = (3.0-2.5) * 1.05 + (2.5-1.25) * 0.1 + (3.0-1.5) * 1 = 0.525 + 0.125 + 1.5 = 2.15W With 2.8VCC @ 1A (VDDQ), 0.1A (VTT), 1A (VCORE), PD = (2.8-2.5) * 1.05 + (2.5-1.25) * 0.1 + (2.8-1.5) * 1 = 0.315 + 0.125 + 1.3 = 1.74W Figure 6. Power Dissipation Calculations PD = (Vcc-2.5)*Iddq + (2.5-1.25)*0.1 + (Vcc-Vcore)*Icore PD - (Vcc-2.5)*Iddq - 0.125 = (Vcc-Vcore)*Icore Icore = [PD - (Vcc-2.5)*Iddq - 0.125] / (Vcc-Vcore) TJUNC = TAMB + PD * (θJA) PD = (TAMB - TJUNC ) / (θJA) θJA = 40 oC/W θJA = 60 oC/W θJA = 80 oC/W Derating (degC/W) 40 Ambient (degC) 85 40 85 40 85 40 60 40 60 40 60 40 40 40 40 40 40 Max Power (W) Vcc (V) Min Vcore (V) Max Iddq (A) Max Icore (A) 1.6 3.3 1.5 1.0 0.4 1.6 3.0 1.5 0.8 0.7 1.6 2.8 1.5 0.5 1.0 2.3 3.3 1.5 1.0 0.7 2.3 3.0 1.4 1.0 1.0 2.3 2.8 1.0 1.0 1.0 2.8 3.3 1.5 1.0 1.0 2.8 3.0 1.2 1.0 1.0 2.8 2.8 1.1 1.0 1.4 Derating (degC/W) 60 Ambient (degC) 85 60 85 60 85 60 60 60 60 60 60 60 40 60 40 60 40 Max Power (W) Vcc (V) Min Vcore (V) Max Iddq (A) Max Icore (A) 1.1 3.3 1.5 0.3 0.4 1.1 3.0 1.5 0.5 0.5 1.1 2.8 1.5 0.6 0.6 1.5 3.3 1.5 1.0 0.3 1.5 3.0 1.5 0.7 0.7 1.5 2.8 1.5 0.5 0.9 1.8 3.3 1.5 0.5 0.7 1.8 3.0 1.5 0.7 1.0 1.8 2.8 1.4 1.0 1.0 Derating (degC/W) 80 Ambient (degC) 85 80 85 80 85 80 60 80 60 80 60 80 40 80 40 80 40 Max Power (W) Vcc (V) Min Vcore (V) Max Iddq (A) Max Icore (A) 0.8 3.0 1.5 0.3 0.4 0.8 2.8 1.5 0.3 0.5 1.1 3.3 1.5 0.5 0.3 1.1 3.0 1.5 0.5 0.5 1.1 2.8 1.5 0.5 0.7 1.4 3.3 1.5 0.5 0.5 1.4 3.0 1.5 0.7 0.6 1.4 2.8 1.5 0.5 0.8 0.8 3.3 1.5 0.3 0.2 Figure 7. Power Derating Table © 2004 California Micro Devices Corp. All rights reserved. 10 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 10/13/04 PRELIMINARY CM3132 Mechanical Details PSOP-8 Mechanical Specifications Dimensions for CM3132 devices packaged in an 8lead PSOP package with a heatspreader are shown below. Mechanical Package Diagrams TOP VIEW D PACKAGE DIMENSIONS Package PSOP-8 Leads 8 Dimensions Millimeters 8 7 6 5 Inches H Min Max Min Max A 1.30 1.62 0.051 0.064 A1 0.03 0.10 0.001 0.004 B 0.33 0.51 0.013 0.020 C 0.18 0.25 0.007 0.010 D 4.83 5.00 0.190 0.197 E 3.81 3.99 0.150 0.157 e 1.02 1.52 0.040 0.060 H 5.79 6.20 0.228 0.244 L 0.41 1.27 0.016 0.050 x** 3.30 3.81 0.130 0.150 y** 2.29 2.79 0.090 0.110 # per tube 100 pieces* # per tape and reel 2500 pieces Pin 1 Marking 1 2 3 E 4 BOTTOM VIEW D 1 2 3 4 Heat Slug x H y x/2 8 Controlling dimension: inches * This is an approximate number which may vary. 7 E y/2 6 5 SIDE VIEW ** Centered on package centerline. A SEATING PLANE A1 e B END VIEW C L Package Dimensions for PSOP-8 © 2004 California Micro Devices Corp. All rights reserved. 10/13/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com 11