CERAMATE CP494

CP494
SWITCHMODE Pulse Width Modulation Control Circuit
The CP494 is a fixed frequency, pulse width modulation control
circuit designed primarily for SWITCHMODE power supply control.
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Complete Pulse Width Modulation Control Circuitry
On–Chip Oscillator with Master or Slave Operation
On–Chip Error Amplifiers
On–Chip 5.0 V Reference
Adjustable Deadtime Control
Uncommitted Output Transistors Rated to 500 mA Source or Sink
Output Control for Push–Pull or Single–Ended Operation
Undervoltage Lockout
MAXIMUM RATINGS (Full operating ambient temperature range applies,
unless otherwise noted.)
Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
42
V
Collector Output Voltage
VC1,
VC2
42
V
Collector Output Current
(Each transistor) (Note 1)
IC1, IC2
500
mA
Amplifier Input Voltage Range
VIR
–0.3 to +42
V
PD
1000
mW
RJA
80
°C/W
Power Dissipation @ TA ≤ 45°C
Thermal Resistance,
Junction–to–Ambient
Operating Junction Temperature
TJ
125
°C
Storage Temperature Range
Tstg
–55 to +125
°C
Operating Ambient Temperature Range
TA
0 to +70
°C
Derating Ambient Temperature
TA
45
°C
PIN CONNECTIONS
Noninv
Input 1
Inv
Input 2
Compen/PWN
Comp Input 3
Deadtime
Control 4
CT 5
+
Error 1
Amp
-
+
2 Error
Amp
-
VCC
5.0 V
REF
≈ 0.1 V
Q2
Ground 7
C1 8
Inv
15 Input
14 Vref
Output
13 Contro
l
12 VCC
Oscillator
RT 6
Noninv
16 Input
11 C2
10 E2
Q1
9 E1
(Top View)
1. Maximum thermal limits must be observed.
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: [email protected]
Tel:886-3-3214525
Http: www.ceramate.com.tw
Page 1 of 11
Rev 1.0 Apr.19,2004
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CP494
SWITCHMODE Pulse Width Modulation Control Circuit
RECOMMENDED OPERATING CONDITIONS
Characteristics
Power Supply Voltage
Symbol
Min
Typ
Max
Unit
VCC
7.0
15
40
V
VC1, VC2
–
30
40
V
IC1, IC2
–
–
200
mA
Amplified Input Voltage
Vin
–0.3
–
VCC – 2.0
V
Current Into Feedback Terminal
lfb
–
–
0.3
mA
Reference Output Current
lref
–
–
10
mA
Timing Resistor
RT
1.8
30
500
k
Timing Capacitor
CT
0.0047
0.001
10
F
Oscillator Frequency
fosc
1.0
40
200
kHz
Collector Output Voltage
Collector Output Current (Each transistor)
ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 F, RT = 12 k, unless otherwise noted.)
For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.
Symbol
Min
Typ
Max
Unit
Vref
4.75
5.0
5.25
V
Line Regulation (VCC = 7.0 V to 40 V)
Regline
–
2.0
25
mV
Load Regulation (IO = 1.0 mA to 10 mA)
Regload
–
3.0
15
mV
Short Circuit Output Current (Vref = 0 V)
ISC
15
35
75
mA
Collector Off–State Current
(VCC = 40 V, VCE = 40 V)
IC(off)
–
2.0
100
A
Emitter Off–State Current
VCC = 40 V, VC = 40 V, VE = 0 V)
IE(off)
–
–
–100
A
Vsat(C)
Vsat(E)
–
–
1.1
1.5
1.3
2.5
IOCL
IOCH
–
–
10
0.2
–
3.5
–
–
100
100
200
200
–
–
25
40
100
100
Characteristics
REFERENCE SECTION
Reference Voltage (IO = 1.0 mA)
OUTPUT SECTION
Collector–Emitter Saturation Voltage (Note 2)
Common–Emitter (VE = 0 V, IC = 200 mA)
Emitter–Follower (VC = 15 V, IE = –200 mA)
Output Control Pin Current
Low State (VOC 0.4 V)
High State (VOC = Vref)
V
Output Voltage Rise Time
Common–Emitter (See Figure 12)
Emitter–Follower (See Figure 13)
tr
Output Voltage Fall Time
Common–Emitter (See Figure 12)
Emitter–Follower (See Figure 13)
tf
A
mA
ns
ns
2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible.
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: [email protected]
Tel:886-3-3214525
Http: www.ceramate.com.tw
Page 2 of 11
Rev 1.0 Apr.19,2004
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CP494
SWITCHMODE Pulse Width Modulation Control Circuit
ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 F, RT = 12 k, unless otherwise noted.)
For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.
Characteristics
Symbol
Min
Typ
Max
Unit
Input Offset Voltage (VO (Pin 3) = 2.5 V)
VIO
–
Input Offset Current (VO (Pin 3) = 2.5 V)
IIO
–
2.0
10
mV
5.0
250
nA
Input Bias Current (VO (Pin 3) = 2.5 V)
IIB
–
–0.1
–1.0
A
ERROR AMPLIFIER SECTION
Input Common Mode Voltage Range (VCC = 40 V, TA = 25°C)
VICR
Open Loop Voltage Gain (VO = 3.0 V, VO = 0.5 V to 3.5 V, RL = 2.0 k)
AVOL
70
95
–
dB
fC–
–
350
–
kHz
Unity–Gain Crossover Frequency (VO = 0.5 V to 3.5 V, RL = 2.0 k)
–0.3 to VCC–2.0
V
m
–
65
–
deg.
Common Mode Rejection Ratio (VCC = 40 V)
CMRR
65
90
–
dB
Power Supply Rejection Ratio (VCC = 33 V, VO = 2.5 V, RL = 2.0 k)
PSRR
–
100
–
dB
Output Sink Current (VO (Pin 3) = 0.7 V)
IO–
0.3
0.7
–
mA
Output Source Current (VO (Pin 3) = 3.5 V)
IO+
2.0
–4.0
–
mA
VTH
–
2.5
4.5
V
II–
0.3
0.7
–
mA
Input Bias Current (Pin 4) (VPin 4 = 0 V to 5.25 V)
IIB (DT)
–
–2.0
–10
A
Maximum Duty Cycle, Each Output, Push–Pull Mode
(VPin 4 = 0 V, CT = 0.01 F, RT = 12 k)
(VPin 4 = 0 V, CT = 0.001 F, RT = 30 k)
DCmax
45
–
48
45
50
50
–
0
2.8
–
3.3
–
fosc
–
40
–
kHz
Phase Margin at Unity–Gain (VO = 0.5 V to 3.5 V, RL = 2.0 k)
PWM COMPARATOR SECTION (Test Circuit Figure 11)
Input Threshold Voltage (Zero Duty Cycle)
Input Sink Current (V(Pin 3) = 0.7 V)
DEADTIME CONTROL SECTION (Test Circuit Figure 11)
Input Threshold Voltage (Pin 4)
(Zero Duty Cycle)
(Maximum Duty Cycle)
%
Vth
V
OSCILLATOR SECTION
Frequency (CT = 0.001 F, RT = 30 k)
Standard Deviation of Frequency* (CT = 0.001 F, RT = 30 k)
fosc
–
3.0
–
%
Frequency Change with Voltage (VCC = 7.0 V to 40 V, TA = 25°C)
fosc (V)
–
0.1
–
%
Frequency Change with Temperature (TA = Tlow to Thigh)
(CT = 0.01 F, RT = 12 k)
fosc (T)
–
–
12
%
Vth
5.5
6.43
7.0
V
–
–
5.5
7.0
10
15
–
7.0
–
UNDERVOLTAGE LOCKOUT SECTION
Turn–On Threshold (VCC increasing, Iref = 1.0 mA)
TOTAL DEVICE
Standby Supply Current (Pin 6 at Vref, All other inputs and outputs open)
(VCC = 15 V)
(VCC = 40 V)
Average Supply Current
(CT = 0.01 F, RT = 12 k, V(Pin 4) = 2.0 V)
(VCC = 15 V) (See Figure 12)
ICC
mA
mA
* Standard deviation is a measure of the statistical distribution about the mean as derived from the formula, N
(Xn – X)2
n=1
N–1
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: [email protected]
Tel:886-3-3214525
Http: www.ceramate.com.tw
Page 3 of 11
Rev 1.0 Apr.19,2004
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CP494
SWITCHMODE Pulse Width Modulation Control Circuit
VCC
Output Control
13
8
6
D
Oscillator
RT
CT
5
-
0.12V
4
Deadtime
Control
Q
Q1
Q
Q2 11
FlipFlop
Deadtime
Comparator
Ck
+
9
10
0.7V
+
0.7mA
+
1
PWM
Comparator
1
2
Error Amp
1
12
-
2
3
UV
Lockout
+
-
VCC
4.9V
Reference
Regulator
+
3.5V
15
Feedback PWM
Comparator Input
+
16
14
Error Amp
2
Ref.
Output
7
Gnd
This device contains 46 active transistors.
Figure 1. Representative Block Diagram
Capacitor CT
Feedback/PWM Comp.
Deadtime Control
Flip-Flop
Clock Input
Flip-Flop
Q
Flip-Flop
Q
Output Q1
Emitter
Output Q2
Emitter
Output
Control
Figure 2. Timing Diagram
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: s[email protected]
Tel:886-3-3214525
Http: www.ceramate.com.tw
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CP494
SWITCHMODE Pulse Width Modulation Control Circuit
APPLICATIONS INFORMATION
The CP494 is a fixed–frequency pulse width modulation
control circuit, incorporating the primary building blocks
required for the control of a switching power supply. (See
Figure 1.) An internal–linear sawtooth oscillator is
frequency– programmable by two external components, RT
and CT. The approximate oscillator frequency is determined
by:
fosc ≈
1.1
RT • CT
For more information refer to Figure 3.
Output pulse width modulation is accomplished by
comparison of the positive sawtooth waveform across
capacitor CT to either of two control signals. The NOR gates,
which drive output transistors Q1 and Q2, are enabled only
when the flip–flop clock–input line is in its low state. This
happens only during that portion of time when the sawtooth
voltage is greater than the control signals. Therefore, an
increase in control–signal amplitude causes a corresponding
linear decrease of output pulse width. (Refer to the Timing
Diagram shown in Figure 2.)
The control signals are external inputs that can be fed into
the deadtime control, the error amplifier inputs, or the
feedback input. The deadtime control comparator has an
effective 120 mV input offset which limits the minimum
output deadtime to approximately the first 4% of the
sawtooth–cycle time. This would result in a maximum duty
cycle on a given output of 96% with the output control
grounded, and 48% with it connected to the reference line.
Additional deadtime may be imposed on the output by
setting the deadtime–control input to a fixed voltage,
ranging between 0 V to 3.3 V.
Functional Table
Input/Output
Controls
Output Function
fout
fosc =
Grounded
Single–ended PWM @ Q1 and Q2
1.0
Push–pull Operation
0.5
@ Vref
The pulse width modulator comparator provides a means
for the error amplifiers to adjust the output pulse width from
the maximum percent on–time, established by the deadtime
control input, down to zero, as the voltage at the feedback
pin varies from 0.5 V to 3.5 V. Both error amplifiers have a
common mode input range from –0.3 V to (VCC – 2V), and
may be used to sense power–supply output voltage and
current. The error–amplifier outputs are active high and are
ORed together at the noninverting input of the pulse–width
modulator comparator. With this configuration, the
amplifier that demands minimum output on time, dominates
control of the loop.
When capacitor CT is discharged, a positive pulse is
generated on the output of the deadtime comparator, which
clocks the pulse–steering flip–flop and inhibits the output
transistors, Q1 and Q2. With the output–control connected
to the reference line, the pulse–steering flip–flop directs the
modulated pulses to each of the two output transistors
alternately for push–pull operation. The output frequency is
equal to half that of the oscillator. Output drive can also be
taken from Q1 or Q2, when single–ended operation with a
maximum on–time of less than 50% is required. This is
desirable when the output transformer has a ringback
winding with a catch diode used for snubbing. When higher
output–drive currents are required for single–ended
operation, Q1 and Q2 may be connected in parallel, and the
output–mode pin must be tied to ground to disable the
flip–flop. The output frequency will now be equal to that of
the oscillator.
The CP494 has an internal 5.0 V reference capable of
sourcing up to 10 mA of load current for external bias
circuits. The reference has an internal accuracy of 5.0%
with a typical thermal drift of less than 50 mV over an
operating temperature range of 0° to 70°C.
500 k
fosc , OSCILLATOR FREQUENCY (Hz)
Description
CT = 0.001 F
100 k
VCC = 15 V
0.01 F
10 k
0.1 F
1.0 k
500
1.0 k 2.0 k 5.0 k
10 k 20 k 50 k
100 k 200 k
RT, TIMING RESISTANCE ()
500 k 1.0 M
Figure 3. Oscillator Frequency versus
Timing Resistance
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: [email protected]
Tel:886-3-3214525
Http: www.ceramate.com.tw
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CP494
VCC = 15 V
VO = 3.0 V
RL = 2.0 k
AVOL
10
100
1.0 k
10 k
f, FREQUENCY (Hz)
0
20
40
60
80
φ
100
120
140
160
180
100 k
1.0 M
% DT, PERCENT DEADTIME (EACH OUTPUT)
120
110
100
90
80
70
60
50
40
30
20
10
0
1.0
φ , EXCESS PHASE (DEGREES)
A VOL , OPEN LOOP VOLTAGE GAIN (dB)
SWITCHMODE Pulse Width Modulation Control Circuit
20
18
16
CT = 0.001 F
14
12
10
8.0
6.0
0.001 F
4.0
2.0
0
500 k 1.0 k
50
1.9
1
40
VCC = 15 V
VOC = Vref
1.CT = 0.01 F
2.RT = 10 k
2.CT = 0.001 F
2.RT = 30 k
2
30
20
10
0
0
1.0
2.0
3.0
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
3.5
0
100
VDT, DEADTIME CONTROL VOLTAGE (IV)
Figure 6. Percent Duty Cycle versus
Deadtime Control Voltage
400
10
I CC , SUPPLY CURRENT (mA)
VCE(sat), SATURATION VOLTAGE (V)
200
300
IE, EMITTER CURRENT (mA)
Figure 7. Emitter–Follower Configuration
Output Saturation Voltage versus
Emitter Current
2.0
1.6
1.4
1.2
1.8
1.0
0.8
0.6
0.4
500 k
Figure 5. Percent Deadtime versus
Oscillator Frequency
V CE(sat) , SATURATION VOLTAGE (V)
% DC, PERCENT DUTY CYCLE (EACH OUTPUT)
Figure 4. Open Loop Voltage Gain and
Phase versus Frequency
10 k
100 k
fosc, OSCILLATOR FREQUENCY (Hz)
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
100
200
300
IC, COLLECTOR CURRENT (mA)
Figure 8. Common–Emitter Configuration
Output Saturation Voltage versus
Collector Current
400
0
0
5.0
10
15
20
25
30
35
VCC, SUPPLY VOLTAGE (V)
Figure 9. Standby Supply Current
versus Supply Voltage
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: [email protected]
Tel:886-3-3214525
Http: www.ceramate.com.tw
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40
CP494
SWITCHMODE Pulse Width Modulation Control Circuit
VCC = 15V
Error Amplifier
Under Test
+
Vin
VCC
Deadtime
Test
Inputs
Feedback
RT
CT
(+)
(-)
Error
(+)
(-)
Output
Control
Gnd
Feedback
Terminal
(Pin 3)
+
-
Vref
Other Error
Amplifier
50k
Figure 10. Error–Amplifier Characteristics
150
2W
150
2W
C1
E1
Output 1
C2
E2
Output 2
Ref
Out
Figure 11. Deadtime and Feedback Control Circuit
15V
15V
RL
68
VC
C
Each
Output
Transistor
C
Each
Output
Transistor
CL
15pF
Q
Q
E
E
VCC
10%
10%
tr
CL
15pF
90%
VEE
90%
90%
90%
VEE
RL
68
tf
Figure 12. Common–Emitter Configuration
Test Circuit and Waveform
Gnd
10%
10%
tr
tf
Figure 13. Emitter–Follower Configuration
Test Circuit and Waveform
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: [email protected]
Tel:886-3-3214525
Http: www.ceramate.com.tw
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CP494
SWITCHMODE Pulse Width Modulation Control Circuit
VO
Vref
To Output
Voltage of
System
1
Vref
2
Error
Amp
+
-
Error
Amp
3
R2
-
2
R1
Negative Output Voltage
VO = Vref
Positive Output Voltage
R2
1
+
R1
R1
R2
VO
To Output
Voltage of
System
R1
R2
VO = Vref 1 +
Figure 14. Error–Amplifier Sensing Techniques
Output
Control
Output
R1
Vref
DT
Q
RT
6
4
CT
R2
5
Output
0.001
30k
CS
Vref
Q
DT
4
RS
Max. % on Time, each output ≈ 45 -
80
1 +
R1
R2
Figure 15. Deadtime Control Circuit
C1
Q1
Output
Control
0 ≤ VOC ≤ 0.4 V
Single-Ended
Q2
Figure 16. Soft–Start Circuit
QC
E1
1.0 mA to
500 mA
C2
E2
C1
2.4 V ≤ VOC ≤ Vref
Output
Control
Q1
Push-Pull
E1
1.0 mA to
250 mA
C2
Q2
QE
E2
1.0 mA to
250 mA
Figure 17. Output Connections for Single–Ended and Push–Pull Configurations
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: [email protected]
Tel:886-3-3214525
Http: www.ceramate.com.tw
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CP494
SWITCHMODE Pulse Width Modulation Control Circuit
Vref
6
5
RT
RT
VCC
RS
Master
CT
Vin > 40V
CT
1N975A
12
VZ = 39V
5.0V
Ref
Vref
270
6
5
RT
Slave
(Additional
Circuits)
CT
Gnd
7
Figure 18. Slaving Two or More Control Circuits
Figure 19. Operation with Vin > 40 V Using
External Zener
+Vin = 8.0V to 20V
12
1
2
1M
33k
0.01 0.01
3
15
16
47
VCC
+
C1
-
Tip
32
CP494
Comp
-
C2
+
8
T1
OC VREF DT
13
14
4.7k
4.7k
+
4
CT
5
E1
RT Gnd
6
7
9
E2
10
11
Tip
32
+VO = 28 V
IO = 0.2 A
1N4934
22
k
L1
+
+
50
25V
47
50
35V
4.7k
1.0
1N4934
+
50
35V
240
10
10k
0.001
15k
All capacitors in F
Figure 20. Pulse Width Modulated Push–Pull Converter
Test
Conditions
Results
Line Regulation
Vin = 10 V to 40 V
14 mV 0.28%
Load Regulation
Vin = 28 V, IO = 1.0 mA to 1.0 A
3.0 mV 0.06%
Output Ripple
Vin = 28 V, IO = 1.0 A
65 mV pp P.A.R.D.
Short Circuit Current
Vin = 28 V, RL = 0.1 1.6 A
Efficiency
Vin = 28 V, IO = 1.0 A
71%
L1 - 3.5 mH @ 0.3 A
T1 - Primary: 20T C.T. #28 AWG
T1 - Secondary: 12OT C.T. #36 AWG
T1 - Core: Ferroxcube 1408P-L00-3CB
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: [email protected]
Tel:886-3-3214525
Http: www.ceramate.com.tw
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Rev 1.0 Apr.19,2004
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CP494
SWITCHMODE Pulse Width Modulation Control Circuit
1.0mH @ 2A
+Vin = 10V to 40V
+VO = 5.0 V
Tip 32A
IO = 1.0 A
47
150
12
8
VCC
50
50V
47k
0.1
11
C1
C2
+
CP494
CT
5
RT
4
13
-
2
+
1
Vref
D.T. O.C. Gnd E1
6
7
9
E2
3
Comp
1.0M
5.1k
5.1k
14
- 15
16
+
500
10V
MR850
5.1k
+
+
10
50
10V
150
0.001
47k
0.1
Figure 21. Pulse Width Modulated Step–Down Converter
Test
Conditions
Results
Line Regulation
Vin = 8.0 V to 40 V
3.0 mV
0.01%
Load Regulation
Vin = 12.6 V, IO = 0.2 mA to 200 mA
5.0 mV
0.02%
Output Ripple
Vin = 12.6 V, IO = 200 mA
Short Circuit Current
Vin = 12.6 V, RL = 0.1 Efficiency
Vin = 12.6 V, IO = 200 mA
40 mV pp
P.A.R.D.
250 mA
72%
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: [email protected]
Tel:886-3-3214525
Http: www.ceramate.com.tw
Page 10 of 11
Rev 1.0 Apr.19,2004
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CP494
SWITCHMODE Pulse Width Modulation Control Circuit
CP494N
CP494
10.0 ± 0.2
19.4 ± 0.3
9
0.3 ± 0.1
0.5 ± 0.1
1.5 ± 0.1
7.62
2.54
9
1
8
1.27
0.4 ± 0.1
0.15 ± 0.1
6.2 ± 0.3
8
16
4.4 ± 0.2
1
0.11
0.51Min.
3.2 ± 0.2 4.25 ± 0.3
6.5 ± 0.3
16
0.3Min.
0° ~ 15°
0.15
DIP16
SOP16
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: [email protected]
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Http: www.ceramate.com.tw
Page 11 of 11
Rev 1.0 Apr.19,2004
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