LX1692B ® TM Full Bridge Resonant CCFL Controller P RODUCTION D ATA S HEET KEY FEATURES DESCRIPTION The LX1692B regulates the CCFL brightness in three ways: analog dimming, digital dimming, or combined analog and digital dimming methods simultaneously to achieve the widest dimming range (> 60 to 1). The LX1692B can accept a brightness control signal that is either an analog voltage or a low frequency PWM. The LX1692B also features integrated gate drivers for the four external power MOSFETs. An integrated 4V LDO powers all internal control circuitry greatly simplifying supply voltage requirements. The LX1692B is available in a 20Pin TSSOP and SOIC. IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com Protected by U.S. Patents: 5,615,093; 5,923,129; 5,930,121; 6,198,234; 7,112,929; Patents Pending PRODUCT HIGHLIGHT For Wide Voltage Range Inverter Application (7V to 22V) Low Stress to Transformers Wide Dimming Range Analog Dimming: >3 to 1 Digital Dimming : >20 to 1 Combined: >60 to 1 Programmable Burst Dimming Frequency Programmable Time Out Protection Fixed Operating Frequency Open Lamp Voltage Protection, Short Lamp Protection, Arc Protection1 WWW . Microsemi .C OM Microsemi’s LX1692B is a cost reduced, third generation CCFL (Cold Cathode Fluorescent Lamp) controller. The integrated controller is optimized to drive CCFL’s using resonant full bridge inverter topology. Resonant full bridge topology provides near sinusoidal waveforms over a wide supply voltage range in order to maximize the life of CCFL lamps, control EMI emissions, and maximize efficiency. This new architecture also provides a wide dimming range. The LX1692B includes safety features that limit the transformer secondary voltage and protect against fault conditions which include open lamp, broken lamp, and short-circuit faults. BENEFITS Even Display Light Distribution Longer Lamp Life with Optimized Lamp Current Amplitude Reduced Operating Voltage Lowers Corona Discharge and Prolongs Module Life High “Nits / Watt” Efficiency Makes Less Heat and Brighter Displays APPLICATIONS LCD TV LCD Monitor VSUPPLY LX1692B A I_R B C_BST C C_TO D Part DUAL FET Balancer C_R DUAL FET BRITE_IN EA_OUT ISNS LX1692B PACKAGE ORDER INFO TA (°C) -20 to +85 PW Plastic TSSOP 20-Pin DW Plastic SOIC 20-Pin RoHS Compliant / Pb-free RoHS Compliant / Pb-free LX1692BIPW LX1692BIDW Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. LX1692BIPW-TR) 1 Arc protection is provided if the arcing level is enough to be trigged. Copyright © 2005 Rev. 1.1, 12/20/2006 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 1 LX1692B ® TM Full Bridge Resonant CCFL Controller P RODUCTION D ATA S HEET ABSOLUTE MAXIMUM RATINGS PACKAGE PIN OUT Note: Exceeding these ratings could cause damage to the device. All voltages are with respect Ground. Currents are positive into, negative out of specified terminal. to THERMAL DATA DW Plastic SOIC 20-Pin THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA 85°C/W VDDA C_R C_BST C_TO I_R ENABLE BRITE_A VIN_SNS BRITE_D VCOMP 1 20 10 11 VDDP AOUT BOUT GND COUT DOUT ISNS OV_SNS ICOMP OC_SNS PW PACKAGE (Top View) VDDA C_R C_BST C_TO I_R ENABLE BRITE_A VIN_SNS BRITE_D VCOMP 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VDDP AOUT BOUT GND COUT DOUT ISNS OV_SNS ICOMP OC_SNS WWW . Microsemi .C OM Supply Input Voltage(VDDP)........................................................................................ 6V VIN_SNS ..................................................................................... -0.3V to VDDP+0.5V Digital Input (ENABLE)................................................................. -0.3V to VDDP+0.5V Analog Inputs (ISNS, OV_SNS, OC_SNS)clamped to ±14V Max Peak Current ±100mA Analog Inputs (BRITE_A, BRITE_D)........................................... -0.3V to VDDP +0.5V Digital Outputs (AOUT, BOUT, COUT, DOUT).......................... -0.3V to VDDP +0.5V Analog Outputs (I_R, ICOMP, VCOMP) ..................................... -0.3V to VDDP + 0.5V Maximum Operating Junction Temperature .............................................................150°C Storage Temperature Range........................................................................... -65 to 150°C Peak Package Solder Reflow Temp. (40 seconds maximum exposure)........260°C(+0, -5) DW PACKAGE (Top View) PW Plastic TSSOP 20-Pin THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA 99°C/W RoHS / Pb-free 100% Matte Tin Lead Finish Junction Temperature Calculation: TJ = TA + (PD x θJA). The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. FUNCTIONAL PIN DESCRIPTION Description C_R Lamp Frequency Programming Capacitor Pin – lamp running frequency is set by the combination of C_R and I_R. The internal lamp current oscillator frequency can be forced to follow an external clock signal at this pin. In this case, the programmed frequency must be lower than the external frequency. Minimum pulse width for external synch signal is 1µsec. Maximum duty is 50% I_R Current Reference Resistor Input. Connects to an external resistor that determines the magnitude of the internal bias currents. The I_R pin is a DC reference voltage of 1V. This voltage should only be used for its intended function. The reference current established at this pin, by connecting an external resistor, is used to charge a capacitor at the C_R pin. The nominal lamp frequency can be adjusted by varying this resistor value in the range of 20K to 100K Ohms. (Note: C is in pF, R is in KΩ , Freq is in kHz). 242 × 10 3 FLAMP = CC _ R ⋅ RI _ R Other reference currents derived from I_R are used for the digital dimming burst oscillator and the strike time out function. Copyright © 2005 Rev. 1.1, 12/20/2006 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 2 PACKAGE DATA Name LX1692B ® TM Full Bridge Resonant CCFL Controller P RODUCTION D ATA S HEET FUNCTIONAL PIN DESCRIPTION (CONTINUED) C_BST Description WWW . Microsemi .C OM Name Burst dimming mode frequency set capacitor. Internal bias currents set via the I_R pin are scaled down and used to charge and discharge the capacitor connected at the C_BST pin. The voltage at the C_BST pin is a sawtooth waveform displaying a voltage that ranges from 0.5V to 2.5V. The frequency of the PWM for digital dimming is set by the I_R and C_BST pins. 98039 where RI_R is in KΩ and CC_BST is in nF, FDIM is Hz FDIM = CC _ BST .RI _ R The internal burst oscillator frequency can also be forced to follow an external clock signal at this pin. In this case, the programmed frequency must be lower than the external frequency. C_TO Time Out set capacitor. An external capacitor is charged with an on chip current source to create a voltage ramp. Over voltage fault shutdown is disabled until C_TO voltage rises above 3.5V, providing a user programmed strike interval. Strike Interval time is t = 0.035 RI _ R ⋅ CC _ TO where RI_R is in KΩ and CC_TO is in µF VDDA Analog Voltage Regulator Output. This output pin is used to connect an external capacitor to stabilize and filter the on-chip LDO regulator. The input of the LDO is the switched VDDP supply. The LDO output is nominally 4.0V and is used to drive all circuitry except the output buffers at AOUT, BOUT, COUT and DOUT. The drop out voltage is typically 0.05V at 2mA; the average internal load. This output can supply up to a 5mA external load. The output capacitor should be a 100nF ceramic dielectric type. ENABLE Chip Enable Input. If logic high, all functions are enabled. If logic low, internal power is disconnected from the VDDP pin, disabling all functions. Logic threshold is 1.85V/1.35V maximum over supply and temperature range. Maximum current into VDDP when ENABLE < 0.8V, is 50µA. ENABLE may be connected directly to VDDP if the disable function is not used. BRITE_D Brightness Control Input for digital dimming. The input signal can be a DC voltage or low frequency PWM signal. Active DC voltage range is 0.5V to 2.5V. Signals above 2.5V makes continuous operation, voltages between 0.5V and 2.5V makes PWM digital dimming. Digital dimming pulse width varies from 100% duty at 2.5V to 0% duty at 0.5V. A minimum BRITE_D input voltage (externally supplied) of approximately TBDV is required to prevent fault stop. PWM inputs from either 3.3V or 5V logic are permissible. Frequency may range up to 1KHz. Max jitter of more than 1µs/V on this input may cause noticeable lamp flicker. Refer to Dimming configuration Table for setting. VCOMP Voltage loop compensation pin for transformer output voltage regulation. An external capacitor is connected from this pin to Ground to adjust loop response. An external resistor divider can be connected to limit the maximum output duty cycle while the IC is operating in strike mode. BRITE_A Brightness control input for analog dimming. The input signal can be a DC voltage or a PWM signal that has been externally filtered to DC. Active DC voltage range is 0 to 2V. Signals above 2V and below 0.45V are clamped and do not change amplitude of output current. VIN_SNS Input voltage sense pin. An external resistor and capacitor are connected to this pin to control slope of the oscillator timing ramp. Ramp slope becomes steeper as the external bridge power supply increases providing rapid line voltage transient response. Copyright © 2005 Rev. 1.1, 12/20/2006 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 PACKAGE DATA ICOMP Error Amp Output for the lamp current regulator. This error amplifier is a gm type and does not require an external capacitor for stability. An External capacitor is connected from this pin to Ground to adjust loop response of the inverter module. This capacitor value can vary from 0.1nF to 33nF as required by specific applications. Error amplifier output voltage is not allowed to exceed the peak voltage of its associated comparator ramp by more than 10%. Page 3 LX1692B ® TM Full Bridge Resonant CCFL Controller P RODUCTION D ATA S HEET FUNCTIONAL PIN DESCRIPTION (CONTINUED) Description OC_SNS Over current sense input. The OC_SNS input is compared to a 2V reference. The comparator output shuts off the PWM outputs to prevent possible secondary failures. The input voltage at this pin is not rectified. Normal operating voltage levels will be in the range of ±0.5V to VDDP. An abnormal voltage can operate continuously as high as ±7V peak under load fault conditions. Transients under fault conditions up to ±11 VPEAK are permitted. An input voltage above 4 peak but less than ±11V peak may cause saturation but will not cause malfunction, phase reversal, or reliability issues with the IC. OV_SNS Over Voltage Sense Input. This input pin monitors a voltage divider (approximately 1000:1) placed across the lamp. The open lamp voltage regulator uses it to regulate open circuit voltage. During both run and strike modes, fault detection comparators monitor voltage amplitude to determine if load opens occur. See functional description section for details on internal circuit operation. Frequency range of the input signal is from DC to 150KHz. Normal operating voltage levels will be in the range of ±0.5 to ±VDDP peak, centered about +0.2 VDC. An abnormal voltage can operate continuously as high as ±7V peak under load fault conditions. Transients under load fault conditions up to ±11V peak are permitted. An input voltage above ±4Vpk may cause saturation, but will not cause malfunction, phase reversal, or reliability issues with the IC ISNS Current Sense Input. The ISNS input is full wave rectified by an On-Chip circuit, then presented to the inverting input of the current error amplifier. Frequency range of the input signal is DC to 200KHz. The ISNS pin also monitors lamp current to determine if the lamp is ignited. If a single cycle at the ISNS pin is greater than 1V, the strike / run flip flop is clocked to the RUN state and threshold of the strike comparator is lowered to 0.3V. During RUN mode current levels are continuously monitored to detect less than 0.3V. A counter clocked by RMPD_OUT is reset each time current is sensed at this input. If the counter overflows (256 counts) a fault latch is set which shuts down the IC. This fault is expected to occur when the lamp is shorted to ground through an impedance of less than 2K ohms or the ISNS resistor itself is shorted. The counter is inhibited during digital dimming off time. Normal operating voltage levels will be in the range of ±0.5V to ±5.5V. An abnormal voltage can operate continuously as high as ±7V peak under load fault conditions. Transients under fault conditions up to ±11 VPK are permitted. Input voltages up 4V peak are linearly rectified. An input voltage above ±4V peak but less than ±11V peak may cause saturation but will not cause malfunction, phase reversal, or reliability issues with the IC. DOUT A buffer P-FET driver output. Has a 20K pull up, RDSON nominal = 30 Ω COUT A buffer P-FET driver output. Has a 20K pull up, RDSON nominal = 30 Ω BOUT A buffer N-FET driver output. Has a 20K pull down, RDSON nominal = 30 Ω AOUT A buffer N-FET driver output. Has a 20K pull down, RDSON nominal = 30 Ω GND Ground VDDP Input Supply Voltage, 4.5V to 5.5V input range. VDDP is switched (see ENABLE) to remove power from chip. An LDO regulator follows the switch and generates 4.0VDC. The output driver stages are powered directly from the VDDP input. The output capacitor should be a 1000nF or larger ceramic dielectric type. WWW . Microsemi .C OM Name PACKAGE DATA Copyright © 2005 Rev. 1.1, 12/20/2006 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 4 LX1692B ® TM Full Bridge Resonant CCFL Controller P RODUCTION D ATA S HEET ELECTRICAL CHARACTERISTICS Parameter ` POWER Power Supply Input Voltage Power Supply Output Voltage VDDP Operating Current VDDP Operating Current ` ` ` ` ` VDDP VDD_A ISB IBB ENABLE INPUT ENABLE Logic Threshold VTH_EN ENABLE threshold Hysteresis VH_EN ENABLE High VEN_HIGH ENABLE Low VEN_LOW Sleep Mode Current IDD_SLEEP Input Resistance RENR UNDER VOLTAGE LOCKOUT UVLO Threshold VDDP VTH_UVLO_P UVLO Hysteresis VH_UVLO BRIGHTNESS CONTROL BRITE_A Voltage Range VR_BR_A Full Brightness BRITE_A Input VBR_FULL _A Full Darkness BRITE_A Input VDARK_FULL_A Full Darkness BRITE_A input Offset VDARKFULL_OS BRITE_D Voltage Range VR_BR_D Full Brightness BRITE_D Input VBR_FULL _D Full Darkness BRITE_D Input VDARK_FULL_D BURST RAMP GENERATOR Ramp Valley Voltage VRVV Ramp Peak Voltage VRPV Ramp Frequency FRAMP Burst Duty Cycle Range BRITE_D to DIMPWM Jitter JBDD Burst PWM min Duty Resolution DRBST LAMP FREQUENCY GENERATOR Lamp Frequency Range FLAMP Lamp Ramp Frequency Lamp Ramp Frequency Regulation FLAMP FLAMP_REG Ramp Valley Voltage Ramp Peak Voltage Ramp PWM Jitter VIN_SNS RAMP VLRVV VLRPV LFJ Ramp Peak Clamp Voltage VRPCV VIN_SNS Discharge Current IVRVV Copyright © 2005 Rev. 1.1, 12/20/2006 Test Conditions VDDP = 4.5V to 5.5V, I Load = 5 mADC fLAMP = 62.5kHz, TA=25°C CAOUT = CBOUT= CCOUT = CDOUT=2000pF, fLAMP = 62.5kHz Min 4.5 3.8 3.8 1.6 LX1692B Typ Max Rising edge 5.5 4.2 6.8 V V mA 10 15 mA 1.85 500 2.0 V mV V V µA KΩ 20 100 3.8 VDDP 0.8 50 4.2 V mV VDDP 2.1 0.55 VDDP 2.63 0.67 V V V V V V V 0.67 2.63 270 100 3 1 V V Hz % µs % 150 kHz 200 VR_BR_D = VDDA, TA=25°C VR_BR_D = VDDA VR_BR_D = VDDA, BRITE_A = 0V VR_BR_A = VDDA VR_BR_A = VDDA, TA=25°C VR_BR_A = VDDA C_BST = 10nF, I_R = 40K, Ta=25°C 0 1.9 0.35 0.4 2.37 0.43 0.43 2.37 230 0 C_BST = 10nF, BRITE_D = 2.4V 2 0 0.45 2.5 0.55 0.55 2.5 250 1 30 Lamp Ignited, Run Mode, TA = 25°C, I_R = 40K, C_R = 100pF 4.5 > VDDP < 5.5V, TA = 25°C VDDP = 5.5V 59.3 62.5 65.7 kHz ±0.5 ±0.1 %/V %/°C V V µs 0.2 2.0 1 VIN = 8V, C_P = C_R = 100pF, R_P = 100K VDDP = 5V 5 7 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Units 4.0 5.3 2.4 0 VENABLE = 0V 70°C except where 12.5 VDDP +0.9 18 V mA Page 5 ELECTRICALS ` Symbol ≤ WWW . Microsemi .C OM Unless otherwise specified, the following specifications apply over the operating ambient temperature -20°C ≤ TA otherwise noted and the following test conditions:. LX1692B ® TM Full Bridge Resonant CCFL Controller P RODUCTION D ATA S HEET ELECTRICAL CHARACTERISTICS (CONTINUED) Parameter ` ` ` BIAS BLOCK Voltage at Pin I_R Pin I_R Max Source Current STRIKING BLOCK ISNS Input Strike Threshold Min ISNS Input Threshold Lamp current Regulation reference voltage during strike period PROTECTION Open Lamp Detection Enable Threshold Over Voltage Detection Threshold Over Current Detection Threshold ` V_IR IMAX_IR Test Conditions Min 70°C except where LX1692B Typ Max I_R = 40K 1.0 75 Units V µA VISNS_STK VISNSMIN 0.9 0.27 1.0 0.3 1.1 0.33 Vpk Vpk VREF_STK 1.8 2 2.2 V 3.5 VFEN VOVSTH VOCTH Open Lamp Time Out ( After Ignition) TOL Over Current Time Out TOC 4.5V > VDDP < 5.5V, ISNS = 0V, , C_TO = 1µF, I_R = 40K, VC_TO > 3.5V VISNS < 0.3V, VC_TO >3.5V, Lamp Freq = 60Khz VOC_SNS >2.0V, Lamp Freq = 60Khz Over Voltage Time Out TOSL VOV_SNS > 2.9V, pulsed input Open Lamp Striking Time Out ` Symbol ≤ TSTKO WWW . Microsemi .C OM Unless otherwise specified, the following specifications apply over the operating ambient temperature -20°C ≤ TA otherwise noted and the following test conditions:. V 3.0 1.8 3.2 2.0 3.4 2.2 V V 1.2 1.4 1.6 sec 2.1 msec 500 µsec 16 count PWM BLOCK VR_ISNS OC_SNS Input Voltage Range OV_SNS Input Voltage Range VIN_SNS Input Voltage Range ICOMP Error Amp Transconductance ICOMP Output Source Current ICOMP Output Sink Current ICOMP Output Voltage Range ISNS-BRITE_A Input Offset Voltage ICOMP Discharge Current ICOMP to A/B Output Propagation Delay VCOMP High voltage VCOMP Sink Current OUTPUT BUFFER BLOCK Output Resistance Output Resistance Pull Up Resistance Pull Down Resistance Output voltage High Output voltage low Min off time VR_OC VR_OV VR_VINS Copyright © 2005 Rev. 1.1, 12/20/2006 Maximum recommended for linear operation of error amplifier GM_EAMP ISNS =1.5V IS_EAMP ISK_EAMP VR_EAMP VOS_EAMP ID_ICOMP ΔV_EAIN = 1.0V ΔV_EAIN = 1.0V ISNS=1.5V, TA=25°C -4 +4 Vpk -4 -4 -0.3 +4.0 +4.0 VDDP Vpk Vpk Vpk 410 µmho 100 220 100 100 0 -100 0 10 VDDA 100 1100 TD_COMP VHI_VCOMP ILO_VCOMP VOVSNS = 0V, VVCOMP = 2V RON_SRC RON_SINK RUP RDN VOH VOL tOFF VDDP = 5V VDDP = 5V COUT, DOUT Aout, BOUT CAOUT = CBOUT= CCOUT = CDOUT=2000pF CAOUT = CBOUT= CCOUT = CDOUT=2000pF ns VDDA 1.5 30 30 20 20 VDDP-0.4 0 200 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 320 µA µA V mV mA VDDP 0.4 550 V mA Ω Ω KΩ KΩ V V ns ELECTRICALS ISNS Input Voltage Range Page 6 LX1692B ® TM Full Bridge Resonant CCFL Controller P RODUCTION D ATA S HEET SIMPLIFIED BLOCK DIAGRAM WWW . Microsemi .C OM VDDA VDDP 4V LDO VDDA VDDP Sleep Logic SLEEP AOUT BOUT Ramp OCS C_R VDDA VDDP PWM Block RMP_RST Output Driver GND COUT DOUT Busrt OSC C_BST C_BST VDDA Fault Detection & Timer Logic 0.5V C_TO 3.5V VDDP VDDA 1V LDET I_R 1.0V / 0.3V ISNS SLEEP ENABLE FWR DIM 2V 2.0V BRITE_A 0 SEL 1 OUT 3.2V OV_SNS 0.45V VIN_SNS Timing RMP_RST C_BST ICOMP BLOCK DIAGRAM BRITE_D Control Logic OC_SNS DIM 2.0V VCOMP Figure 1 – Block Diagram Copyright © 2005 Rev. 1.1, 12/20/2006 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 7 LX1692B ® TM Full Bridge Resonant CCFL Controller P RODUCTION D ATA S HEET STATE DIAGRAM WWW . Microsemi .C OM VIN QD QC COUT_P AOUT DOUT_P DOUT_P COUT_P T1 BOUT C1 AOUT 0 BOUT QA 56 78 0 1234 5 QB VIN VIN VIN T1 T1 T1 C1 C1 C1 T0-T1 T1-T2 T2-T3 VIN VIN VIN T1 C1 T1 T1 C1 T3-T4 C1 T4-T5 T5-T6 VIN VIN T1 T1 C1 C1 DIAGRAMS T6-T7 1234 T7-T8 Figure 2 – State Diagram Copyright © 2005 Rev. 1.1, 12/20/2006 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 8 LX1692B ® TM Full Bridge Resonant CCFL Controller P RODUCTION D ATA S HEET TYPICAL APPLICATION WWW . Microsemi .C OM VIN VIN R1 22K C1 470µF 16V BZX84C5V1 Z1 Q2 FDS6675A R2 22K C2 0.1µF BZX84C5V1 Z2 Q2 FDS6675A C3 0.1µF Q3 FDS6612A T1 TBD HV1A Q4 FDS6612A C4 2.2pF RTN1A VAF C5 1nF C6 10µF HV2A I_SNS1 RTN2A R3 300R C7 10µF T2 TBD HV1B VDDP RTN1B C10 2.2pF +5V C8 1µF C9 1.0µF C11 100pF C12 10nF C14 1µF VIN I_SNS2 VDDA VDDP C_R AOUT C_BST BOUT C_TO GND R4 120K I_R EN BRTA R6 40K Part R5 300R COUT ENABLE DOUT BRITE_A ISNS BRITE_D VCOMP D2 BAT54C R7 3R C16 2.2nF T3 T09040A VAF VBF ICOMP R8 10K D3 BAS40 OC_SNS LX1692BIPW C15 100pF HV2B RTN2B D1 BAT54C VIN_SNS OV_SNS BRT_D VBF C13 1nF I_SNS1 C17 220pF I_SNS2 D4 BAT54C R9 15K R10 3R T4 T09040A Figure 3 – Schematic APPLICATIONS Copyright © 2005 Rev. 1.1, 12/20/2006 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 9 LX1692B ® TM Full Bridge Resonant CCFL Controller P RODUCTION D ATA S HEET FUNCTIONAL DESCRIPTION OPEN LAMP Two operating modes, Strike and Run, are employed by the LX1692B. Upon power up or ENABLE going true, strike mode is entered. After a successful strike, e.g., lamp is ignited, run mode is entered. If ignition is unsuccessful, or if the lamp extinguishes while running, a fault is declared and the controller automatically shuts down. When the IC is first powered on or enabled, the inverter output voltage must be made higher than the normal operating voltage of the lamp to cause ignition. The lamp may not ignite immediately when specified strike voltage is applied. It is customary to apply strike voltage for from 0.3 to 3 seconds to insure ignition of cold, dark, or aged lamps. The LX1692B has a programmable time out for this purpose. During strike time out, open lamp voltage is regulated to a value programmed by a voltage divider across the lamp and sensed at the OV_SNS pin. OSCILLATOR CHARACTERISTICS The main oscillator in the LX1692B has a fixed frequency loop. The fixed frequency loop is user set via the I_R resistor and the C_R capacitor value. STRIKING THE LAMP Lamp ignition is determined by monitoring the lamp current feedback voltage at the ISNS pin. If less than 1.0V during the strike period, the lamp is considered not ignited and Strike mode continues until ignition is detected or strike time out (approximately 1 - 2 seconds) is reached. If greater than 1.0V, strike is declared and a latch is set. The IC is now in “run” mode. And threshold voltage for strike detect is reduced to 0.3V to permit a minimum 3:1 analog dimming ratio to be achieved. FAULT PROTECTION The LX1692B has shut down protection for all common lamp fault conditions. These include the following: a. b. c. d. Open or broken lamp High Voltage Arcing on transformer secondary side Short from high side of lamp to ground Short from low side of lamp to ground ( current sense resistor shorted) Copyright © 2005 Rev. 1.1, 12/20/2006 Strike time out is programmed by selecting the capacitor value at the C_TO pin. If the lamp has not ignited before the end of strike time out, a fault is declared and the IC outputs are latched off. HIGH VOLTAGE ARC OR OVER PROGRAMMED VOLTAGE If a high voltage arc occurs due to intermittent lamp contacts or component failure, if the over voltage feedback divider is improperly designed, or if the open lamp voltage regulation circuitry fails, the peak voltage on the OV_SNS pin will rise above + 3.2 VDC. This creates a pulse that increments a 4 bit accumulating counter. After 16 events are counted, an open lamp fault is declared and the IC outputs are latched off. This fault is enabled at all times, including during lamp striking. The 4 bit counter is reset by signal C_BST which typically operates at 100 to 300 Hz. Also, OVSNS pin voltage is greater than 3.2V, then ICOMP pin will be forced to discharge to 0V about 600ns. OPEN LAMP VOLTAGE REGULATION The open lamp voltage regulator regulates the peak voltage on the OV_SNS pin to +/- 1.97 volts, + the 0.2 volt offset, with a maximum tolerance +/-8% (+/- 158 mV). Assuming an additional +/- 5% tolerance for each of the two capacitors or resistors in the high voltage divider, maximum open lamp voltage tolerance at the system level is +/- 18%. At the high side of tolerance, OV_SNS peak voltage is +2.42V, on the low side of tolerance, OV_SNS input voltage will be regulated at +1.914 Vpk. If tighter total voltage regulation is needed in a given application, the feedback divider can be made with 1% resistors. Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 1 DESCRIPTION Three inputs from the lamp are monitored to detect these conditions, ISNS, OV_SNS, and OC_SNS. Fault protection is designed to prevent fire or smoke from being generated by terminating inverter operation in the event of failures in the high voltage components and the power FET’s. All fault shut down events can only be reset by ENABLE or VDDP cycling. WWW . Microsemi .C OM OPERATING MODES LX1692B ® TM Full Bridge Resonant CCFL Controller P RODUCTION D ATA S HEET FUNCTIONAL DESCRIPTION (CONTINUED) OR BROKEN LAMP AFTER SUCCESSFUL IGNITION After run mode is entered, an intermittent or open lamp problem can also be detected at the ISNS input. After ignition, peak voltage on the ISNS input is dependent on lamp current amplitude and voltage on the BRITE_A pin. I_SNS signal amplitude should be designed to be greater than +/- 400 mVPK (280 mVRMS) to insure a false open lamp fault shut down does not occur. A comparator monitors ISNS and generates a reset pulse to a watch dog timer for any peak voltage > 0.3V. The watch dog, a 9 bit binary counter, is reset once every cycle of I_SNS voltage. If lamp current flowing through the ISNS resistor is too low (e.g., voltage is less than 0.3V peak), reset pulses are not generated and the counter is allowed to overflow and set the fault latch. Nominal short circuit duration is 500 micro seconds when operating at 65 KHz. SHORT CIRCUITS ACROSS THE LAMP TERMINALS, SHORTS FROM THE HIGH VOLTAGE TERMINAL TO GROUND AND SHORT CIRCUITS FROM GROUND TO THE LOW SIDE LAMP TERMINAL. A Short to ground from the lamp return terminal also shorts out the lamp current sense resistor, removing current feedback to the controller. This short is detected as a rise in voltage across the OC_SNS resistor which is located on the normally grounded side of the HV transformer secondary. A comparator senses peak voltage > 2.0Vdc at the OC_SNS pin. This comparator clocks the 4 bit watch dog timer described above in the open lamp fault logic. Sixteen events during a single cycle of the C_BST signal will overflow the watchdog counter and cause an over current shut down during either strike or run mode. WWW . Microsemi .C OM INTERMITTENT UNDER VOLTAGE LOCKOUT Keeps chip outputs active off until VDDA is high enough to insure stable operation. ON CHIP LDO REGULATOR Output voltage is 4.0 +/-5%. Supplies all internal circuitry except output driver stage. Capable to source 5mA to external circuitry. DIMMING MODES Separate input pins are available for digital and analog dimming modes for maximum flexibility. See dimming truth table below. Digital dimming rise and fall times can be controlled by the ICOMP capacitor (See Dimming Modes Table). DIMMING MODES MODE BRITE A BRITE D ISNS CBST I Range DC voltage controlled analog 0 – 2V VDDA cap 3:1 External PWM controlled digital VDDA PWM cap 60:1 DC voltage controlled digital VDDA 0.5-2.5V Cap 30:1 Analog + voltage controlled Digital 0 -2V 0.5-2.5V Cap 60:1 Note: For Reverse analog dimming, BRITE_A signal inversion must occur external to the controller DESCRIPTION Copyright © 2005 Rev. 1.1, 12/20/2006 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 2 LX1692B ® TM Full Bridge Resonant CCFL Controller P RODUCTION D ATA S HEET PACKAGE DIMENSIONS 20-Pin Thin Small Shrink Outline (TSSOP) Dim A A1 A2 b c D E E1 e L Θ1 *LC 3 21 P E F D A H SEATING PLANE DW WWW . Microsemi .C OM PW B L G C M MILLIMETERS MIN MAX 1.10 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 6.40 6.60 6.25 6.55 4.30 4.50 0.65 BSC 0.45 0.75 0° 8° 0.10 INCHES MIN MAX 0.043 0.002 0.006 0.031 0.041 0.007 0.012 0.004 0.008 0.252 0.260 0.246 0.258 0.169 0.177 0.026 BSC 0.018 0.030 0° 8° 0.004 20-Pin Plastic (SOWB) Wide Body SOIC A 20 11 P B 1 G 10 D F L C Seating Plane J M K MILLIMETERS MIN MAX 12.65 12.85 7.49 7.75 2.35 2.65 0.25 0.46 0.64 0.89 1.27 BSC 0.23 0.32 0.10 0.30 8.13 8.64 0° 8° 10.26 10.65 0.10 − INCHES MIN MAX 0.498 0.506 0.295 0.305 0.093 0.104 0.010 0.018 0.025 0.035 0.050 BSC 0.009 0.013 0.004 0.012 0.320 0.340 0° 8° 0.404 0.419 0.004 − *Lead Coplanarity Note: 1. Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(.006”) on any side. Lead dimension shall not include solder coverage. Copyright © 2005 Rev. 1.1, 12/20/2006 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 3 MECHANICALS Dim A B C D F G J K L M P *LC LX1692B TM ® Full Bridge Resonant CCFL Controller P RODUCTION D ATA S HEET NOTES WWW . Microsemi .C OM NOTES PRODUCTION DATA – Information contained in this document is proprietary to Microsemi and is current as of publication date. This document may not be modified in any way without the express written consent of Microsemi. Product processing does not necessarily include testing of all parameters. Microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time. Copyright © 2005 Rev. 1.1, 12/20/2006 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 4