CM6800A LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO GENERAL DESCRIPTION FEATURES The CM6800A is a controller for power factor corrected, Patent Number #5,565,761, #5,747,977, #5,742,151, switched mode power suppliers. Power Factor Correction #5,804,950, #5,798,635 (PFC) allows the use of smaller, lower cost bulk capacitors, Pin to pin compatible with ML4800 and FAN6800 reduces power line loading and stress on the switching Additional folded-back current limit for PWM section. FETs, and results in a power supply that fully compiles with 23V Bi-CMOS process IEC-1000-3-2 specifications. Intended as a BiCMOS VIN OK turn on PWM at 2.25V instead of 1.5V(ML4800). version Internally synchronized leading edge PFC and trailing edge of the industry-standard ML4824, CM6800A includes circuits for the implementation of leading edge, PWM in one IC average current, “boost” type power factor correction and a Slew rate enhanced transconductance error amplifier for trailing edge, pulse width modulator (PWM). Gate-driver ultra-fast PFC response with 1A capabilities minimizes the need for external driver Low start-up current (100 μ A typ.) circuits. Low power requirements improve efficiency and Low operating current (3.0mA type.) reduce component costs. Low total harmonic distortion, high PF An over-voltage comparator shuts down the PFC section in Reduces ripple current in the storage capacitor between the PFC and PWM sections the event of a sudden decrease in load. The PFC section Average current, continuous or discontinuous boost leading also includes peak current limiting and input voltage edge PFC brownout protection. The PWM section can be operated in VCC OVP Comparator, Low Power Detect Comparator current or voltage mode, at up to 250kHz, and includes an PWM configurable for current mode or voltage mode accurate 50% duty cycle limit to prevent transformer operation saturation. CM6800A includes an additional folded-back current limit Current fed gain modulator for improved noise immunity Brown-out control, over-voltage protection, UVLO, and soft start, and Reference OK for PWM section to provide short circuit protection function. APPLICATIONS Desktop PC Power Supply Internet Server Power Supply IPC Power Supply UPS Battery Charger DC Motor Power Supply Monitor Power Supply PIN CONFIGURATION SOP-16 (S16) / PDIP-16 (P16) Top View 1 IEAO 2 I AC 3 I SENSE 4 V RMS Telecom System Power Supply 5 Distributed Power 2006/10/11 Rev. 1.3 VEAO 16 V FB 15 V REF 14 V CC 13 SS PFC OUT 12 6 V DC PW M OUT 11 7 RAM P1 GND 10 8 RAM P2 DC I LIMIT Champion Microelectronic Corporation 9 Page 1 CM6800A LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO PIN DESCRIPTION Pin No. Symbol Description Min. Operating Voltage Typ. Max. Unit 1 IEAO PFC transconductance current error amplifier output 0 4.25 V 2 IAC PFC gain control reference input 0 1 mA 3 ISENSE Current sense input to the PFC current limit comparator -5 0.7 V 4 VRMS Input for PFC RMS line voltage compensation 0 6 V 5 SS Connection point for the PWM soft start capacitor 0 8 V 6 VDC PWM voltage feedback input 0 8 V 7 RAMP 1 Oscillator timing node; timing set by RT CT 1.2 3.9 V 0 6 V 0 1 V (RTCT) 8 When in current mode, this pin functions as the current sense input; when in voltage mode, it is the PWM input from PFC (PWM RAMP) output (feed forward ramp). RAMP 2 9 DC ILIMIT PWM current limit comparator input 10 GND Ground 11 PWM OUT PWM driver output 0 VCC V 12 PFC OUT PFC driver output 0 VCC V 13 VCC Positive supply 10 18 V 14 VREF Buffered output for the internal 7.5V reference 15 VFB PFC transconductance voltage error amplifier input 16 VEAO 2006/10/11 Rev. 1.3 PFC transconductance voltage error amplifier output Champion Microelectronic Corporation 15 7.5 0 0 2.5 V 3 V 6 V Page 2 CM6800A LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO BLOCK DIAGRAM (CM6800A) 1 16 13 IEAO VEAO VCC - 0.3V gmv VFB + 15 17.9V LOW POWER DETECT COMPARATOR . 2.5V 2 VREF 7.5V 14 REFERENCE . POWER FACTOR CORRECTOR - gmi . IAC S Q R Q S Q R Q VCC MPPFC + - - -1V GAIN + - MODULATOR 4 7 PFC OVP + - + + VRMS 3 VCC OVP + 2.75V 3.5K VCC VCC PFC OUT 12 PFC ILIMIT 3.5K ISENSE MNPFC RAMP1 OSCILLATOR GND CLK PFCOUT 350 8 SW SPST PWMOUT PWM DUTY DUTY CYCLE RAMP2 LIMIT MPPWM - 1V + VDC Vcc 20uA 350 Q R Q VFB - + . 2.25V SW SPST SW SPST + 1V MNPWM + SS SW SPST VIN OK DC ILIMIT VREF Q 9 S DC ILIMIT R 10 PWM OUT 11 - 5 S - 6 VCC VCC UVLO GND PULSE WIDTH MODULATOR CM6800A(ON:13V/OFF:10V) GND ORDERING INFORMATION Part Number CM6800AGIP* CM6800AGIS* *Note: G : Suffix for Pb Free Product 2006/10/11 Rev. 1.3 Temperature Range -40℃ to 125℃ 16-Pin PDIP (P16) -40℃ to 125℃ 16-Pin Wide SOP (S16) Champion Microelectronic Corporation Package Page 3 CM6800A LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO ABSOLUTE MAXIMUM RATINGS Absolute Maximum ratings are those values beyond which the device could be permanently damaged. Parameter Min. VCC IEAO ISENSE Voltage PFC OUT PWMOUT Voltage on Any Other Pin IREF IAC Input Current Peak PFC OUT Current, Source or Sink Peak PWM OUT Current, Source or Sink PFC OUT, PWM OUT Energy Per Cycle Junction Temperature Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Thermal Resistance (θJA) Plastic DIP Plastic SOIC 0 -5 GND – 0.3 GND – 0.3 GND – 0.3 -65 -40 Max. Units 20 7.5 0.7 VCC + 0.3 VCC + 0.3 VCC + 0.3 10 1 1 1 1.5 150 150 125 260 V V V V V V mA mA A A μJ 80 105 ℃/W ℃/W ℃ ℃ ℃ ℃ ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply Vcc=+15V, RT = 30.16kΩ, CT = 1000pF, TA=Operating Temperature Range (Note 1) Symbol Parameter Test Conditions CM6800A Min. Typ. Unit Max. Voltage Error Amplifier (gmv) Input Voltage Range Transconductance 0 VNONINV = VINV, VEAO = 3.75V at room temp Feedback Reference Voltage Input Bias Current Note 2 Output High Voltage 6 V 70 90 μ mho 2.45 2.5 2.55 -1.0 -0.05 μA 5.8 6.0 V 50 Output Low Voltage Sink Current Source Current Open Loop Gain Power Supply Rejection Ratio 11V < VCC < 16.5V 0.4 -20 V 30 40 μA μA 50 60 dB 50 60 dB VFB = 3V, VEAO = 6V VFB = 1.5V, VEAO = 1.5V 0.1 -35 V Current Error Amplifier (gmi) Input Voltage Range Transconductance -1.5 VNONINV = VINV, VEAO = 3.75V at room temp 50 Input Offset Voltage -25 Output High Voltage 4.0 Output Low Voltage 2006/10/11 Rev. 1.3 85 V 100 μ mho 25 mV 4.25 1.0 Champion Microelectronic Corporation 0.7 V 1.2 Page 4 V CM6800A LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO ELECTRICAL CHARACTERISTICS (Conti.) Unless otherwise stated, these specifications apply Vcc=+15V, RT =30.16kΩ, CT = 1000pF, TA=Operating Temperature Range (Note 1) Symbol Parameter Test Conditions CM6800A Min. Typ. Max. -65 -35 Unit 35 75 μA μA 60 70 dB 60 75 dB Threshold Voltage 2.70 2.77 Hysteresis 230 Sink Current ISENSE = +0.6V, IEAO = 4.0V Source Current ISENSE = -0.6V, IEAO = 1.5V Open Loop Gain Power Supply Rejection Ratio 11V < VCC < 16.5V PFC OVP Comparator 2.85 V 300 mV 0.4 V Low Power Detect Comparator Threshold Voltage 0.2 0.3 Threshold Voltage 17.5 17.9 18.5 V Hysteresis 1.40 1.5 1.65 V 2.65 2.75 2.85 V 2 4 ms 0.4 0.5 0.6 V -1.10 -1.00 -0.90 V 20 100 mV 250 ns VCC OVP Comparator Tri-Fault Detect Fault Detect HIGH Time to Fault Detect HIGH VFB=VFAULT DETECT LOW to VFB=OPEN.470pF from VFB to GND Fault Detect LOW PFC ILIMIT Comparator Threshold Voltage (PFC ILIMIT VTH – Gain Modulator Output) Delay to Output (Note 4) Overdrive Voltage = -100mV DC ILIMIT Comparator Threshold Voltage Delay to Output (Note 4) 0.95 Overdrive Voltage = 100mV 1.0 1.05 250 V ns VIN OK Comparator OK Threshold Voltage 2.16 2.25 2.36 V Hysteresis 0.9 1.1 1.3 V 0.70 0.84 0.95 1.80 2.00 2.20 0.90 1.00 1.10 0.25 0.32 0.40 Gain (Note 3) Bandwidth Output Voltage = 3.5K*(ISENSE-IOFFSET) 2006/10/11 Rev. 1.3 GAIN Modulator IAC = 100 μ A, VRMS =0, VFB = 1V at room temp IAC = 100 μ A, VRMS = 1.1V, VFB = 1V at room temp IAC = 150 μ A, VRMS = 1.8V, VFB = 1V at room temp IAC = 300 μ A, VRMS = 3.3V, VFB = 1V at room temp IAC = 100 μ A IAC = 250 μ A, VRMS = 1.1V, VFB = 1V Champion Microelectronic Corporation 10 0.84 0.90 MHz 0.95 Page 5 V CM6800A LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO ELECTRICAL CHARACTERISTICS (Conti.) Unless otherwise stated, these specifications apply Vcc=+15V, RT = 30.16kΩ, CT = 1000pF, TA=Operating Temperature Range (Note 1) Symbol Parameter Test Conditions Initial Accuracy Oscillator TA = 25℃ Voltage Stability 11V < VCC < 16.5V CM6800A Min. 60 Temperature Stability Total Variation Line, Temp Typ. 70 CT Discharge Current % % 74 V 640 ns VRAMP2 = 0V, VRAMP1 = 2.5V 6.5 15 mA Reference TA = 25℃, I(VREF) = 1mA 7.4 7.6 V 11V < VCC < 16.5V 0mA < I(VREF) < 7mA; TA = 0℃~70℃ Load Regulation kHz 360 Output Voltage Line Regulation kHz 1 2.5 PFC Dead Time (Note 4) Unit 2 52 Ramp Valley to Peak Voltage Max. 0mA < I(VREF) < 5mA; TA = -40℃~85℃ Temperature Stability 7.5 10 25 mV 10 20 mV 10 20 mV 0.4 Total Variation Line, Load, Temp TJ = 125℃, 1000HRs Long Term Stability % 7.35 7.65 V 5 25 mV 0 % 15 ohm PFC Minimum Duty Cycle VIEAO > 4.0V Maximum Duty Cycle VIEAO < 1.2V 90 95 IOUT = -20mA at room temp Output Low Rdson IOUT = -100mA at room temp Output High Rdson % 15 ohm IOUT = 10mA, VCC = 9V at room temp 0.4 0.8 V IOUT = 20mA at room temp 15 20 ohm IOUT = 100mA at room temp 15 20 ohm CL = 1000pF 50 Rise/Fall Time (Note 4) ns PWM Duty Cycle Range 0-45 0-47 IOUT = -20mA at room temp Output Low Rdson IOUT = -100mA at room temp Output High Rdson 0-49 % 15 ohm 15 ohm IOUT = 10mA, VCC = 9V 0.4 0.8 V IOUT = 20mA at room temp 15 20 ohm IOUT = 100mA at room temp 15 20 ohm CL = 1000pF 50 Rise/Fall Time (Note 4) PWM Comparator Level Shift 0.7 ns 1.0 1.1 V 100 150 μA Supply Start-Up Current VCC = 12V, CL = 0 at room temp Operating Current 3.0 7.0 mA Undervoltage Lockout Threshold 14V, CL = 0 CM6800A 12.74 13 13.26 V Undervoltage Lockout Hysteresis CM6800A 2.85 3.0 3.15 V Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 2: Includes all bias currents to other circuits connected to the VFB pin. -1 Note 3: Gain = K x 5.375V; K = (ISENSE – IOFFSET) x [IAC (VEAO – 0.625)] ; VEAOMAX = 6V Note 4: Guaranteed by design, not 100% production test. 2006/10/11 Rev. 1.3 Champion Microelectronic Corporation Page 6 CM6800A LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO TYPICAL PERFORMANCE CHARACTERISTIC 100 127 Transconductance (um ho) Transconductance (umho) 120 113 106 99 92 85 78 71 90 80 70 60 50 40 30 20 10 64 0 57 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 -500 3 0 VFB (V) 500 ISENSE(m V) Voltage Error Amplifier (gmv) Transconductance Current Error Amplifier (gmi) Transconductance 0.4 2 0.35 1.8 0.3 1.6 0.25 1.4 0.2 1.2 Gain Variable Gain Block Constant (K) 2.2 0.15 1 0.8 0.1 0.6 0.05 0.4 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRMS (V) 0.2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRMS (V) Gain Modulator Transfer Characteristic (K) K= -1 IGAINMOD − IOFFSET mV IAC x (6 - 0.625) 2006/10/11 Rev. 1.3 Gain Gain = Champion Microelectronic Corporation ISENSE − IOFFSET IAC Page 7 CM6800A LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO Functional Description The CM6800A consists of an average current controlled, continuous boost Power Factor Correction (PFC) front end and a synchronized Pulse Width Modulator (PWM) back end. The PWM can be used in either current or voltage mode. In voltage mode, feedforward from the PFC output buss can be used to improve the PWM’s line regulation. In either mode, the PWM stage uses conventional trailing edge duty cycle modulation, while the PFC uses leading edge modulation. This patented leading/trailing edge modulation technique results in a higher usable PFC error amplifier bandwidth, and can significantly reduce the size of the PFC DC buss capacitor. The synchronized of the PWM with the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the CM6800A runs at the same frequency as the PFC. In addition to power factor correction, a number of protection features have been built into the CM6800A. These include soft-start, PFC overvoltage protection, peak current limiting, brownout protection, duty cycle limiting, and under-voltage lockout. Since the boost converter topology in the CM6800A PFC is of the current-averaging type, no slope compensation is required. PFC Section Power Factor Correction Power factor correction makes a nonlinear load look like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with and proportional to the line voltage, so the power factor is unity (one). A common class of nonlinear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. The peak-charging effect, which occurs on the input filter capacitor in these supplies, causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. Such supplies present a power factor to the line of less than one (i.e. they cause significant current harmonics of the power line frequency to appear at their input). If the input current drawn by such a supply (or any other nonlinear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the AC line and a unity power factor will be achieved. To hold the input current draw of a device drawing power from the AC line in phase with and proportional to the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. The PFC section of the CM6800A uses a boost-mode DC-DC converter to accomplish this. The input to the converter is the full wave rectified AC line voltage. No bulk filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges (at twice line frequency) from zero volts to the peak value of the AC input and back to zero. By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current drawn from the power line is proportional to the input 2006/10/11 Rev. 1.3 line voltage. One of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VACrms. The other condition is that the current drawn from the line at any given instant must be proportional to the line voltage. Establishing a suitable voltage control loop for the converter, which in turn drives a current error amplifier and switching output driver satisfies the first of these requirements. The second requirement is met by using the rectified AC line voltage to modulate the output of the voltage control loop. Such modulation causes the current error amplifier to command a power stage current that varies directly with the input voltage. In order to prevent ripple, which will necessarily appear at the output of boost circuit (typically about 10VP-P ripple at low frequency on a 385V DC level), from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain of the PFC such to be proportional to 1/VIN^2, which linearizes the transfer function of the system as the AC input to voltage varies. Gain Modulator Figure 1 shows a block diagram of the PFC section of the CM6800A. The gain modulator is the heart of the PFC, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line voltage, and PFC output voltages. There are three inputs to the gain modulator. These are: 1. A current representing the instantaneous input voltage (amplitude and waveshape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is then fed into the gain modulator at IAC. Sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. The gain modulator responds linearly to this current. 2. A voltage proportional to the long-term RMS AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The gain modulator’s output is inversely 2 proportional to VRMS (except at unusually low values of VRMS where special gain contouring takes over, to limit power dissipation of the circuit components under heavy brownout conditions). The relationship between VRMS and gain is called K, and is illustrated in the Typical Performance Characteristics. 3. The output of the voltage error amplifier, VEAO. The gain modulator responds linearly to variations in this voltage. Champion Microelectronic Corporation Page 8 CM6800A LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual-ground (negative) input of the current error amplifier. In this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the PFC form the power line. The general for of the output of the gain modulator is: IGAINMOD = IAC × VEAO x 1V VRMS2 (1) More exactly, the output current of the gain modulator is given by: IGAINMOD = K x (VEAO – 0.625V) x IAC Where K is in units of V-1 Note that the output current of the gain modulator is limited around 228.47 μ A and the maximum output voltage of the gain modulator is limited to 228.47uA x 3.5K=0.8V. This 0.8V also will determine the maximum input power. However, IGAINMOD cannot be measured directly from ISENSE. ISENSE = IGAINMOD-IOFFSET and IOFFSET can only be measured when VEAO is less than 0.5V and IGAINMOD is 0A. Typical IOFFSET is around 60uA. Selecting RAC for IAC pin IAC pin is the input of the gain modulator. IAC also is a current mirror input and it requires current input. By selecting a proper resistor RAC, it will provide a good sine wave current derived from the line voltage and it also helps program the maximum input power and minimum input line voltage. RAC=Vin peak x 7.9K. For example, if the minimum line voltage is 80VAC, the RAC=80 x 1.414 x 7.9K=894Kohm. Current Error Amplifier, IEAO The current error amplifier’s output controls the PFC duty cycle to keep the average current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the ISENSE pin. The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. 2006/10/11 Rev. 1.3 In higher power applications, two current transformers are sometimes used, one to monitor the IF of the boost diode. As stated above, the inverting input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator will cause the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator’s output decreases, the output duty cycle will decrease, to achieve a less negative voltage on the ISENSE pin. Cycle-By-Cycle Current Limiter and Selecting RS The ISENSE pin, as well as being a part of the current feedback loop, is a direct input to the cycle-by-cycle current limiter for the PFC section. Should the input voltage at this pin ever be more negative than –1V, the output of the PFC will be disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle. RS is the sensing resistor of the PFC boost converter. During the steady state, line input current x RS = IGAINMOD x 3.5K. Since the maximum output voltage of the gain modulator is IGAINMOD max x 3.5K= 0.8V during the steady state, RS x line input current will be limited below 0.8V as well. Therefore, to choose RS, we use the following equation: RS =0.8V x Vinpeak/(2x Line Input power) For example, if the minimum input voltage is 80VAC, and the maximum input rms power is 200Watt, RS = (0.8V x 80V x 1.414)/(2 x 200) = 0.226 ohm. PFC OVP In the CM6800A, PFC OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load should suddenly change. A resistor divider from the high voltage DC output of the PFC is fed to VFB. When the voltage on VFB exceeds 2.75V, the PFC output driver is shut down. The PWM section will continue to operate. The OVP comparator has 250mV of hysteresis, and the PFC will not restart until the voltage at VFB drops below 2.50V. The VFB power components and the CM6800A are within their safe operating voltages, but not so low as to interfere with the boost voltage regulation loop. Also, VCC OVP can be served as a redundant PFCOVP protection. VCC OVP threshold is 17.9V with 1.5V hysteresis. Champion Microelectronic Corporation Page 9 CM6800A LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO 1 16 VEAO 13 IEAO VCC PFC OVP VRMS GMi PFC CMP + + . - 14 REFERENCE - POWER FACTOR CORRECTOR TRI-FAULT 0.5V 3.5K IAC 4 7 LOW POWER DETECT VREF 7.5V . 2.75V + 2.5V 3 - . 2 17.9V + VCC OVP - GMv VFB + + 18 - 0.3V VCC S Q R Q + MPPFC - -1V GAIN + - MODULATOR VCC PFC OUT S Q R Q 12 PFC ILIMIT ISENSE RAMP1 3.5K MNPFC GND OSCILLATOR CLK Figure 1. PFC Section Block Diagram Error Amplifier Compensation The PWM loading of the PFC can be modeled as a negative resistor; an increase in input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. Figure 2 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current loop compensation is returned to VREF to produce a soft-start characteristic on the PFC: as the reference voltage comes up from zero volts, it creates a differentiated voltage on IEAO which prevents the PFC from immediately demanding a full duty cycle on its boost converter. PFC Voltage Loop There are two major concerns when compensating the voltage loop error amplifier, VEAO; stability and transient response. Optimizing interaction between transient response and stability requires that the error amplifier’s open-loop crossover frequency should be 1/2 that of the line frequency, or 23Hz for a 47Hz line (lowest anticipated international power frequency). The gain vs. input voltage of the CM6800A’s voltage error amplifier, VEAO has a specially shaped non-linearity such that under steady-state operating conditions the transconductance of the error amplifier is at a local minimum. Rapid perturbation in line or load conditions will cause the input to the voltage error amplifier (VFB) to deviate from its 2.5V (nominal) value. If this happens, the transconductance of the voltage error amplifier will increase significantly, as shown in the Typical Performance Characteristics. This raises the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with a conventional linear gain characteristics. 2006/10/11 Rev. 1.3 The Voltage Loop Gain (S) ΔVOUT ΔVFB ΔVEAO * * ΔVEAO ΔVOUT ΔVFB PIN * 2.5V ≈ * GMV * ZCV 2 VOUTDC * ΔVEAO * S * CDC = ZCV: Compensation Net Work for the Voltage Loop GMv: Transconductance of VEAO PIN: Average PFC Input Power VOUTDC: PFC Boost Output Voltage; typical designed value is 380V. CDC: PFC Boost Output Capacitor PFC Current Loop The current amplifier, IEAO compensation is similar to that of the voltage error amplifier, VEAO with exception of the choice of crossover frequency. The crossover frequency of the current amplifier should be at least 10 times that of the voltage amplifier, to prevent interaction with the voltage loop. It should also be limited to less than 1/6th that of the switching frequency, e.g. 16.7kHz for a 100kHz switching frequency. The Current Loop Gain (S) ΔVISENSE ΔDOFF ΔIEAO * * ΔDOFF ΔIEAO ΔISENSE VOUTDC * RS ≈ * GMI * ZCI S * L * 2 .5 V = Champion Microelectronic Corporation Page 10 CM6800A LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO ZCI: Compensation Net Work for the Current Loop GMI: Transconductance of IEAO VOUTDC: PFC Boost Output Voltage; typical designed value is 380V and we use the worst condition to calculate the ZCI RS: The Sensing Resistor of the Boost Converter 2.5V: The Amplitude of the PFC Leading Modulation Ramp L: The Boost Inductor There is a modest degree of gain contouring applied to the transfer characteristic of the current error amplifier, to increase its speed of response to current-loop perturbations. However, the boost inductor will usually be the dominant factor in overall current loop response. Therefore, this contouring is significantly less marked than that of the voltage error amplifier. This is illustrated in the Typical Performance Characteristics. Figure 2. Compensation Network Connections for the Voltage and Current Error Amplifiers 2006/10/11 Rev. 1.3 ISENSE Filter, the RC filter between RS and ISENSE : There are 2 purposes to add a filter at ISENSE pin: 1.) Protection: During start up or inrush current conditions, it will have a large voltage cross Rs which is the sensing resistor of the PFC boost converter. It requires the ISENSE Filter to attenuate the energy. 2.) To reduce L, the Boost Inductor: The ISENSE Filter also can reduce the Boost Inductor value since the ISENSE Filter behaves like an integrator before going ISENSE which is the input of the current error amplifier, IEAO. The ISENSE Filter is a RC filter. The resistor value of the ISENSE Filter is between 100 ohm and 50 ohm because IOFFSET x the resistor can generate an offset voltage of IEAO. By selecting RFILTER equal to 50 ohm will keep the offset of the IEAO less than 5mV. Usually, we design the pole of ISENSE Filter at fpfc/6, one sixth of the PFC switching frequency. Therefore, the boost inductor can be reduced 6 times without disturbing the stability. Therefore, the capacitor of the ISENSE Filter, CFILTER, will be around 283nF. Figure 3. External Component Connections to VCC Champion Microelectronic Corporation Page 11 CM6800A LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO Oscillator (RAMP1) The oscillator frequency is determined by the values of RT and CT, which determine the ramp and off-time of the oscillator output clock: fOSC = 1 tRAMP + tDEADTIME The dead time of the oscillator is derived from the following equation: tRAMP = CT x RT x In VREF − 1.25 VREF − 3.75 at VREF = 7.5V: tRAMP = CT x RT x 0.51 The dead time of the oscillator may be determined using: tDEADTIME = 2.5V x CT = 943 x CT 2.65mA The dead time is so small (tRAMP >> tDEADTIME ) that the operating frequency can typically be approximately by: fOSC = 1 tRAMP EXAMPLE: For the application circuit shown in the datasheet, with the oscillator running at: fOSC = 67.5kHz = 1 tRAMP -5 Solving for CT x RT yields 2.9 x 10 . Selecting standard components values, CT = 470pF, and RT =61.9kΩ The dead time of the oscillator adds to the Maximum PWM Duty Cycle (it is an input to the Duty Cycle Limiter). With zero oscillator dead time, the Maximum PWM Duty Cycle is typically 45%. In many applications, care should be taken that CT not be made so large as to extend the Maximum Duty Cycle beyond 50%. This can be accomplished by using a stable 390pF capacitor for CT. PWM Section Pulse Width Modulator The PWM section of the CM6800A is straightforward, but there are several points which should be noted. Foremost among these is its inherent synchronization to the PFC section of the device, from which it also derives its basic timing. The PWM is capable of current-mode or voltage-mode operation. In current-mode applications, the PWM ramp (RAMP2) is usually derived directly from a current sensing resistor or current transformer in the primary of the output stage, and is thereby representative 2006/10/11 Rev. 1.3 of the current flowing in the converter’s output stage. DCILIMIT, which provides cycle-by-cycle current limiting, is typically connected to RAMP2 in such applications. For voltage-mode, operation or certain specialized applications, RAMP2 can be connected to a separate RC timing network to generate a voltage ramp against which VDC will be compared. Under these conditions, the use of voltage feedforward from the PFC buss can assist in line regulation accuracy and response. As in current mode operation, the DC ILIMIT input is used for output stage overcurrent protection. No voltage error amplifier is included in the PWM stage of the CM6800A, as this function is generally performed on the output side of the PWM’s isolation boundary. To facilitate the design of optocoupler feedback circuitry, an offset has been built into the PWM’s RAMP2 input which allows VDC to command a zero percent duty cycle for input voltages below 0.7V. PWM Current Limit The DC ILIMIT pin is a direct input to the cycle-by-cycle current limiter for the PWM section. Should the input voltage at this pin ever exceed 1V, the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle. Beside, the cycle-by-cycle current, when the DC ILIMIT triggered the cycle-by-cycle current, it also softly discharge the voltage of soft start capacitor. It will limit PWM duty cycle mode. Therefore, the power dissipation will be reduced during the dead short condition. VIN OK Comparator The VIN OK comparator monitors the DC output of the PFC and inhibits the PWM if this voltage on VFB is less than its nominal 2.25V. Once this voltage reaches 2.45V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft-start begins. PWM Control (RAMP2) When the PWM section is used in current mode, RAMP2 is generally used as the sampling point for a voltage representing the current on the primary of the PWM’s output transformer, derived either by a current sensing resistor or a current transformer. In voltage mode, it is the input for a ramp voltage generated by a second set of timing components (RRAMP2, CRAMP2),that will have a minimum value of zero volts and should have a peak value of approximately 5V. In voltage mode operation, feedforward from the PFC output buss is an excellent way to derive the timing ramp for the PWM stage. Soft Start Start-up of the PWM is controlled by the selection of the external capacitor at SS. A current source of 20 μ A supplies the charging current for the capacitor, and start-up of the PWM begins at around 0.7V. Start-up delay can be programmed by the following equation: CSS = tDELAY x 20 μA 0.7V Champion Microelectronic Corporation Page 12 CM6800A LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO where CSS is the required soft start capacitance, and the tDEALY is the desired start-up delay. It is important that the time constant of the PWM soft-start allow the PFC time to generate sufficient output power for the PWM section. The PWM start-up delay should be at least 5ms. If anything goes wrong, and VCC goes beyond 17.9V, the PFC gate (pin 12) drive goes low and the PWM gate drive (pin 11) remains function. The resistor’s value must be chosen to meet the operating current requirement of the CM6800A itself (5mA, max.) plus the current required by the two gate driver outputs. Solving for the minimum value of CSS: CSS = 5ms x 20 μA = 142nF 0.7V Caution should be exercised when using this minimum soft start capacitance value because premature charging of the SS capacitor and activation of the PWM section can result if VFB is in the hysteresis band of the VIN OK comparator at start-up. The magnitude of VFB at start-up is related both to line voltage and nominal PFC output voltage. Typically, a 1.0 μ F soft start capacitor will allow time for VFB and PFC out to reach their nominal values prior to activation of the PWM section at line voltages between 90Vrms and 265Vrms. In today’s PC power supply, since it has the house-keeping IC in the secondary, the time sequence maybe different from the last paragraph. The 5mS delay and the 1uF Soft Start Capacitor may vary and they may vary base on the application conditions. Generating VCC After turning on CM6800A at 13V, the operating voltage can vary from 10V to 17.9V. The threshold voltage of VCC OVP comparator is 17.9V. The hysteresis of VCC OVP is 1.5V. When VCC see 17.9V, PFCOUT will be low, and PWM section will not be disturbed. That’s the two ways to generate VCC. One way is to use auxiliary power supply around 15V, and the other way is to use bootstrap winding to self-bias CM6800A system. The bootstrap winding can be either taped from PFC boost choke or from the transformer of the DC to DC stage. 2006/10/11 Rev. 1.3 The ratio of winding transformer for the bootstrap should be set between 18V and 15V. A filter network is recommended between VCC (pin 13) and bootstrap winding. The resistor of the filter can be set as following. RFILTER x IVCC ~ 2V, IVCC = IOP + (QPFCFET + QPWMFET ) x fsw IOP = 3mA (typ.) EXAMPLE: With a wanting voltage called, VBIAS ,of 18V, a VCC of 15V and the CM6800A driving a total gate charge of 90nC at 100kHz (e.g. 1 IRF840 MOSFET and 2 IRF820 MOSFET), the gate driver current required is: IGATEDRIVE = 100kHz x 90nC = 9mA RBIAS = VBIAS − VCC ICC + IG RBIAS = 18V − 15V 5mA + 9mA Choose RBIAS = 214Ω The CM6800A should be locally bypassed with a 1.0 μ F ceramic capacitor. In most applications, an electrolytic capacitor of between 47 μ F and 220 μ F is also required across the part, both for filtering and as part of the start-up bootstrap circuitry. Champion Microelectronic Corporation Page 13 CM6800A LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO Leading/Trailing Modulation Conventional Pulse Width Modulation (PWM) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. The error amplifier output is then compared with the modulating ramp up. The effective duty cycle of the trailing edge modulation is determined during the ON time of the switch. Figure 4 shows a typical trailing edge control scheme. One of the advantages of this control technique is that it required only one system clock. Switch 1(SW1) turns off and switch 2 (SW2) turns on at the same instant to minimize the momentary “no-load” period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC’s output ripple voltage can be reduced by as much as 30% using this method. In case of leading edge modulation, the switch is turned OFF right at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned ON. The effective duty-cycle of the leading edge modulation is determined during OFF time of the switch. Figure 5 shows a leading edge control scheme. 2006/10/11 Rev. 1.3 Champion Microelectronic Corporation Page 14 CM6800A LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO APPLICATION CIRCUIT (Voltage Mode) R5 IVIN_EMC EMC FILTER L2 R3 L3 RT1 IVIN D4 PFC_VIN IVIN L1 IL1 PFC_VIN IAC D5 Q3 VIN AC R2 C3 C8 C2 R1 R10 R12 R14 C33 100n D12 Q1 Q2N2222 PFC_DC R13 Q2 Q2N904 R15 R23 R18 D7 1N4002 1N4002 Q4 R22 R25 10k D10 R26 18k PFC_Vout R16A MUR1100 C10 C23 470p R24 75 D6 PFC_Vout IC10 22 1N4148 R11 D5 IBOOT R17A 22 VFB C55A C41 R65A C30 R58 R64 R59 C43 IEAO U2 CM6800/01/24 1 16 IEAO VEAO 2 ISENSE R60 3 VRMS SS VDC C47 VREF VRMS 5 SS 6 C44 R56 R57 C45 C48 C49 8 VCC 13 GND RAMP2 ILIMIT VREF VCC 12 PFC-OUT RAMP1 VREF 14 VCC VDC PWM-OUT 7 VEAO 15 VFB I-SENSE VREF 4 C46 R66 IAC C52 C53 1u 100n VCC C54 11 10 PWM_OUT R63 ZD2 9 C57 C56 R62 ILIMIT ILIMIT C50 R61 470 C51 R44 C4 ISO1 VDC C14 PWM_IN PFC_Vout C7 10n R27 100k 10n C22 10n R34 C38 4.7 R49 IL4 D9A D8 D13 T1 D9B L4 L5 R35 4.7 IC17 IC18 C17 C18 C40 R43 C39 ILOAD C19 MUR1100 MUR1100 R46 PWM_Vout C22 10n R45 PWM_Rload 500m U1 CM431 R48 C15 10n VCC IBIAS C34 100n D16 PWM_OUT R32A R32 VCC 1N4148 Q6 Q2N2222 PWM_DC R28 Q7 Q2N904 22 C31 R33 T 2:3 Q3 R29 10k ILIMIT R31 ZD1 6.8V 2006/10/11 Rev. 1.3 Champion Microelectronic Corporation Page 15 CM6800A LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO APPLICATION CIRCUIT (Current Mode) R5 IVIN_EMC EMC FILTER L2 R3 L3 RT1 IVIN D4 PFC_VIN IVIN L1 IL1 PFC_VIN IAC D5 Q3 VIN AC R2 C3 C8 C2 R1 R10 R12 R14 C33 100n D12 Q1 Q2N2222 PFC_DC R13 Q2 Q2N904 R15 R23 R18 D7 1N4002 1N4002 PFC_Vout IC10 D10 R22 R26 18k R25 10k R16A MUR1100 C10 C23 470p R24 75 D6 PFC_Vout Q4 22 1N4148 R11 D5 IBOOT R17A 22 VFB C55A C41 C30 R58 R64 R59 R65A C43 IEAO U2 CM6800/01/24 1 16 IEAO VEAO 2 ISENSE R60 3 VRMS SS VDC C47 VREF R57 5 SS 6 R67 C48 C49 PFC-OUT VDC PWM-OUT 8 ILIMIT C45 VCC VRMS 7 R56 C44 VFB I-SENSE VREF 4 C46 R66 IAC RAMP1 GND RAMP2 ILIMIT VEAO 15 VREF 14 13 VREF VCC 12 C52 C53 1u 100n VCC C54 11 10 PWM_OUT R63 ZD2 9 C57 C56 R62 C50 R61 470 ILIMIT ILIMIT C51 R68 R44 C4 ISO1 VDC C14 PWM_IN PFC_Vout R34 C38 C7 10n R27 100k C22 10n 10n 4.7 R49 IL4 D9A D8 D13 MUR1100 T1 D9B L4 L5 R46 PWM_Vout IC17 IC18 C17 C18 ILOAD R35 4.7 C40 R43 C39 C19 R45 PWM_Rload 500m U1 CM431 MUR1100 C22 10n R48 C15 10n VCC IBIAS C34 100n D16 R32 VCC 1N4148 PWM_OUT R32A Q6 Q2N2222 PWM_DC R28 Q7 Q2N904 22 C31 R33 T 2:3 Q3 R29 10k ILIMIT R31 ZD1 6.8V 2006/10/11 Rev. 1.3 Champion Microelectronic Corporation Page 16 CM6800A LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO PACKAGE DIMENSION 16-PIN PDIP (P16) PIN 1 ID θ θ 16-PIN SOP (S16), 0.300” Wide Body PIN 1 ID θ 2006/10/11 Rev. 1.3 Champion Microelectronic Corporation Page 17 CM6800A LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO IMPORTANT NOTICE Champion Microelectronic Corporation (CMC) reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. A few applications using integrated circuit products may involve potential risks of death, personal injury, or severe property or environmental damage. CMC integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Use of CMC products in such applications is understood to be fully at the risk of the customer. In order to minimize risks associated with the customer’s applications, the customer should provide adequate design and operating safeguards. HsinChu Headquarter Sales & Marketing 5F, No. 11, Park Avenue II, Science-Based Industrial Park, HsinChu City, Taiwan 7F-6, No.32, Sec. 1, Chenggong Rd., Nangang District, Taipei City 115, Taiwan, R.O.C. T E L : +886-3-567 9979 F A X : +886-3-567 9909 http://www.champion-micro.com T E L : +886-2-2788 0558 F A X : +886-2-2788 2985 2006/10/11 Rev. 1.3 Champion Microelectronic Corporation Page 18