CIRRUS CDB5460A

\
CDB5460A
CDB5460A Evaluation Board and Software
Features
General Description
z Direct
The CDB5460A is an inexpensive tool designed to evaluate the functionality and performance of the CS5460A.
The CS5460A Data Sheet is supplied in conjunction with
the CDB5460A evaluation board.
Shunt Sensor and Current
Transformer Interface
z RS-232 Serial Communication with PC
z On-board 80C51 Microcontroller
z On-board Voltage Reference
z Lab Windows/CVITM Evaluation Software
-
Register Setup & Chip Control
FFT Analysis
Time Domain Analysis
Noise Histogram Analysis
z On-board
Data SRAM
z Integrated RS-232 Test Mode
z “Auto-Boot” Demo with serial EEPROM
The evaluation board includes an LT1019 voltage reference, an 80C51 microcontroller, an RS232 transceiver,
and firmware. The 8051 controls the serial communication between the evaluation board and the PC via the
firmware, enabling quick and easy access to all of the
CS5460A’s registers and functions.
The CDB5460A includes software for Data Capture,
Time Domain Analysis, Histogram Analysis, and Frequency Domain Analysis.
ORDERING INFORMATION
CDB5460A
VA+
VA-
AGND
C RY S TA L
4.096 M H z
VD+
S E RIAL
E E PR O M
Evaluation Board
V u+
C RY S TA L
20.0 M H z
TEST
S W IT C H E S
R E SE T
C IR CU IT R Y
V IN +
V IN -
IIN +
IIN -
CS
SDI
C S 5460
SDO
S C LK
IN T
E D IR
EOUT
80C 51
M icrocontroller
R S 232
T R AN S C E IV ER
R S 232
C O N NE C T O R
V R EF
IN O U T
LE D s
REF
AGND
V O LT A G E
R E FE RE N C E
Cirrus Logic, Inc.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
32k × 8
S R AM
Copyright  Cirrus Logic, Inc. 2002
(All Rights Reserved)
AUG ‘02
DS487DB3
1
CDB5460A
TABLE OF CONTENTS
1. HARDWARE ............................................................................................................................. 5
1.1 Introduction ........................................................................................................................ 5
1.2 Evaluation Board Overview ................................................................................................ 5
1.2.1 Analog Section ...................................................................................................... 5
1.2.2 Digital Section ....................................................................................................... 6
1.2.3 Power Supply Section ........................................................................................... 6
1.3 Using the Evaluation Board ............................................................................................... 6
2. SOFTWARE .............................................................................................................................. 8
2.1 Installation Procedure ........................................................................................................ 9
2.2 Using the Software ............................................................................................................. 9
2.3 Selecting and Testing a COM Port .................................................................................... 9
2.4 Register Access in the Setup Window ............................................................................. 10
2.4.1 Refresh Screen Button ........................................................................................ 10
2.4.2 CS5460A Crystal Frequency ............................................................................... 10
2.4.3 Configuration Register ........................................................................................ 10
2.4.4 Mask Register / Status Register .......................................................................... 11
2.4.5 Cycle Count / Pulse Rate / Time Base Registers ................................................ 11
2.4.6 Control Register .................................................................................................. 12
2.5 Calibration Window .......................................................................................................... 12
2.5.1 Offset / Gain Register .......................................................................................... 12
2.5.2 Performing Calibrations ....................................................................................... 12
2.6 Conversion Window ......................................................................................................... 13
2.6.1 Single Conversion Button .................................................................................... 14
2.6.2 Continuous Conversions Button .......................................................................... 14
2.6.3 Re-Initialize Serial Port Button ............................................................................ 14
2.6.4 Standby / Sleep Mode Buttons ............................................................................ 14
2.6.5 Power Up Button ................................................................................................. 14
2.7 Viewing Pulse Rate Output Data ..................................................................................... 14
2.7.1 Integration Period Box ......................................................................................... 15
Contacting Cirrus Logic Support
For a com plete listing of D irect S ales, D istributor, and S ales R epresentative contacts, visit the Cirrus Logic w eb site at:
http://www.cirrus.com /corporate/contacts/sales.cfm
I IM P O R TA N T N O TIC E
“P relim inary” product inform ation describes products that are in production, but for w hich full characterization data is not yet available. “A dvance” product inform ation describes products that are in developm ent and subject to developm ent changes. C irrus Logic, Inc. and its subsidiaries (“C irrus”) believe that the inform ation contained in this docum ent is accurate and reliable. H owever, the inform ation is subject to change w ithout notice and is provided “AS IS ” without warranty
of any kind (express or im plied). C ustom ers are advised to obtain the latest version of relevant inform ation to verify, before placing orders, that inform ation being
relied on is current and com plete. A ll products are sold subject to the term s and conditions of sale supplied at the tim e of order acknowledgm ent, including those
pertaining to w arranty, patent infringem ent, and lim itation of liability. N o responsibility is assum ed by Cirrus for the use of this inform ation, including use of this
inform ation as the basis for m anufacture or sale of any item s, or for infringem ent of patents or other rights of third parties. This docum ent is the property of C irrus
and by furnishing this inform ation, C irrus grants no license, express or im plied under any patents, m ask w ork rights, copyrights, tradem arks, trade secrets or
other intellectual property rights. C irrus ow ns the copyrights of the inform ation contained herein and gives consent for copies to be m ade of the inform ation only
for use w ithin your organization with respect to C irrus integrated circuits or other parts of C irrus. This consent does not extend to other copying such as copying
for general distribution, advertising or prom otional purposes, or for creating any w ork for resale.
An export perm it needs to be obtained from the com petent authorities of the Japanese G overnm ent if any of the products or technologies described in this m aterial and controlled under the “Foreign Exchange and Foreign Trade Law ” is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the com petent authorities of the C hinese G overnm ent if any of the products or technologies described in this m aterial is subject to the P R C Foreign
Trade Law and is to be exported or taken out of the P R C.
C ER TAIN AP P LIC A TIO N S US IN G SE M ICO N D U C TO R P RO DU C TS M A Y IN V O LV E P O TE N TIA L R ISK S O F D E A TH , PE R S O N AL IN JU R Y, O R SE V ER E
PR O P E R TY O R EN V IR O N M E N TA L D A M A G E (“CR ITIC A L A P PLICA TIO N S”). C IR R U S P R O D U CTS A RE N O T D E S IG N ED , AU TH O RIZE D , O R W A R R AN TED TO B E SU ITAB LE FO R U SE IN LIFE -S U PP O R T D E V IC ES O R S Y STEM S O R O TH E R C R ITIC A L A PP LICA TIO N S. IN CLU SIO N O F C IR R U S PR O D U C TS
IN S UC H A P PLIC ATIO N S IS U N D E R STO O D TO BE FU LLY AT TH E C U STO M E R 'S RISK .
C irrus Logic, C irrus, and the C irrus Logic logo designs are tradem arks of C irrus Logic, Inc. A ll other brand and product nam es in this docum ent m ay be tradem arks or service m arks of their respective ow ners. B M , A T and P S/2 are tradem arks of International B usiness M achines C orporation. W indow s is a tradem ark
of M icrosoft C orporation. Lab W indow s and C VI are tradem arks of N ational Instrum ents.S P ITM is a tradem ark of M otorola. M icrow ire TM is a tradem ark of N ational S em iconductor.
2
CDB5460A
2.7.2 Periods To Average Box ..................................................................................... 15
2.7.3 Start Button ......................................................................................................... 15
2.8 Data Collection Window Overview .................................................................................. 15
2.8.1 Time Domain / FFT / Histogram Selector ........................................................... 15
2.8.2 Collect Button ...................................................................................................... 17
2.8.3 Config Button ...................................................................................................... 17
2.8.4 Output Button ...................................................................................................... 17
2.8.5 Zoom Button ....................................................................................................... 17
2.8.6 Channel Select Buttons ...................................................................................... 17
2.9 Config Window ................................................................................................................ 17
2.9.1 Number of Samples ............................................................................................ 17
2.9.2 Average ............................................................................................................... 17
2.9.3 FFT Window ........................................................................................................ 17
2.9.4 Histogram Bin Width ........................................................................................... 17
2.9.5 Pages to Collect .................................................................................................. 17
2.9.6 Data to Collect .................................................................................................... 17
2.9.7 Accept Button ...................................................................................................... 18
2.10 Collecting Data Sets ...................................................................................................... 18
2.11 Retrieving Saved Data From a File ............................................................................... 18
2.12 Analyzing Data .............................................................................................................. 18
2.13 Histogram Information ................................................................................................... 18
2.13.1 BIN .................................................................................................................... 18
2.13.2 MAGNITUDE .................................................................................................... 18
2.13.3 MAXIMUM ........................................................................................................ 18
2.13.4 MEAN .........................................................................................................................19
2.13.5 MINIMUM .......................................................................................................... 19
2.13.6 STD. DEV. ........................................................................................................ 19
2.13.7 VARIANCE ....................................................................................................... 19
2.14 Frequency Domain Information ..................................................................................... 19
2.14.1 FREQUENCY ................................................................................................... 19
2.14.2 MAGNITUDE .................................................................................................... 19
2.14.3 S/D .................................................................................................................... 19
2.14.4 S/N+D ............................................................................................................... 19
2.14.5 SNR .................................................................................................................. 19
2.14.6 S/PN .................................................................................................................. 19
2.14.7 # of AVG ........................................................................................................... 19
2.15 Time Domain Information .............................................................................................. 19
2.15.1 COUNT ............................................................................................................. 19
2.15.2 MAGNITUDE .................................................................................................... 19
2.15.3 MAXIMUM ........................................................................................................ 20
2.15.4 MINIMUM .......................................................................................................... 20
3. ADDENDUM ........................................................................................................................... 28
3.1 Board Modifications for Charge Pump ............................................................................. 28
3
CDB5460A
LIST OF FIGURES
Figure 1. Start-Up Window ............................................................................................................ 10
Figure 2. Setup Window ................................................................................................................ 11
Figure 3. Calibration Window ........................................................................................................ 12
Figure 4. Conversion Window ....................................................................................................... 13
Figure 5. Pulse Rate Output Window ............................................................................................ 14
Figure 6. Time Domain Analysis ................................................................................................... 15
Figure 7. FFT Analysis .................................................................................................................. 16
Figure 8. Histogram Analysis ........................................................................................................ 16
Figure 9. Analog Schematic ......................................................................................................... 21
Figure 10. Digital Schematic Part 1............................................................................................... 22
Figure 11. Digital Schematic Part 2............................................................................................... 23
Figure 12. Power Supply Schematic ............................................................................................. 24
Figure 13. Silkscreen..................................................................................................................... 25
Figure 14. Circuit Side................................................................................................................... 26
Figure 15. Solder Side................................................................................................................... 27
Figure 16. CDB5460A Modifications for A- Charge Pump ............................................................ 28
LIST OF TABLES
Table 1. Reference Selection ................................................................................................................ 5
Table 2. Power Supply Connections..................................................................................................... 6
Table 3. Header, Jumper, and DIP Switch Descriptions....................................................................... 7
Table 4. DIP Switch S1 Setting.............................................................................................................. 8
4
CDB5460A
1. HARDWARE
1.1 Introduction
The CDB5460A evaluation board provides a quick
means of evaluating the CS5460A Power Meter IC.
The CDB5460A evaluation board’s analog section
operates from either a single +5 V or dual ±2.5 V
power supply. The evaluation board interfaces the
CS5460A to an IBMTM compatible PC via an RS232 interface. To accomplish this, the board comes
equipped with an 80C51 microcontroller and a 9pin RS-232 cable which physically interfaces the
evaluation board to the PC. Additionally, analysis
software provides easy access to the internal registers of the CS5460A, and provides a means to display the performance in the time domain or
frequency domain.
1.2 Evaluation Board Overview
The board is partitioned into two main sections: analog and digital. The analog section consists of the
CS5460A and a precision voltage reference. The
digital section consists of the 80C51 microcontroller, 32 Kilobytes of SRAM, the hardware test
switches, the reset circuitry, and the RS-232 interface. The board also has a user friendly power supply connection.
1.2.1 Analog Section
The CS5460A is designed to accurately measure
and calculate: Energy, Instantaneous Power, IRMS,
and VRMS while operating from a 4.096 MHz crystal. As shown in Figure 9 there are four BNC connectors (J6, J7, J8, J9) provided for converter input
connections. A Shunt Sensor or Current Transformer can be connected to the converter’s current
inputs via J9 (IIN+) and J8 (IIN-). A voltage divider can be connected to the converter’s voltage input
via J6 (VIN+) and J7 (VIN-). Note, a simple RC
network filters the sensor’s output to reduce any in-
terference picked up by the input leads. The 3 dB
corner of the filter is approximately 50 KHz differential and common mode.
The evaluation board provides three voltage reference options, on-chip, on-board and external, as
shown in Figure 9. Table 1 illustrates the options
available. With J18’s jumpers in position REFOUT, the on-chip reference provides 2.5 volts.
With J18’s jumpers in position LT1019, the
LT1019 provides 2.5 volts (the LT1019 was chosen
for its low drift, typically 5 ppm/°C). By setting
J18’s jumpers to position REF+, the user can supply an external voltage reference to J26’s REF+
and VA- inputs. Application Note 4 on the web
(http://www.cirrus.com/products//pubs.html) details various voltage references.
Reference
Description
J18
LT1019
Selects on board
LT1019 Reference
(5ppm/°C)
O
O
O
O LT1019
O REF+
O REFOUT
REF+
Selects external
reference
O
O
O
O LT1019
O REF+
O REFOUT
REFOUT
Selects the reference
supplied by CS5460A
O
O
O
O LT1019
O REF+
O REFOUT
Table 1. Reference Selection
The CS5460A serial interfaces are SPITM and MicrowireTM compatible. The interface control lines
(CS, SDI, SDO, and SCLK) are connected to the
80C51 microcontroller via Port 1. To interface an
external microcontroller, these control lines are
also connected to J19 (Header 19). However to accomplish this, the evaluation board must be modified in one of three ways: 1) cut the interface
control traces going to the microcontroller, 2) remove resistors 24, 23, 22, and 21, or 3) remove the
microcontroller.
5
CDB5460A
1.2.2 Digital Section
The schematics for the digital section are shown in
Figure 10 and Figure 11. The digital section contains the microcontroller, test switches, a Maxim
MAX3232 interface chip, and 32K bytes of
SRAM, and one serial EEPROM. The test switches
aid in debugging communication problems between the CDB5460A and the PC. The microcontroller derives its clock from a 20.0 MHz crystal.
From this, The RS-232 data conversion IC (10) is
configured to communicate via RS-232 at 9600
baud, no parity, 8-bit data, and 1 stop bit.
1.2.3 Power Supply Section
Figure 12 illustrates the power supply connections
to the evaluation board. The VA+ post supplies the
positive analog section of the evaluation board, the
LT1019 and the ADC. The VA- post supplies the
negative analog voltage circuitry. Note, this terminal is grounded when powering the CDB5460A
from a single +5 Volt analog supply. The VD+ post
supplies the digital section of the ADC and level
shifter. The Vu+ post supplies the digital section of
the evaluation board, the 80C51, the reset circuitry,
and the RS-232 interface circuitry. Note, the
board’s digital section supplied via Vu+ post, must
Power Supplies
Analog
Digital
VA+
be +5 Volts only. Table 2 shows the various power
connections with the required jumper settings on
J12 and J11.
1.3 Using the Evaluation Board
The CS5460A is a highly integrated device, containing dual ADCs with a computational unit. The
CS5460A and CDB5460A data sheets should be
read thoroughly and understood before using the
CDB5460A evaluation board. The CS5460A contains a programmable gain amplifier (PGA), two
∆Σ modulators, two high rate filters, an on-chip reference, and power calculation engine to compute
Energy, VRMS, IRMS, and Instantaneous Power.
The PGA sets the input levels of the current channel at either 30 mVRMS or 150 mVRMS (for VREFIN = 2.5 V). The on-chip reference can provide
the necessary 2.5 V reference. This output (VREFOUT) is used to supply the VREFIN pin with
2.5 V. The ∆Σ modulators and high rate digital filter allow the user to measure instantaneous voltage,
current, and power at a output word rate of 4000 Hz
when a 4.096 MHz clock source is used. Table 3
describes the various headers, jumpers and DIP
switches on the CDB5460A evaluation board. DIP
switch S1 is used to control the 80C51. Table 4 illustrates the varies setting of the DIP Switch S1.
Power Post Connections
VAGND
VD+
Jumpers
Vu+
J11
+5V
+5V
+5
NC
GND
+5
NC
Vu+ O
VD+ O
VD+ O
VA+ O
O
O
O
O
VDDD
VDDD
D+
D+
VA- O
A- O
O GND
O GND
+5V
+3V
+5
NC
GND
+3
+5
Vu+ O
VD+ O
VD+ O
VA+ O
O
O
O
O
VDDD
VDDD
D+
D+
VA- O
A- O
O GND
O GND
±2.5V
+3V
+2.5
-2.5
GND
+3
+5
Vu+ O
VD+ O
VD+ O
VA+ O
O
O
O
O
VDDD
VDDD
D+
D+
VA- O
A- O
O GND
O GND
Table 2. Power Supply Connections
6
J12
CDB5460A
Name
Function Description
Default Setting
Default Jumpers
J13
Used to switch VIN+ on the CS5460A between J6
and GND.
VIN+ Set to BNC J6
O
O
O VIN+
O GND
J14
Used to switch VIN- on the CS5460A between J11
and GND.
VIN- Set to BNC J7
O
O
O VINO GND
J11
Used to switch VA-, A-, and GND. Refer toTable 2
on page 6
Negative Analog
Power Supply Set to
0V
VA- O
A- O
O GND
O GND
J18
Used to switch the VREFIN from external J26
header, to the on board LT1019 reference, or to the
on-chip reference VREFOUT. Refer to Table
Table 1, “Reference Selection,” on page 5
VREFIN Set to onchip reference
VREFOUT
J12
Used to switch VU+, VD+, and VA+ to VDDD
and/or D+. Refer to Table 2, “Power Supply Connections,” on page 6
J17
O LT1019
O REF+
O REFOUT
Vu+ O
VD+ O
VD+ O
VA+ O
Used to connect an external micro-controller.
Connected to 80C51
Used in conjunction with the self test modes to test
RS-232 Set to Normal
the UART/RS-232 communication link between the
Mode
microcontroller and a PC.
O
O
O
O
VDDD
VDDD
D+
D+
NC
O
O
O
O
J17
J19
Digital Power Supply
Set to +5V
O
O
O
J15
Used to switch IIN+ on the CS5460A between J10
and GND.
IIN+ Set to BNC J9
O
O
O IIN+
O GND
J16
Used to switch IIN- on the CS5460A between J9
and GND.
IIN- Set to BNC J8
O
O
O IINO GND
J23
Used to switch XIN on the CS5460A to HDR6 when XIN Set for on-board
an external micro-controller is used.
4.096 MHz XTAL
O
O
O GND
O XIN
JP2
Used to connect PFMON pin on the CS5460A to
monitor Power Supply VA+
PFMON Set Monitor
VA+
O
O JP2
JP4
Used to connect the RESET Button to the
CS5460A
RESET Set connected to CS5460A
O
O JP4
S1
J21
J10
DIP switch to control 80C51 (See Table 4)
S1-1 is used to enable auto-boot mode
S1-2 is used to select crystal to 80C51
S1-3 is used to select RS-232 test mode
Allows LEDs D2 and D3 to indicate pulses on
/EOUT and /EDIR. Pulse frequency must be less
than ~6Hz to see light.
S1-1 Auto-Boot off
S1-2 Set 20 MHz
S1-3 Set Normal
1
2
3
OPEN
Disable LEDs
Used to disconnect XTAL1 input on microcontroller
Use on-board crystal
from off-board oscillator input.
O
O J21
O
O J10
Table 3. Header, Jumper, and DIP Switch Descriptions
7
CDB5460A
80C51 Mode
80C51 in Normal Operating Mode
S1-1 OPEN
S1-2 CLOSED 20 MHz Crystal
S1-3 OPEN
80C51 in Normal Operation Mode
S1-1 OPEN
S1-2 OPEN 11.059 MHz Crystal
S1-3 OPEN
80C51 in Test Mode
S1-1 OPEN
S1-2 CLOSED 20 MHz Crystal
S1-3 CLOSED
80C51 in Test Mode
S1-1 OPEN
S1-2 OPEN 11.059 MHz Crystal
S1-3 CLOSED
Auto-Boot Mode
S1-1 CLOSED
S1-2 CLOSED
S1-3 OPEN
S1
1
2
3
40 00 00 61
;In configuration Register, turn highpass filters on, set K = 1.
4C 10 00 00
;Set Pulse Rate Register to 32768 Hz.
E8
;Start continuous conversions.
78 00 01 00
;Write stop bit to CS5460A to terminate
OPEN
1
2
3
OPEN
1
2
3
OPEN
1
2
3
OPEN
1
2
3
OPEN
Table 4. DIP Switch S1 Setting
The S1-3 switch should be set to the OPEN position for normal operation. When testing the RS-232
link in the PC software, close S1-3. The S1-2
switch selects the crystal source for the 80C51.
There are two crystal options available,
11.059 MHz and 20 MHz. If S1-2 is OPEN the
11.059 MHz crystal is selected, and when S1-2 is
CLOSED the 20 MHz crystal is selected.
If S1-1 is closed, the CS5460A operates in autoboot mode. When in auto-boot mode, a hardware
reset (press on S2) will cause the CS5460A to boot
up using the serial data from the serial EEPROM
on the board (U9). The EEPROM must be programmed prior to the auto-boot sequence. The EEPROM does come pre-programmed with a valid
boot-up sequence. This sequence programs the
CS5460A for continuous conversion mode. If voltage and current signals are applied to the inputs, the
CS5460A will issue pulses on the /EOUT and
/EDIR pins. Note that JP4 header must be shorted
for auto-boot to work.
8
When the CDB5460 Evaluation Board is sent from
the factory, the EEPROM is programmed with the
following CS5460A command/data sequence:
autoboot sequence.
The auto-boot sequence runs with no assistance
from the 8051 microcontroller. The user can verify
this by disconnecting power from the board, pulling the microcontroller out of its socket, then power on again and run in auto-boot mode. See the
CS5460A data sheet for more details on auto-boot.
2. SOFTWARE
The evaluation board comes with software and an
RS-232 cable to link the evaluation board to the
PC. The evaluation software was developed with
Lab Windows/CVITM, a software development
package from National Instruments. The software
was designed to run under Windows 95TM or later,
and requires about 3MB of hard drive space (2MB
for the CVI Run-Time EngineTM, and 1MB for the
evaluation software). After installing the software,
read the readme.txt file for any last minute updates
or changes. More sophisticated analysis software
can be developed by purchasing the development
package from National Instruments (512-7940100).
CDB5460A
2.1 Installation Procedure
1) Turn on the PC, running Windows 95TM or later.
2) Insert the Installation Diskette #1 into the PC.
3) Select the Run option from the Start menu.
4) At the prompt, type: A:\SETUP.EXE <enter>.
5) The program will begin installation.
6) If it has not already been installed on the PC,
the user will be prompted to enter the directory
in which to install the CVI Run-Time EngineTM. The Run-Time EngineTM manages executables created with Lab Windows/CVITM. If
the default directory is acceptable, select OK
and the Run-Time EngineTM will be installed
there.
7) After the Run-Time EngineTM is installed, the
user is prompted to enter the directory in which
to install the CDB5460A software. Select OK
to accept the default directory.
8) Once the program is installed, it can be run by
double-clicking on the EVAL5460A icon, or
through the Start menu.
Notes: The software is written to run with 640 x 480
resolution; however, it will work with 1024 x 768
resolution. If the user interface appears to be
small, the user might consider setting the
display settings to 640 x 480. (640x480 was
chosen to accommodate a variety of
computers).
2.2 Using the Software
Before launching the software, the user should set
up the CDB5460A evaluation board by using the
correct jumper and DIP switch settings as described in Part I, and connect it to an open COM
port on the PC using the RS-232 serial cable. Once
the board is powered on, the user can start the software package.
When the software is launched, the Start-Up window appears first (Figure 1). This window contains
information concerning the software’s title, revision number, copyright date, etc. At the top of the
screen is a menu bar which displays user options.
The menu bar item Menu is initially disabled to
prevent conflicts with other serial communications
devices, such as the mouse or a modem. After selecting a COM port, the Menu item will become
available.
2.3 Selecting and Testing a COM Port
Upon start-up, the user is prompted to select the serial communications port which will interface to
the CDB5460A board. To select the COM port,
pull down the Setup menu option, and select either
COM1 or COM2 (the DISK option is used for previously saved files, and is discussed later). Testing
the COM port to verify communication between
the PC and the evaluation board is not necessary,
but can help to troubleshoot some problems. The
procedure for testing the communication link follows.
1) Pull down the Setup menu option again, and select TEST RS-232.
2) When prompted, set DIP switch 1 (the leftmost
DIP switch) to the closed position, reset the
board, and press OK to perform the test.
3) If the test passes, set DIP switch 1 to the open
position, and reset the board to return to normal
operating mode.
4) If the test fails, check the serial port connections, power connections, jumpers, and DIP
switch settings on the board, and run the test
again from step 1.
Once the serial link is established between the PC
and the evaluation board, the user is ready to access
the internal registers of the CS5460A, collect data,
and perform analysis on the collected data.
9
CDB5460A
Figure 1. Start-Up Window
2.4 Register Access in the Setup Window
The Evaluation software provides access to the
CS5460A’s internal registers in the Setup Window
(Figure 2). The user can enter the Setup Window
by pulling down Menu and selecting Setup Window, or by pressing F2 on the keyboard.
ing any registers to reflect the current status of the
part.
2.4.2 CS5460A Crystal Frequency
In the Setup Window, all of the CS5460A’s registers are displayed in hexadecimal notation, and also
decoded to provide easier readability. Refer to the
CS5460A data sheet for information on register
functionality and meanings.
The CS5460A accepts a wide range of crystal input
frequencies, and can therefore run at many different sample rates. The crystal frequency being used
on the CS5460A should be entered in this box to
provide accurate frequency calculations in the FFT
window. This will also help the software decide
which functions can be performed reliably with the
evaluation system.
2.4.1 Refresh Screen Button
2.4.3 Configuration Register
The Refresh Screen button will update the contents
of the screen by reading all the register values from
the part. This usually takes a couple of seconds, but
it is a good idea to press the Refresh Screen button
when entering the Setup Window, or after modify-
In the Configuration Register box, the contents of
the Configuration Register can be modified by typing a hexadecimal value in the HEX: box, or by
changing any of the values below the HEX: box to
the desired settings. Note that when changing the
10
CDB5460A
Figure 2. Setup Window
value of the reset bit to ‘1’ (RS, bit 7 in the Configuration Register), the part will be reset, and all registers will return to their default values. Press the
Refresh Screen button after performing a reset to
update the screen with the new register values.
Note:
Although the CDB5460A software allows the
user to modify any of the bits in the
Configuration Register, changing certain bits
may cause the software and board to behave
erratically. For the evaluation system to
function properly, the Interrupt Output function
should be set to the default Active Low, and the
Eout / Edir Function should be set to the default
Normal. This applies only to the CDB5460A
evaluation system, and not to the CS5460A
chip itself.
2.4.4 Mask Register / Status Register
The Mask and Status Registers are displayed in
hexadecimal and decoded in this box to show what
each of the bits means. The Mask Register can be
modified by typing a value in the HEX: box, or by
checking the appropriate check boxes for the bits
that are to be masked. The Status Register cannot
be directly modified. It can only be reset by pressing the Clear Status Register Button. The HEX:
box for this register, and the LEDs are display only.
A LED that is on means that the corresponding bit
in the Status Register is set (except the Invalid
Command bit, which is inverted).
Note:
The value present in the Mask register may be
changed by the software during certain
operations to provide correct functionality of the
CDB5460A board.
2.4.5 Cycle Count / Pulse Rate / Time Base
Registers
These three boxes display the values of the Cycle
Count, Pulse Rate, and Time Base Registers in both
hexadecimal and decimal format. All three registers can be modified by typing a value in the corresponding Value: or HEX: box.
11
CDB5460A
2.4.6 Control Register
The Control Register contains various bits used to
activate or terminate various features of the
CS5460A. Refer to the CS5460A data sheet for description of the bits. The user is able to turn each bit
on or off individually. The value of the Control
Register is displayed in HEX. Note that the Control Register, like all other CS5460A registers, is
24 bits long. Most of these bits are reserved or unused. Only the usable bits are displayed in the Setup Window.
2.5 Calibration Window
The Calibration Window is used to display and
write to the CS5460A offset and gain calibration
registers. The user is also able to initiate the
CS5460A’s calibration sequences that are used to
set the calibration values. Both AC and DC calibrations can be run for offset and gain, for either the
voltage channel or the current channel, or both simultaneously. The user should refer to the
CS5460A data sheet for more details on calibration.
2.5.1 Offset / Gain Register
In the Offset and Gain Register boxes, the offset
and gain registers for both channels are displayed
in hexadecimal and decimal. These registers can all
be modified directly by typing the desired value in
the hexadecimal display boxes. There are two
types of offset registers: DC offset and AC offset.
The AC offset registers only affect the RMS-register values. Note that the RMS offset registers only
hold positive values between 0 and +1. The DC
offset register is a two’s complement number
whose value ranges from -1 to +1.
2.5.2 Performing Calibrations
Offset and gain calibrations can be performed on
both the voltage and current channels of the
CS5460A. It is generally a good idea to softwarereset the CS5460A before running calibrations, because the values in the calibration registers will affect the results of the calibration. A software reset
Figure 3. Calibration Window
12
CDB5460A
will reset these registers back to the default values
of zero offset and unity gain. Offset calibration
should be performed before gain calibration to ensure accurate results.
2.5.2.1. Offset Calibrations:
1) Ground the channel(s) you want to calibrate directly at the channel header(s). HDR1 and
HDR2 for the voltage channel, and HDR8 and
HDR9 for the current channel. The channel(s)
could also be grounded directly at the BNC
connectors.
2) Press the corresponding AC or DC offset calibrate button (Cal V, Cal I, or Cal Both) in the
Offset Register boxes.
3) The calibration value(s) will automatically update when the calibration is completed.
2.5.2.2. Gain Calibrations:
1) Attach an AC or DC calibration signal to the
BNC connector(s), and make sure the corresponding channel headers (J13, J4, J15, and
J16) are set to the input position.
2) Press the corresponding AC or DC gain calibrate button (Cal V, Cal I, or Cal Both) in the
Gain Register box.
3) The calibration value(s) will automatically update when the calibration is completed.
The Calibration Window also contains the Power
Offset Register display and adjustment. The user
can read and write the value in the Power Offset
Register.
2.6 Conversion Window
The Conversion Window (Figure 4) allows the user
to see the results of single and continuous conversions on all six data registers, perform data averaging, utilize the power-saving modes of the
CS5460A, and reset the CS5460A’s serial port.
The Conversion Window can be accessed by pulling down the Menu option, and selecting Conversion Window, or by pressing F3.
Figure 4. Conversion Window
13
CDB5460A
2.6.1 Single Conversion Button
On pressing this button, single conversions will be
performed repeatedly until the user presses the
Stop button. After each conversion is complete, the
Result data column will update with the values
present in each data register. The Mean and Standard Deviation columns will update every N cycles, where N is the number in the Samples to
Average box. Note that it can take many collection
cycles after pressing the Stop button before the data
actually stops being collected.
2.6.2 Continuous Conversions Button
This button functions similarly to the Single Conversion button, except that continuous conversions
are performed instead. The data on the screen is updated in the same fashion, and the Stop button terminates this action. There are some speed
limitations when performing this function, and if
any of these limitations are exceeded, the user will
be prompted to change some settings before proceeding.
2.6.3 Re-Initialize Serial Port Button
CS5460A data sheet to the part. This sequence
brings the CS5460A’s serial port back to a known
state. It does not reset any of the registers in the
part.
2.6.4 Standby / Sleep Mode Buttons
When these buttons are pressed, the part will enter
either Standby or Sleep power saving modes. To
return to normal mode, use the Power Up button.
2.6.5 Power Up Button
This button is used to send the Power Up/Halt command to the CS5460A. The part will return to normal operating mode and halt any conversions that
are being done at this time.
2.7 Viewing Pulse Rate Output Data
The CS5460A features a pulse-rate energy output.
The CDB5460A has the capability to demonstrate
the functionality of this output in the Pulse Rate
Output Window (Figure 5). The Pulse Rate Output
Window can be accessed by pressing the F4 key, or
by pulling down the Menu option, and selecting
Pulse Rate Window.
When this button is pressed, the software will send
the synchronization sequence discussed in the
Figure 5. Pulse Rate Output Window
14
CDB5460A
2.7.1 Integration Period Box
This box allows the user to select the length of time
which pulses will be collected over.
2.7.2 Periods To Average Box
limitations of the on-board microcontroller, some
higher pulse rates cannot be accurately collected. If
the pulse rate is too high, a warning message will
appear.
2.8 Data Collection Window Overview
This box allows the user to average a number of integration periods together.
2.7.3 Start Button
When the Start button is pressed, the CDB5460A
will capture pulse rate data according to the values
in the Integration Period and Periods to Average
boxes. After each integration period, the Pulse
Count and Frequency columns will be updated. The
Average Freq. and Standard Deviation columns
will only be updated after all of the integrations
have been collected. The software stops collecting
data when the user presses the Stop button, or when
the data collection is finished. Due to some speed
The Data Collection Window (Figure 6, Figure 7,
and Figure 8) allows the user to collect sample sets
of data from the CS5460A and analyze them using
time domain, FFT, and histogram plots. The Data
Collection Window is accessible through the Menu
option, or by pressing F5.
2.8.1 Time Domain / FFT / Histogram Selector
This menu selects the type of data processing to
perform on the collected data and display in the
plot area. Refer to the section on Analyzing Data
for more information.
Figure 6. Time Domain Analysis
15
CDB5460A
Figure 7. FFT Analysis
Figure 8. Histogram Analysis
16
CDB5460A
2.8.2 Collect Button
This button will collect data from the part, to be analyzed in the plot area. See the section on Collecting Data Sets for more information.
2.8.3 Config Button
This button will bring up the configuration window, in which the user can modify the data collection specifications. See the discussion of the Config
Window in this document.
2.8.4 Output Button
This button will bring up a window in which the
user can output the data to a file for later use, print
out a plot, or print out the entire screen.
Note: When saving data, only the data channel being displayed on the plot will be saved to a file.
2.8.5 Zoom Button
memory size on the CDB5460A, the maximum is
4096 samples when collecting two channels, and
2048 samples when collecting three channels.
2.9.2 Average
When doing FFT processing, this box will determine the number of FFTs to average. FFTs will be
collected and averaged when the Collect button is
pressed.
2.9.3 FFT Window
This box allows the user to select the type of windowing algorithm for FFT processing. Windowing
algorithms include the Blackman, Blackman-Harris, Hanning, 5-term Hodie, and 7-term Hodie. The
5-term Hodie and 7-term Hodie are windowing algorithms developed at Crystal Semiconductor.
2.9.4 Histogram Bin Width
This button allows the user to zoom in on the plot
by selecting two points in the plot area. Press the
Restore button to return to the normal data plot, or
press the Zoom button again to zoom in even further.
This box allows for a variable "bin width" when
plotting histograms of the collected data. Each vertical bar in the histogram plot will contain the number of output codes contained in this box.
Increasing this number may allow the user to view
histograms with larger input ranges.
2.8.6 Channel Select Buttons
2.9.5 Pages to Collect
Depending on the number of channels of information that has been collected, between 1 and 3 channel select buttons will appear below the graph,
allowing the user to choose the appropriate channel
for display. In the Time Domain mode, an additional button labeled "Overlay" will be present, to allow the user to display all of the channels on the
same plot.
This box determines the number of data "pages"
that the microcontroller will collect before sending
data to the PC. Each page consists of the number of
samples collected, and only the last page will be returned to the PC for processing. This function is
useful at higher sampling frequencies to minimize
board-level noise at the beginning of the conversion set.
2.9 Config Window
2.9.6 Data to Collect
The Config Window allows the user to set up the
data collection and analysis parameters.
These six check boxes allow the user to select the
data channels that will be collected and returned to
the PC for processing. Up to three channels can be
selected at once. There are some restrictions on the
speed and number of samples to collect when selecting more than one channel. A warning message
2.9.1 Number of Samples
This box allows the user to select the number of
samples to collect, between 16 and 8192. Due to
17
CDB5460A
will appear on pressing the Collect button in the
Data Collection Window if any speed limits appear
to be exceeded, but the data collection will still take
place.
2) Find the data file in the list and select it. Press
the Select button to return.
2.9.7 Accept Button
4) The data from the file should appear on the
screen. To select a different file, repeat the procedure.
When this button is pressed, the current settings
will be saved, and the user will return to the Data
Collection Window.
2.10 Collecting Data Sets
To collect a sample data set:
1) In the Data Collection Window, press the Config button to bring up the Configuration Window and view the current settings.
2) Select the appropriate settings from the available options (see the section on the Configuration Window) and press the Accept button.
3) The Data Collection Window should still be
visible. Press the Collect button to begin collecting data. A progress indicator bar will appear at the bottom of the screen during the data
collection process.
4) Data is first collected from the CS5460A and
stored in SRAM, and then transferred from the
SRAM to the PC through the RS-232 serial cable. Depending on the value of the Cycle Count
Register and the number of samples being collected, this process may take a long time. The
process can be terminated by pressing the Stop
button, but if this is done, the user should also
press Reset on the CDB5460A board.
5) Once the data has been collected, it can be analyzed, printed, or saved to disk.
2.11 Retrieving Saved Data From a File
The CDB5460A software allows the user to save
data to a file, and retrieve it later when needed. To
load a previously saved file:
1) Pull down the Setup option and select Disk. A
file menu will appear.
18
3) Go to the Data Collection Window, and press
the Collect button.
2.12 Analyzing Data
The evaluation software provides three types of
analysis tests - Time Domain, Frequency Domain,
and Histogram. The Time Domain analysis processes acquired conversions to produce a plot of
Magnitude versus Conversion Sample Number.
The Frequency Domain analysis processes acquired conversions to produce a magnitude versus
frequency plot using the Fast-Fourier transform
(results up to Fs/2 are calculated and plotted). Also,
statistical noise calculations are calculated and displayed. The Histogram analysis test processes acquired conversions to produce a histogram plot.
Statistical noise calculations are also calculated and
displayed.
2.13 Histogram Information
The following is a description of the indicators associated with Histogram Analysis. Histograms can be
plotted in the Data Collection Window by setting the
Time Domain / FFT / Histogram selector to Histogram (Figure 8).
2.13.1 BIN
Displays the x-axis value of the cursor on the Histogram.
2.13.2 MAGNITUDE
Displays the y-axis value of the cursor on the Histogram.
2.13.3 MAXIMUM
Indicator for the maximum value of the collected
data set.
CDB5460A
2.13.4 MEAN
2.14.1 FREQUENCY
Indicator for the mean of the data sample set. The
mean is calculated using the following formula:
Displays the x-axis value of the cursor on the FFT
display.
n -1
Σ
2.14.2 MAGNITUDE
Xi
Displays the y-axis value of the cursor on the FFT
display.
i= 0
M ean =
n
2.14.3 S/D
2.13.5 MINIMUM
Indicator for the Signal-to-Distortion Ratio, 4 harmonics are used in the calculations (decibels).
Indicator for the minimum value of the collected
data set.
2.14.4 S/N+D
2.13.6 STD. DEV.
Indicator for the Signal-to-Noise + Distortion Ratio
(decibels).
Indicator for the Standard Deviation of the collected data set. The Standard Deviation is calculated using the following formula
2.14.5 SNR
Indicator for the Signal-to-Noise Ratio, first 4 harmonics are not included (decibels).
n-1
S tD ev =
Σ
(X i - M ean) 2
i= 0
2.14.6 S/PN
Indicator for the Signal-to-Peak Noise Ratio (decibels).
n
2.14.7 # of AVG
2.13.7 VARIANCE
Indicates the Variance for the current data set. The
variance is calculated using the following formula:
n -1
V ar =
Σ
(X i - M ean) 2
i= 0
n
Displays the number of FFT’s averaged in the current display.
2.15 Time Domain Information
The following controls and indicators are associated with Time Domain Analysis. Time domain data
can be plotted in the Data Collection Window by setting the Time Domain / FFT / Histogram selector to
Time Domain (Figure 6).
2.14 Frequency Domain Information
2.15.1 COUNT
The following describe the indicators associated
with FFT (Fast Fourier Transform) Analysis. FFT
data can be plotted in the Data Collection Window
by setting the Time Domain / FFT / Histogram selector to FFT (Figure 7).
Displays current x-position of the cursor on the
time domain display.
2.15.2 MAGNITUDE
Displays current y-position of the cursor on the
time domain display.
19
CDB5460A
2.15.3 MAXIMUM
Indicator for the maximum value of the collected
data set.
2.15.4 MINIMUM
Indicator for the minimum value of the collected
data set.
20
Figure 9. Analog Schematic
CDB5460A
21
Figure 10. Digital Schematic Part 1
CDB5460A
22
Figure 11. Digital Schematic Part 2
CDB5460A
23
CDB5460A
Figure 12. Power Supply Schematic
24
Figure 13. Silkscreen
CDB5460A
25
Figure 14. Circuit Side
CDB5460A
26
Figure 15. Solder Side
CDB5460A
27
CDB5460A
3. ADDENDUM
3.1 Board Modifications for Charge Pump
The CDB5460A can be modified by the user, to include a charge pump circuit, whose output could be
used to supply the VA- supply pin in the +2.5V and
-2.5V analog power configuration. The diagram
below illustrates the schematic of such a circuit.
The components must be added by the user.
1) Header H1 allows a clock source to be clipped
across J1 with J2 open to analyze the charge
pump by itself or drive it asynchronous to the
CS5460A. With J1 open and J2 closed, the
pump is clocked synchronously with the
CS5460A. For best results, the charge pump
should be clocked synchronously with the
CS5460A.
nents C1, C2, D1 and D2. D1 and D2 are
BAT85 schottky diodes chosen for their speed
and low forward voltage. Capacitor C1 provides the necessary current at 4.096 MHz. Capacitor C2 provides extra storage if the load on
A- is increased. If the external reference is removed (and therefore the CS5460A is the only
load on A-) C2 can be removed. The bypass capacitors from VA+ to A- will be sufficient.
3) Header H2 connects the charge pump to A-. H2
can be removed to analyze the unloaded performance of the charge pump. This should be
closed for "charge-pump" mode operation.
4) A four-pin socket (U1) is added to connect an
optional clock oscillator to the XIN pin and easily operate the CS5460A in "external clock"
mode.
2) The charge pump is constructed from compo-
H1
C1
HD R
1.0 nF
D2
H2
B A T 85
HDR
J1
AJ2
D1
B AT 85
1.0 nF
C2
AGND
A GN D
AGND
XIN
D GN D
MC
CS 5460
HD R 10
D+
C LO CK
XINT
DG ND
A lread y E xists
Figure 16. CDB5460A Modifications for A- Charge Pump
28