CS4340
24-Bit, 96 kHz Stereo D/A Converter for Audio
Features
! 101
dB Dynamic Range
! -91 dB THD+N
! +3.0 V or +5.0 V Power Supply
! Low Clock Jitter Sensitivity
! Filtered Line-level Outputs
! On-chip Digital De-emphasis for 32, 44.1 and
48 kHz
! 33 mW with 3V Supply
! Popguard® Technology for Control of Clicks
and Pops
! Lead-free Packaging Available
Description
The CS4340 is a complete stereo digital-to-analog system
including digital interpolation, fourth-order delta-sigma dig-
ital-to-analog conversion, digital de-emphasis and
switched capacitor analog filtering. The advantages of this
architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no
linearity drift over time and temperature and a high tolerance to clock jitter.
The CS4340 accepts data at audio sample rates from
4 kHz to 100 kHz, consumes very little power, and operates over a wide power supply range. The features of the
CS4340 are ideal for DVD players, CD players, set-top box
and automotive systems.
ORDERING INFORMATION
CS4340-DSZ 16-pin SOIC, Lead Free,
CS4340-KS 16-pin SOIC
CS4340-KSZ 16-pin SOIC, Lead Free,
CS4340-CZZ 16-pin TSSOP, Lead Free,
CDB4340
Evaluation Board
-40 to 85 °C
-10 to 70 °C
-10 to 70 °C
-10 to 70 °C
I
SCLK/DEM1
DEM0
RST
De-emphasis
LRCK
Serial
Input
Interface
SDATA
DIF0 DIF1
www.cirrus.com
MUTEC
External
Mute Control
Interpolation
Filter
∆Σ DAC
Analog Filter
AOUTL
Interpolation
Filter
∆Σ DAC
Analog Filter
AOUTR
MCLK
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
JULY '05
DS297F3
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CS4340
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 4
SPECIFIED OPERATING CONDITIONS .............................................................................................. 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 4
ANALOG CHARACTERISTICS (CS4340-KS/KSZ/CZZ)....................................................................... 5
ANALOG CHARACTERISTICS (CS4340-DSZ) .................................................................................... 7
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE........................................ 8
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE........................................................ 11
SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK ..................................................... 12
DC ELECTRICAL CHARACTERISTICS.............................................................................................. 13
DIGITAL INPUT CHARACTERISTICS ................................................................................................ 13
DIGITAL INTERFACE SPECIFICATIONS........................................................................................... 13
2. PIN DESCRIPTION .............................................................................................................................. 14
3. TYPICAL CONNECTION DIAGRAM ................................................................................................. 15
4. APPLICATIONS ................................................................................................................................... 16
4.1 Sample Rate Range/Operational Mode ........................................................................................ 16
4.2 System Clocking ........................................................................................................................... 16
4.2.1 Internal Serial Clock Mode ............................................................................................... 16
4.2.2 External Serial Clock Mode .............................................................................................. 17
4.3 Digital Interface Format ................................................................................................................. 17
4.4 De-Emphasis ................................................................................................................................ 18
4.5 Power-up Sequence .................................................................................................................... 19
4.6 Popguard® Transient Control ........................................................................................................ 19
4.6.1 Power-up .......................................................................................................................... 19
4.6.2 Power-down ..................................................................................................................... 19
4.6.3 Discharge Time ................................................................................................................ 19
4.7 Mute Control ................................................................................................................................. 20
4.8 Grounding and Power Supply Arrangements ............................................................................... 20
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED
IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER
AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH
THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
2
DS297F3
CS4340
5. PARAMETER DEFINITIONS ................................................................................................................21
6. REFERENCES ......................................................................................................................................22
7. PACKAGE DIMENSIONS ....................................................................................................................23
7.1 SOIC ..............................................................................................................................................23
7.2 TSSOP ..........................................................................................................................................24
8. PACKAGE THERMAL RESISTANCE .................................................................................................25
LIST OF FIGURES
Figure 1. Output Test Load ...........................................................................................................................6
Figure 2. Maximum Loading..........................................................................................................................6
Figure 3. Single-Speed Stopband Rejection .................................................................................................9
Figure 4. Single-Speed Transition Band .......................................................................................................9
Figure 5. Single-Speed Transition Band (Detail)...........................................................................................9
Figure 6. Single-Speed Passband Ripple .....................................................................................................9
Figure 7. Double-Speed Stopband Rejection................................................................................................9
Figure 8. Double-Speed Transition Band......................................................................................................9
Figure 9. Double-Speed Transition Band (Detail) .......................................................................................10
Figure 10. Double-Speed Passband Ripple................................................................................................10
Figure 11. Serial Input Timing (External SCLK) ..........................................................................................11
Figure 12. Internal Serial Mode Input Timing ..............................................................................................12
Figure 13. Internal Serial Clock Generation ................................................................................................12
Figure 14. Typical Connection Diagram......................................................................................................15
Figure 15. CS4340 Format 0 - I2S up to 24-Bit Data ..................................................................................17
Figure 16. CS4340 Format 1 - Left Justified up to 24-Bit Data ...................................................................17
Figure 17. CS4340 Format 2 - Right Justified, 24-Bit Data.........................................................................18
Figure 18. CS4340 Format 3 - Right Justified, 16-Bit Data.........................................................................18
Figure 19. De-Emphasis Curve...................................................................................................................18
LIST OF TABLES
Table 1.CS4340 Speed Modes ...................................................................................................................16
Table 2.Single-Speed Mode Standard Frequencies ...................................................................................16
Table 3.Double-Speed Mode Standard Frequencies..................................................................................16
Table 4.Internal SCLK/LRCK Ratio.............................................................................................................17
Table 5.Digital Interface Format - DIF1 and DIF0 .......................................................................................17
Table 6.De-Emphasis Control .....................................................................................................................18
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CS4340
1.
CHARACTERISTICS AND SPECIFICATIONS
(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions.
Typical performance characteristics are derived from measurements taken at TA = 25°C.)
SPECIFIED OPERATING CONDITIONS (All voltages with respect to AGND = 0 V.)
Parameters
Symbol
Min
Nom
Max
Units
Nominal 3.3V
Nominal 5.0V
VA
VA
2.7
4.75
3.3
5.0
3.6
5.5
V
V
-KS/KSZ/CZZ
-DSZ
TA
TA
-10
-40
-
+70
+85
°C
°C
DC Power Supply
Specified Operating Temperature
(Power Applied)
ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to AGND. Operation
beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these
extremes.)
Parameters
Symbol
Min
VA
-0.3
6.0
V
Iin
-
±10
mA
VIND
-0.3
VA+0.4
V
Ambient Operating Temperature (power applied)
TA
-55
125
°C
Storage Temperature
Tstg
-65
150
°C
DC Power Supply
Input Current
Digital Input Voltage
(Note 1)
Max
Units
Notes: 1. Any pin except supplies.
4
DS297F3
CS4340
ANALOG CHARACTERISTICS (CS4340-KS/KSZ/CZZ) (Test conditions (unless otherwise
specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load
RL = 10 kΩ, CL = 10 pF (see Figure 1).)
VA = 5.0 V
Parameter
Single-Speed Mode
Dynamic Range
18 to 24-Bit
16-Bit
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
Double-Speed Mode
Dynamic Range
18 to 24-Bit
16-Bit
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
DS297F3
VA = 3.0 V
Min
Typ
Max
Min
Typ
Max
Unit
93
96
-
98
101
92
95
-
89
92
-
94
97
92
95
-
dB
dB
dB
dB
-
-91
-78
-38
-90
-72
-32
-86
-
-
-94
-74
-34
-91
-72
-32
-89
-
dB
dB
dB
dB
dB
dB
93
96
-
98
101
92
95
-
89
92
-
94
97
92
95
-
dB
dB
dB
dB
-
-91
-78
-38
-90
-72
-32
-86
-
-
-94
-74
-34
-91
-72
-32
-89
-
dB
dB
dB
dB
dB
dB
Fs = 48 kHz
(Note 2)
unweighted
A-Weighted
unweighted
A-Weighted
(Note 2)
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
Fs = 96 kHz
(Note 2)
unweighted
A-Weighted
unweighted
A-Weighted
(Note 2)
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
5
CS4340
ANALOG CHARACTERISTICS (CS4340-KS/KSZ/CZZ)
Parameters
Symbol
(Continued)
Min
Typ
Max
Units
-
102
-
dB
Interchannel Gain Mismatch
-
0.1
-
dB
Gain Drift
-
±100
-
ppm/°C
0.6•VA
0.7•VA
0.8•VA
Vpp
-
100
-
Ω
Dynamic Performance for All Modes
Interchannel Isolation (1 kHz)
DC Accuracy
Analog Output Characteristics and Specifications
Full Scale Output Voltage
Output Impedance
Minimum AC-Load Resistance
(Note 3)
RL
-
3
-
kΩ
Maximum Load Capacitance
(Note 3)
CL
-
100
-
pF
Notes: 2. One-half LSB of triangular PDF dither is added to data.
3. Refer to Figure 2.
.
3.3 µF
AOUTx
+
V
out
R
L
AGND
C
L
Capacitive Load -- C L (pF)
125
100
75
25
2.5
3
Figure 1. Output Test Load
6
Safe Operating
Region
50
5
10
15
20
Resistive Load -- RL (kΩ )
Figure 2. Maximum Loading
DS297F3
CS4340
ANALOG CHARACTERISTICS (CS4340-DSZ) (Test conditions (unless otherwise specified):
Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load
RL = 10 kΩ, CL = 10 pF (see Figure 1).)
VA = 5.0 V
Parameter
Single-Speed Mode
Dynamic Range
18 to 24-Bit
16-Bit
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
Double-Speed Mode
Dynamic Range
18 to 24-Bit
16-Bit
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
DS297F3
VA = 3.0 V
Min
Typ
Max
Min
Typ
Max
Unit
93
96
-
98
101
92
95
-
89
92
-
94
97
92
95
-
dB
dB
dB
dB
-
-91
-78
-38
-90
-72
-32
-86
-
-
-94
-74
-34
-91
-72
-32
-87
-
dB
dB
dB
dB
dB
dB
93
96
-
98
101
92
95
-
89
92
-
94
97
92
95
-
dB
dB
dB
dB
-
-91
-78
-38
-90
-72
-32
-86
-
-
-94
-74
-34
-91
-72
-32
-87
-
dB
dB
dB
dB
dB
dB
Fs = 48 kHz
(Note 2)
unweighted
A-Weighted
unweighted
A-Weighted
(Note 2)
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
Fs = 96 kHz
(Note 2)
unweighted
A-Weighted
unweighted
A-Weighted
(Note 2)
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
7
CS4340
ANALOG CHARACTERISTICS (CS4340-DSZ) (Continued)
Parameters
Symbol
Min
Typ
Max
Units
-
102
-
dB
Interchannel Gain Mismatch
-
0.1
-
dB
Gain Drift
-
±100
-
ppm/°C
0.6•VA
0.7•VA
0.8•VA
Vpp
-
100
-
Ω
Dynamic Performance for All Modes
Interchannel Isolation (1 kHz)
DC Accuracy
Analog Output Characteristics and Specifications
Full Scale Output Voltage
Output Impedance
Minimum AC-Load Resistance
(Note 3)
RL
-
3
-
kΩ
Maximum Load Capacitance
(Note 3)
CL
-
100
-
pF
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The
filter characteristics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be
referenced to the desired sample rate by multiplying the given characteristic by Fs.)
Parameter
Min
Typ
Max
Unit
0
0
-
0.4535
0.4998
Fs
Fs
Single-Speed Mode - (4 kHz to 50 kHz sample rates)
Passband
to -0.05 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz
-0.02
-
+0.08
dB
0.5465
-
-
Fs
50
-
-
dB
-
9/Fs
-
s
0 - 20 kHz
-
±0.36/Fs
-
s
Fs = 44.1 kHz
-
-
+0.05/-0.14
dB
0
0
-
0.4621
0.4982
Fs
Fs
Frequency Response 10 Hz to 20 kHz
-0.06
-
+0.2
dB
StopBand
0.577
-
-
Fs
55
-
-
dB
-
4/Fs
-
s
-
±1.39/Fs
±0.23/Fs
-
s
s
StopBand
StopBand Attenuation
(Note 4)
Group Delay
Passband Group Delay Deviation
De-emphasis Error (Relative to 1 kHz)
(Note 5)
Double-Speed Mode - (50 kHz to 100 kHz sample rates)
Passband
to -0.1 dB corner
to -3 dB corner
StopBand Attenuation
(Note 4)
Group Delay
Passband Group Delay Deviation
0 - 40 kHz
0 - 20 kHz
Notes: 4. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.
5. De-emphasis is only available in Single-Speed Mode.
8
DS297F3
CS4340
Figure 3. Single-Speed Stopband Rejection
Figure 5. Single-Speed Transition Band (Detail)
Figure 7. Double-Speed Stopband Rejection
DS297F3
Figure 4. Single-Speed Transition Band
Figure 6. Single-Speed Passband Ripple
Figure 8. Double-Speed Transition Band
9
CS4340
Figure 9. Double-Speed Transition Band (Detail)
10
Figure 10. Double-Speed Passband Ripple
DS297F3
CS4340
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
Parameters
Min
Max
Units
MCLK Frequency
1.024
25.6
MHz
MCLK Duty Cycle
45
55
%
4
50
50
100
kHz
kHz
40
60
%
Input Sample Rate
Symbol
Single-Speed Mode
Double-Speed Mode
Fs
Fs
LRCK Duty Cycle
SCLK Pulse Width Low
tsclkl
20
-
ns
SCLK Pulse Width High
tsclkh
20
-
ns
-
128xFs
64xFs
Hz
Hz
SCLK Frequency
Single-Speed Mode
Double-Speed Mode
SCLK rising to LRCK edge delay
tslrd
20
-
ns
SCLK rising to LRCK edge setup time
tslrs
20
-
ns
SDIN valid to SCLK rising setup time
tsdlrs
20
-
ns
SCLK rising to SDIN hold time
tsdh
20
-
ns
LRCK
t sclkh
t slrs
t slrd
t sclkl
SCLK
t sdlrs
t sdh
SDATA
Figure 11. Serial Input Timing (External SCLK)
DS297F3
11
CS4340
SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK
Parameters
Min
Typ
Max
Units
MCLK Frequency
1.024
-
25.6
MHz
MCLK Duty Cycle
45
-
55
%
4
50
-
50
100
kHz
kHz
Input Sample Rate
Symbol
Single-Speed Mode
Double-Speed Mode
Fs
Fs
LRCK Duty Cycle
%
(Note 6)
SCLK Period
tsclkw
1
---------------SCLK
-
-
s
tsclkr
-
t sclkw
-------------2
-
s
SDATA valid to SCLK rising setup time
tsdlrs
1
---------------------- + 10
( 512 )Fs
-
-
ns
SCLK rising to SDATA hold time
MCLK / LRCK = 512, 256 or 128
tsdh
1
---------------------- + 15
( 512 )Fs
-
-
ns
SCLK rising to SDATA hold time
MCLK / LRCK = 384 or 192
tsdh
1
---------------------- + 15
( 384 )Fs
-
-
ns
(Note 7)
SCLK rising to LRCK edge
Notes: 6. The Duty Cycle must be 50% +/− 1/2 MCLK Period.
7. See section 4.2.1 for derived internal frequencies.
LRCK
t sclkr
SDATA
t sclkw
t sdlrs
t sdh
*INTERNAL SCLK
Figure 12. Internal Serial Mode Input Timing
*The SCLK pulses shown are internal to the CS4340.
LRCK
MCLK
1
N
2
N
*INTERNAL SCLK
SDATA
Figure 13. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS4340. N equals MCLK divided by SCLK
12
DS297F3
CS4340
DC ELECTRICAL CHARACTERISTICS
(AGND = 0 V; all voltages with respect to AGND.)
Parameters
Symbol
Min
Typ
Max
Units
IA
IA
-
15
11
18
14
mA
mA
-
75
33
90
42
mW
mW
-
60
30
-
µA
µA
-
0.3
0.09
-
mW
mW
-
60
40
-
dB
dB
VQ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
0.45•VA
250
0.01
-
kΩ
Filt+ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
VA
250
0.01
-
mA
MUTEC Low-Level Output Voltage
-
0
-
V
MUTEC High-Level Output Voltage
-
VA
-
V
Maximum MUTEC Drive Current
-
3
-
mA
Normal Operation (Note 8)
Power Supply Current
VA = 5.0 V
VA = 3.0 V
Power Dissipation
VA = 5.0 V
VA = 3.0 V
Power-down Mode (Note 9)
Power Supply Current
VA = 5.0 V
VA = 3.0 V
Power Dissipation
VA = 5.0 V
VA = 3.0 V
IA
All Modes of Operation
Power Supply Rejection Ratio (Note 10)
1 kHz
60 Hz
PSRR
V
mA
V
kΩ
Notes: 8. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input sampled at the highest Fs for
each speed mode, and open outputs, unless otherwise specified.
9. Power Down Mode is defined as RST = LO with all clocks and data lines held static.
10. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 14. Increasing the
capacitance will also increase the PSRR.
DIGITAL INPUT CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.)
Parameters
Input Leakage Current
Symbol
Min
Typ
Max
Units
Iin
-
-
±10
µA
-
8
-
pF
Input Capacitance
DIGITAL INTERFACE SPECIFICATIONS
Parameters
(AGND = 0 V; all voltages with respect to AGND.)
Symbol
Min
Max
Units
High-Level Input Voltage
VIH
2.0
-
V
Low-Level Input Voltage
VIL
-
0.8
V
High-Level Input Voltage
VIH
2.0
-
V
Low-Level Input Voltage
VIL
-
0.8
V
3.3 V Logic (3.0 V to 3.6 V DC Supply)
5.0 V Logic (4.75 V to 5.25 V DC Supply)
DS297F3
13
CS4340
2.
PIN DESCRIPTION
RST
1
16
MUTEC
SDATA
2
15
AOUTL
SCLK/DEM1
3
14
VA
LRCK
4
13
AGND
MCLK
5
12
AOUTR
DIF1
6
11
REF_GND
DIF0
7
10
VQ
DEM0
8
9
FILT+
Pin Name
#
Pin Description
RST
1
Reset (Input) - Powers down device.
SDATA
2
Serial Audio Data (Input) - Input for two’s complement serial audio data.
SCLK
3
Serial Clock (Input) -Serial clock for the serial audio interface.
DEM1
DEM0
3
8
De-emphasis Control (Input) - Selects the standard 15 µs/50 µs digital de-emphasis filter
response for 44.1 kHz sample rate.
LRCK
4
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
MCLK
5
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
DIF1
DIF0
6
7
Digital Interface Format (Input) - Defines the required relationship between the Left Right
Clock, Serial Clock and Serial Audio Data.
FILT+
9
Positive Voltage Reference (Output) - Positive voltage reference for the internal sampling circuits.
VQ
10
Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
REF_GND
11
Reference Ground (Input) - Ground reference for the internal sampling circuits.
AOUTR
AOUTL
12
15
Analog Outputs (Output) - The full scale analog output level is specified in the Analog Characteristics table.
AGND
13
Analog Ground (Input)
VA
14
Power (Input) - Positive power for the analog, digital and serial audio interface sections.
MUTEC
16
Mute Control (Output) - Control signal for an optional mute circuit.
14
DS297F3
CS4340
3.
TYPICAL CONNECTION DIAGRAM
+3.0 V to +5.0 V
+
0.1 µF
14
1 µF
VA
2
Serial Audio
Data
Processor
3
4
SDATA
3.3 µF
SCLK/DEM1
AOUT L
560 Ω
Left
Audio
O utput
15
+
LRCK
C
10 k Ω
RL
CS4340
M UTEC 16
External Clock
5
M CLK
FILT+
VQ
6
7
Mode
Configuration
OPTIONAL
MUTE
CIRCUIT
9
+
10
.1 µF + 1 µF
0.1 µF
1 µF
11
REF_GND
DIF1
3.3 µF
DIF0
560 Ω
Right
Audio
O utput
12
8
AOUTR
DEM0
1
+
10 k Ω
RST
RL
C
AGND
13
C=
R L + 560
4 π F S R L 560
Figure 14. Typical Connection Diagram
DS297F3
15
CS4340
4. APPLICATIONS
4.1
Sample Rate Range/Operational Mode
The device operates in one of two operational modes determined by the Master Clock to Left/Right Clock ratio (see
section 4.2). Sample rates outside the specified range for each mode are not supported.
Input Sample Rate (Fs)
4 kHz - 50 kHz
50 kHz - 100 kHz
MODE
Single-Speed Mode
Double-Speed Mode
Table 1. CS4340 Speed Modes
4.2
System Clocking
The device requires external generation of the master (MCLK) and left/right (LRCK) clocks. The device also requires
external generation of the serial clock (SCLK) if the internal serial clock is not used. The LRCK, defined also as the
input sample rate Fs, must be synchronously derived from MCLK according to specified ratios. The specified ratios
of MCLK to LRCK, along with several standard audio sample rates and the required MCLK frequency, are illustrated
in Tables 2 and 3.
Sample Rate
(kHz)
32
44.1
48
256x
8.1920
11.2896
12.2880
MCLK (MHz)
384x
12.2880
16.9344
18.4320
512x
16.3840
22.5792
24.5760
Table 2. Single-Speed Mode Standard Frequencies
Sample Rate
(kHz)
64
88.2
96
MCLK (MHz)
128x
8.1920
11.2896
12.2880
192x
12.2880
16.9344
18.4320
Table 3. Double-Speed Mode Standard Frequencies
4.2.1 Internal Serial Clock Mode
The device will enter the Internal Serial Clock Mode if no low to high transitions are detected on the SCLK pin
for 2 consecutive periods of LRCK. In this mode, the SCLK is internally derived and synchronous with MCLK
and LRCK. The SCLK/LRCK ratio is either 32, 48, or 64 depending upon the MCLK/LRCK ratio and the Digital
Interface Format selection (see Table 4).
16
DS297F3
CS4340
The internal serial clock is utilized when additional de-emphasis control is required. Operation in the Internal
Serial Clock mode is identical to operation with an external SCLK synchronized with LRCK; however, External
SCLK mode is recommended for system clocking applications.
Input
MCLK/LRCK
Ratio
512, 256, 128
384, 192
512, 256, 128
Digital Interface Format Selection
Left Justified 24 Right Justified
Right Justified
Bits
24 Bits
16 Bits
I2S up to 24
Bits
X
-
-
X
Internal
SCLK/LRCK
Ratio
32
X
X
X
X
48
-
X
X
-
64
Table 4. Internal SCLK/LRCK Ratio
4.2.2 External Serial Clock Mode
The device will enter the External Serial Clock Mode whenever 16 low to high transitions are detected on the
SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial Clock Mode if no low
to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK.
4.3
Digital Interface Format
The device will accept audio samples in several digital interface formats as illustrated in Table 5. The desired format
is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship between LRCK, SCLK and
SDIN, see Figures 15 through 18.
DIF1
0
0
1
1
DIF0
0
1
0
1
DESCRIPTION
FORMAT
0
1
2
3
I2S, up to 24-bit data
Left Justified, up to 24-bit data
Right Justified, 24-bit Data
Right Justified, 16-bit Data
FIGURE
15
16
17
18
Table 5. Digital Interface Format - DIF1 and DIF0
Left C ha nnel
LR C K
R ig ht C ha nnel
SCLK
SDIN
MSB
+5 +4 +3 +2 +1
-1 -2 -3 -4 -5
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 15. CS4340 Format 0 - I2S up to 24-Bit Data
Left C ha nnel
LR C K
R ig ht C ha nnel
SCLK
SDIN
MSB -1
-2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB -1
-2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 16. CS4340 Format 1 - Left Justified up to 24-Bit Data
DS297F3
17
CS4340
LRCK
R ight Cha nnel
Left Channel
SCLK
SDIN
0
7
23 22 21 20 19 18
6
5
4
3
2
1
0
7
23 22 21 20 19 18
6
5
4
3
2
1
0
Figure 17. CS4340 Format 2 - Right Justified, 24-Bit Data
32 clo cks
LRCK
R ight Cha nnel
Left Channel
SCLK
SDIN
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Figure
18. CS4340 Format 3 - Right Justified, 16-Bit Data
32 clo cks
4.4
De-Emphasis
The device includes on-chip digital de-emphasis. Figure 19 shows the de-emphasis curve for Fs equal to 44.1 kHz.
The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs.
Pin 8 is available for de-emphasis control and selects the 44.1 kHz de-emphasis filter. If the Internal Serial Clock is
used, pin 3 is also available for additional de-emphasis control and, in combination with pin 8, selects either the 32,
44.1, or 48 kHz de-emphasis filter. Please see Table 6 for the desired de-emphasis control.
Gain
dB
Internal SCLK
T1=50 µs
0dB
T2 = 15 µs
-10dB
DEM1
0
0
1
1
DEM0 Description
0
Disabled
1
44.1 kHz
0
48 kHz
1
32 kHz
External SCLK
DEM0 Description
0
1
Disabled
44.1 kHz
Table 6. De-Emphasis Control
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 19. De-Emphasis Curve
18
DS297F3
CS4340
4.5
Power-up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supply and configuration pins
are stable, and the clocks are locked to the appropriate frequencies discussed in section 4.2. It is also recommended
that reset be enabled if the analog supply drops below the minimum specified operating voltage to prevent power
glitch related issues.
4.6
Popguard® Transient Control
The CS4340 uses Popguard® technology to minimize the effects of output transients during power-up and powerdown. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes
the audio transients commonly produced by single-ended single-supply converters. It is activated inside the DAC
when RST is enabled/disabled and requires no other external control, aside from choosing the appropriate DCblocking capacitors.
4.6.1 Power-up
When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins. This gradual
voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing the power-up transient.
4.6.2 Power-down
To prevent transients at power-down, the device must first enter its power-down state by enabling RST. When
this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR.
In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for
the next power-on.
4.6.3 Discharge Time
To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking capacitors
have fully discharged before turning on the power or exiting the power-down state. If not, a transient will occur
when the audio outputs are initially clamped to AGND. The time that the device must remain in the powerdown state is related to the value of the DC-blocking capacitance. For example, with a 3.3 µF capacitor, the
minimum power-down time will be approximately 0.4 seconds.
DS297F3
19
CS4340
4.7
Mute Control
The Mute Control pin goes high during power-up initialization, reset, or if the MCLK to LRCK ratio is incorrect. The
pin will also go high following the reception of 8192 consecutive audio samples of static 0 or -1 on both the left and
right channels. A single sample of non-zero data on either channel will cause the Mute Control pin to go low. This
pin is intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in
any single-ended single supply system.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in
extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle
channel noise/signal-to-noise ratios which are only limited by the external mute circuit. See the CDB4340 data sheet
for a suggested mute circuit.
4.8
Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4340 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 14 shows the recommended power arrangements, with
VA connected to a clean supply. If the ground planes are split between digital ground and analog ground, REF_GND
& AGND should be connected to the analog ground plane.
Decoupling capacitors should be as close to the DAC as possible, with the low value ceramic capacitor being the
closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling
into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and REF_GND (as well as VQ and REF_GND), and should also be located on
the same layer as the DAC. The CDB4340 evaluation board demonstrates the optimum layout and power supply
arrangements.
20
DS297F3
CS4340
5. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
effect the measurement. This measurement technique has been accepted by the Audio Engineering
Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
DS297F3
21
CS4340
6. REFERENCES
1) CDB4340 Evaluation Board Datasheet
22
DS297F3
CS4340
7. PACKAGE DIMENSIONS
7.1
SOIC
16L SOIC (150 MIL BODY) PACKAGE DRAWING
E
H
1
b
c
D
SEATING
PLANE
∝
A
L
e
DIM
A
A1
b
C
D
E
e
H
L
∝
MIN
0.053
0.004
0.013
0.0075
0.386
0.150
0.040
0.228
0.016
0°
A1
INCHES
NOM
0.064
0.006
0.016
0.008
0.390
0.154
0.050
0.236
0.025
4°
MAX
0.069
0.010
0.020
0.010
0.394
0.157
0.060
0.244
0.050
8°
MIN
1.35
0.10
0.33
0.19
9.80
3.80
1.02
5.80
0.40
0°
MILLIMETERS
NOM
1.63
0.15
0.41
0.20
9.91
3.90
1.27
6.0
0.64
4°
MAX
1.75
0.25
0.51
0.25
10.00
4.00
1.52
6.20
1.27
8°
JEDEC #: MS-012
Controling Dimension is Millimeters
DS297F3
23
CS4340
7.2
TSSOP
16L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11
A2
E
A
∝
e
b2
SIDE VIEW
A1
L
END VIEW
SEATING
PLANE
1 2 3
TOP VIEW
DIM
A
A1
A2
b
D
E
E1
e
L
∝
MIN
-0.002
0.03346
0.00748
0.193
0.248
0.169
-0.020
0°
INCHES
NOM
-0.004
0.0354
0.0096
0.1969
0.2519
0.1732
0.026 BSC
0.024
4°
MAX
0.043
0.006
0.037
0.012
0.201
0.256
0.177
-0.028
8°
MIN
-0.05
0.85
0.19
4.90
6.30
4.30
-0.50
0°
MILLIMETERS
NOM
--0.90
0.245
5.00
6.40
4.40
0.065 BSC
0.60
4°
NOTE
MAX
1.10
0.15
0.95
0.30
5.10
6.50
4.50
-0.70
8°
2,3
1
1
JEDEC #: MO-153
Controlling Dimension is Millimeters
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
24
DS297F3
CS4340
8. PACKAGE THERMAL RESISTANCE
Package
SOIC
TSSOP
DS297F3
(for multi-layer boards)
(for multi-layer boards)
Symbol
Min
Typ
Max
Units
θJA
θJA
-
74
89
-
°C/Watt
°C/Watt
25