CIRRUS CS48500

CS48500 Data Sheet
‰ Cost-effective, High-performance 32-bit DSP
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300,000,000 MAC/S (multiply accumulates per second)
Dual MAC cycles per clock
72-bit accumulators are the most accurate in the industry
24k x 32 SRAM, 2k blocks - assignable to data or program
Internal ROM contains a variety of configurable sound
enhancement feature sets
— 8-channel internal DMA
— Internal watch-dog DSP lock-up prevention
Differentiating from the legacy Cirrus multi-standard, multichannel decoders, this new CS48500 family is still based on
the same high-performance 32-bit fixed point DSP Digital
Signal Processor core but instead is equipped with much less
memory, tailoring it for more cost-effective applications
associated with multi-channel and virtual-channel sound
enhancements. Target applications are:
— Digital Televisions
— Multimedia Peripherals
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‰ DSP Tool Set w/ Private Keys for Protecting Customer IP
‰ Configurable Serial Audio Inputs/Outputs
In these applications there are a wide variety of licensable DSP
IP codes available today from:
Configurable for all input/output types
Maximum 32-bit @ 192 kHz
Supports 32-bit audio sample I/O between DSP chips
TDM input modes (multiple channels on same line)
192 kHz SPDIF transmitter
Multi-channel DSD direct stream digital SACD input
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iPod® Docking Stations
Automotive Head Units
Automotive Outboard Amplifiers
HD-DVD & Blu-ray Disc DVD Receivers
PC Speakers
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FEATURES
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‰ Supports Two Different Input Fs Sample Rates
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Output can be master or slave
Dual processing path capability
Input supports dual domain slave clocking
Hardware assist time sampling for sample rate conversion
‰ Integrated Clock Manager/PLL
— Can operate from external crystal, external oscillator
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The CS48500 is programmed using the Cirrus proprietary DSP
Composer™ GUI development tool. Processing chains may
be designed using a drag-and-drop interface to place/utilize
functional macro audio DSP primitives. The end result is a
software image that is down-loaded to the DSP via serial host
or serial boot modes.
Input Fs Auto Detection
Host & Boot via Serial Interface
Configurable GPIOs and External Interrupt Input
1.8V Core / 3.3V I/O that are +5V Tolerant
Low-power Mode
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— "Energy-Star Ready" via low-power mode, 350uW in standby
12 Ch. Audio In /
6 Ch. SACD In
S/PDIF
Cirrus also has developed, or is developing their own royaltyfree versions of popular features sets like Cirrus Bass
Manager, Cirrus Dynamic Volume Leveler, Cirrus Original
Multichannel Surround, Cirrus Virtual Speaker & Cirrus 3DAudio.
Ordering Information:
See page 23 for ordering information
Serial
Control 1
GPIO
Debug
Watchdog
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32-bit
DSP
P
X
TMR1
TMR2
Y
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12 Ch PCM
Audio Out
PLL
Advance Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
©Copyright 2006 Cirrus Logic, Inc.
http://www.cirrus.com
CONFIDENTIAL
DEC ’06
DS734A3
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CS48500 Data Sheet
32-bit Audio Decoder DSP Family
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com.
IMPORTANT NOTICE
"Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS"
without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including
those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by
furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual
property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use
within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general
distribution, advertising or promotional purposes, or for creating any work for resale.
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN
AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES,
LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE
FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A
MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM
ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, the Cirrus Logic logo designs, DSP Composer, and Cirrus Framework are trademarks of Cirrus Logic, Inc. All other brand and product names in
this document may be trademarks or service marks of their respective owners.
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Dolby, Dolby Digital, Dolby Headphone, Dolby Virtual Speaker, Dolby Headphone, and Pro Logic are registered trademarks of Dolby Laboratories, Inc. Supply of an
implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or Intellectual Property Right of Dolby Laboratories, to use the Implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby
Laboratories.
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DTS is a registered trademark of the Digital Theater Systems, Inc. DTS Neo:6 is a trademark of Digital Theater Systems, Inc. It is hereby notified that a third-party
license from DTS is necessary to distribute software of DTS in any finished end-user or ready-to-use final product.
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SRS, Circle Surround and Trusurround XT are registered trademarks of SRS Labs, Inc. Circle Surround II is a trademark of SRS Labs, Inc. The CIRCLE SURROUND
TECHNOLOGY rights incorporated in the Cirrus Logic chip are owned by SRS Labs, Inc. and by Valence Technology Ltd., and licensed to Cirrus Logic, Inc.
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Users of any Cirrus Logic chip containing enabled CIRCLE SURROUND TECHNOLOGY® (i.e., CIRCLE SURROUND® LICENSEES) must first sign a license to purchase production quantities for consumer electronics applications which may be granted upon submission of a preproduction sample to, and the satisfactory passing
of performance verification tests performed by SRS Labs, Inc., or Valence Technology Ltd. E-mail requests for performance specifications and testing rate schedule
may be made to [email protected] SRS Labs, Inc. and Valence Technology, Ltd., reserve the right to decline a use license for any submission that does not
pass performance specifications or is not in the consumer electronics classification.
All equipment manufactured using any Cirrus Logic chip containing enabled CIRCLE SURROUND® TECHNOLOGY must carry the Circle Surround® logo on the front
panel in a manner approved in writing by SRS Labs, Inc., or Valence Technology Ltd. If the Circle Surround® logo is printed in users manuals, service manuals or
advertisements, it must appear in a form approved in writing by SRS Labs, Inc., or Valence Technology, Ltd. The rear panel of Circle Surround® products, users
manuals, service manuals, and all advertising must all carry the legends as described in LICENSOR'S most current version of the CIRCLE SURROUND Trademark
Usage Manual.
SPI is a trademark of Motorola, Inc.
I2C is a registered trademark of Philips Semiconductor.
iPod is a registered trademark of Apple Computer, Inc.
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©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
DS734A3
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
Table of Contents
1. Documentation Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3. Code Overlays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4. Hardware Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
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4.1 DSP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1.1 DSP Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1.2 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 On-chip DSP Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.1 Digital Audio Input Port (DAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.2 Digital Audio Output Port (DAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.3 Serial Control Port (I2C® or SPI™) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.4 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.5 PLL-based Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.6 Hardware Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 DSP I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.1 Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.2 Termination Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.3 Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4 Application Code Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5. Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Digital DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Power Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 Thermal Data (48 LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 Switching Characteristics— RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7 Switching Characteristics — XTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8 Switching Characteristics — Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10 Switching Characteristics — Serial Control Port - SPI Master Mode . . . . . . . . . . . . . . . . . . . . . . . . .
5.11 Switching Characteristics — Serial Control Port - I2C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12 Switching Characteristics — Serial Control Port - I2C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . .
5.13 Switching Characteristics — Digital Audio Slave Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.14 Switching Characteristics — DSD Slave Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.15 Switching Characteristics — Digital Audio Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8. Device Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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8.2 CS48540, 48-pin LQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.3 CS48560,48-pin LQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9. Package Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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9.1 48-pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DS734A3
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
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CS48500 Data Sheet
32-bit Audio Decoder DSP Family
List of Figures
List of Tables
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Figure 1. RESET Timing .........................................................................................................................14
Figure 2. XTI Timing................................................................................................................................15
Figure 3. Serial Control Port - SPI Slave Mode Timing...........................................................................16
Figure 4. Serial Control Port - SPI Master Mode Timing.........................................................................17
Figure 5. Serial Control Port - I2C Slave Mode Timing ...........................................................................18
Figure 6. Serial Control Port - I2C Master Mode Timing .........................................................................19
Figure 7. Digital Audio Input (DAI) Port Timing Diagram ........................................................................20
Figure 8. Direct Stream Digital - Serial Audio Input Timing.....................................................................21
Figure 9. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode........................21
Figure 10. Digital Audio Output Data, Input and Output Clock Timing....................................................22
Figure 11. Digital Audio Port Timing, MCLK Master Mode .....................................................................22
Figure 12. CS48520, 48-Pin LQFP Pinout ..............................................................................................24
Figure 13. CS48540, 48-Pin LQFP Pinout ..............................................................................................25
Figure 14. CS48560, 48-Pin LQFP Pinout ..............................................................................................26
Figure 15. 48-Pin LQFP Package Drawing .............................................................................................27
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Table 1. CS48500 Related Documentation...............................................................................................5
Table 2. Device and Firmware Selection Guide........................................................................................8
Table 3. Ordering Information .................................................................................................................23
Table 4. Environmental, Manufacturing, & Handling Information............................................................23
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©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
DS734A3
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
1. Documentation Strategy
The CS48500 Data Sheet describes the CS48500 family of multichannel audio processors. This
document should be used in conjunction with the following documents when evaluating or designing a
system around the CS48500 family of processors.
Description
CS48500 Data Sheet
This document
CS48500 Hardware User’s Manual
Includes detailed system design information
including Typical Connection Diagrams, BootProcedures, Pin Descriptions, Etc.
AN298 - CS48500 Firmware User’s Manual
Includes detailed firmware design information
including signal processing flow diagrams and
control API information
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Document Name
DSP Composer User’s Manual
Includes detailed configuration and usage
information for the GUI development tool.
Table 1. CS48500 Related Documentation
The scope of the CS48500 Data Sheet is primarily the hardware specifications of the CS48500 family of
devices. This includes hardware functionality, characteristic data, pinout, and packaging information.
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The intended audience for the CS48500 Data Sheet is the system PCB designer, mcu programmer, and
the quality control engineer.
DS734A3
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
5
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
2. Overview
The CS48500 DSP Family is designed to provide high-performance post-processing and mixing of ditial
audio. The dual clock domain provided on the PCM inputs allows for the mixing of audio streams with
different sampling frequencies. The low-power standby preserves battery life for applications which are
always on, but not necessarily processing audio, such as automotive audio systems.
There are three devices comprising the CS48500 family. The CS48520, CS48540 and CS48560 are
differentiated by the number of inputs and outputs available. All DSPs support dual input clock domains
and dual audio processing paths. All DSPs are available in a 48-pin QFP package. Please refer to Table
2 on page 8 for the input, output, firmware features of each device.
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2.1 Licensing
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Licenses are required for all of the 3rd party audio processing algorithms listed in Section 3. Please
contact your local Cirrus Logic Sales representative for more information.
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©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
DS734A3
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
3. Code Overlays
The suite of software available for the CS48500 family consists of an operating system (OS) and a library
of overlays. The overlays have been divided into three main groups called Matrix-processors, Virtualizerprocessors, and Post-processors. All software components are defined below:
1. OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external
memory, processing host messages, calling audio-processing subroutines, error concealment, etc.
2. Matrix-processor- Any Module that performs a matrix decode on PCM data to produce more output
channels than input channels (2Ön channels). Examples are Dolby ProLogic IIx and DTS Neo:6.
Generally speaking, these modules increase the number of valid channels in the audio I/O buffer.
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3. Virtualizer-processor - Any module that encodes PCM data into fewer output channels than input
channels (nÖ2 channels) with the effect of providing “phantom” speakers to represent the physical audio
channels that were eliminated. Examples are Dolby Headphone® and Dolby Virtual Speaker®. Generally
speaking, these modules reduce the number of valid channels in the audio I/O buffer.
4. Post-processors - Any module that processes audio I/O buffer PCM data in-place after the matrix- or
virtualizer-processors. Examples are bass management, audio manager, tone control, EQ, delay,
customer-specific effects, etc.
The bulk of each overlay is stored in ROM within the CS48500, but a small image is required to configure
the overlays and boot the DSP. This small image can either be stored in an external serial
FLASH/EEPROM, or downloaded via a host controller through the SPI™/I2C® serial port.
The overlay structure reduces the time required to reconfigure the DSP when a processing change is
requested. Each overlay can be reloaded independently without disturbing the other overlays. For
example, when a new matrix-processor is selected, the OS, virtualizer-, and post-processors do not
need to be reloaded — only the new matrix-processor (the same is true for the other overlays).
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Table 2 below lists the firmware available based on device selection. Please refer AN298, CS48500
Firmware User’s Manual for the latest listing of application codes and Cirrus Framework™ modules
available.
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Chanenel Count
Input/Output
CS48540 features Plus
12 channel Car Audio
High-end Digital TV
Dual Source/Dual Zone
SACD
CS48520 features Plus
8 Channel Car Audio
DVD Receiver
Digital TV
Portable Audio Docking Station
Portable DVD
DVD Mini / Receiver
Multimedia PC Speakers
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Up to 12 channel in /12 channel
out
Up to 8 channel in / 8 channel
out
Up to 4 channel in / 4 channel
out
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Suggested
Application
Table 2. Device and Firmware Selection Guide
Note: Refer to AN298 for more information on Software features
CS48560-DQZ
CS48560-CQZ
CS48540-DQZ
CS48540-CQZ
CS48520-CQZ
Device
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48-pin QFP
48-pin QFP
48-pin QFP
Package
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
DS734A3
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
4. Hardware Functional Description
4.1 DSP Core
The CS48500 is a single-core DSP with separate X and Y data and P code memory spaces. The DSP
core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing
two multiply-and-accumulate (MAC) operations per clock cycle. The DSP core has eight 72-bit
accumulators, four X- and four Y-data registers, and 12 index registers.
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The DSP core is coupled to a flexible DMA engine. The DMA engine can move data between peripherals
such as the serial control port (SCP), digital audio input (DAI) and digital audio output (DAO), or any DSP
core memory, all without the intervention of the DSP. The DMA engine off loads data move instructions
from the DSP core, leaving more MIPS available for signal processing instructions.
CS48500 functionality is controlled by application codes that are stored in on-board ROM or downloaded
to the CS48500 from a host controller or external serial FLASH/EEPROM.
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Users can develop their applications using DSP Composer to create the processing chain and then
compile the image into a series of commands that are sent to the CS48500 through the SCP. The
processing application can either load modules (matrix-processors, virtualizers, post-processors) from
the DSPs on-board ROM, or custom firmware can be downloaded through the SCP.
The CS48500 is suitable for a variety of audio post-processing applications such as automotive headends, automotive amplifiers, and boom boxes.
4.1.1 DSP Memory
The DSP core has its own on-chip data and program RAM and ROM and does not require external
memory for post-processing applications.
The Y-RAM and P-RAM share a single block of memory that can be configured to make Y and P equal in
size, or more memory can be allocated for Y-RAM in 2kword blocks.
4.1.2 DMA Controller
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The powerful 8-channel DMA controller can move data between 8 on-chip resources. Each resource has
its own arbiter: X, Y, and P RAMs/ROMs and the peripheral bus. Modulo and linear addressing modes
are supported, with flexible start address and increment controls. The service intervals for each DMA
channel, as well as up to 6 interrupt events, are programmable.
DS734A3
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
9
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
4.2 On-chip DSP Peripherals
4.2.1 Digital Audio Input Port (DAI)
Each version of the CS48500 support a different number of input channels. Refer toTable 2 on page 8 for
more details.
FT
The DAI port supports a wide variety of data input formats at sample rates (Fs) as high as 192 kHz. The
port is capable of accepting PCM or DSD formats. Up to 32-bit word lengths are supported. DSD is
supported and internally converted to PCM before processing. The DAI also supports a time division
multiplexed (TDM) one-line data mode, that packs PCM audio on a single data line (the total number
possible depends on the ratio of SCLK to LRCLK and the version of chip. For example on the CS48520
only 4 ch of PCM are supported in one line mode and on the CS48560 up to 8 channels are supported.).
EN
D TI
EL A
L
PH D
I RA
The port has two independent slave-only clock domains. Each data input can be independently assigned
to a clock domain. The sample rate of the input clock domains can be determined automatically by the
DSP, off-loading the task of monitoring the SPDIF receiver from the host. A time-stamping feature allows
the input data to be sample-rate converted via software.
4.2.2 Digital Audio Output Port (DAO)
Each version of the CS48500 support a different number of output channels. Refer toTable 2 on page 8
for more details.
DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as 192
kHz. The port can be configured as an independent clock domain mastered by the DSP, or as a clock
slave if an external MCLK or SCLK/LRCLK source is available. One of the serial audio pins can be reconfigured as a SPDIF transmitter that drives a bi-phase encoded S/PDIF signal (data with embedded
clock on a single line).
4.2.3 Serial Control Port (I2C® or SPI™)
D
The on-chip serial control port is capable of operating as master or slave in either SPI™ or I2C® modes.
Master/Slave operation is chosen by mode select pins when the CS48500 comes out of reset. The serial
clock pin can support frequencies as high as 25 MHz in SPI mode (SPI clock speed must always be ≤
(Fdclk/2)). The CS48500 serial control port also includes a pin for flow control of the communications
interface (#SCP_BSY) and a pin to indicate when the DSP has a message for the host (#SCP_IRQ).
4.2.4 GPIO
N
FI
Many of the CS48500 peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an
output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge,
falling edge, active-low, or active-high.
4.2.5 PLL-based Clock Generator
C
O
The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to
clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can
be output on the DAO port for driving audio converters. The CS48500 defaults to running from the
external reference frequency and is switched to use the PLL output after overlays have been loaded and
configured, either through master boot from an external FLASH or through host control. A built-in crystal
oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable
between 1:1 (default) or 2:1.
10
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
DS734A3
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
4.2.6 Hardware Watchdog Timer
The CS48500 has an integrated watchdog timer that acts as a “health” monitor for the DSP. The
watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset. This
peripheral ensures that the CS48500 will reset itself in the event of a temporary system failure. In standalone mode (i.e. no host mcu), the DSP will reboot from external FLASH. In slave mode (i.e. host mcu
present) a GPIO will be used to signal the host that the watchdog has expired and the DSP should be
rebooted and re-configured.
4.3 DSP I/O Description
4.3.1 Multiplexed Pins
FT
Many of the CS48500 pins are multi-functional. For details on pin functionality please refer to the
CS48500 Hardware User’s Manual.
4.3.2 Termination Requirements
EN
D TI
EL A
L
PH D
I RA
Open-drain pins on the CS48500 must be pulled high for proper operation. Please refer to the CS48500
Hardware User’s Manual to identify which pins are open-drain and what value of pull-up resistor is
required for proper operation.
Mode select pins on the CS48500 are used to select the boot mode upon the rising edge from reset. A
detailed explanation of termination requirements for each communication mode select pin can be found
in the CS48500 Hardware User’s Manual.
4.3.3 Pads
The CS48500 I/Os operate from the 3.3 V supply and are 5 V tolerant.
4.4 Application Code Security
C
O
N
FI
D
The external program code may be encrypted by the programmer to protect any intellectual property it
may contain. A secret, customer-specific key is used to encrypt the program code that is to be stored
external to the device. Please contact your local Cirrus representative for details.
DS734A3
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
11
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
5. Characteristics and Specifications
Note:
All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and
temperature. All data sheet typical parameters are measured under the following conditions: T = 25 °C,
CL = 20 pF, VDD = VDDA = 1.8 V, VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.
5.1 Absolute Maximum Ratings
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)
DC power supplies:
Symbol
Min
Max
Unit
VDD
VDDA
VDDIO
–0.3
–0.3
–0.3
-
2.0
3.6
3.6
0.3
V
V
V
V
Iin
-
+/- 10
mA
3.6
V
5.0
V
150
°C
Core supply
PLL supply
I/O supply
|VDDA – VDDIO|
Input pin current, any pin except supplies
Vfilt
-0.3
Vinio
-0.3
Storage temperature
Tstg
–65
EN
D TI
EL A
L
PH D
I RA
Input voltage on PLL_REF_RES
Input voltage on I/O pins
FT
Parameter
Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
5.2 Recommended Operating Conditions
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)
Parameter
DC power supplies:
Core supply
PLL supply
I/O supply
|VDDA – VDDIO|
Ambient operating temperature
Symbol
Min
Typ
Max
Unit
VDD
VDDA
VDDIO
1.71
3.13
3.13
1.8
3.3
3.3
0
1.89
3.46
3.46
V
V
V
V
TA
-
- CQZ
- DQZ
0
- 40
°C
+ 70
+ 85
Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.
5.3 Digital DC Characteristics
(Measurements performed under static conditions.)
High-level input voltage
D
Parameter
FI
Low-level input voltage, except XTI
Low-level input voltage, XTI
Min
Typ
Max
Unit
VIH
2.0
-
-
V
VIL
-
-
0.8
V
VILXTI
-
-
0.6
V
Vhys
N
Input Hysteresis
Symbol
0.4
V
High-level output voltage (IO = -2mA), except XTI
VOH
VDDIO * 0.9
-
-
Low-level output voltage (IO = 2mA), except XTI
V
-
-
VDDIO * 0.1
V
IIN
-
-
5
µA
Input leakage current (all digital pins with internal
pull-up resistors enabled, and XTI)
IIN-PU
-
-
56
µA
C
O
VOL
Input leakage current (all digital pins with internal
pull-up resistors disabled)
12
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
DS734A3
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
5.4 Power Supply Characteristics
(measurements performed under operating conditions)
Min
Typ
Max
Unit
-
203
8
27
469
-
mA
mA
mA
mW
-
100
1
15
350
-
µA
µA
µA
µW
Operational Power Supply Current:
VDD: Core and I/O operating1
VDDA: PLL operating
VDDIO: With most ports operating
Total Operational Power Dissipation:
Standby Power Supply Current:
VDD: Core and I/O not clocked
VDDA: PLL halted
VDDIO: All connected I/O pins 3-stated by other ICs in system
Total Standby Power Dissipation:
FT
Parameter
5.5 Thermal Data (48 LQFP)
Parameter
EN
D TI
EL A
L
PH D
I RA
1.Dependent on application firmware and DSP clock speed.
Symbol
Min
Typ
Max
Unit
Thermal Resistance (Junction to Ambient)
Two-layer Board1
Four-layer Board2
θja
-
63.5
54
-
°C / Watt
Thermal Resistance (Junction to Top of Package)
Two-layer Board1
Four-layer Board2
ψ jt
-
0.70
0.64
-
°C / Watt
Notes: 1. Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper
covering 20 % of the top & bottom layers.
2. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper
covering 20 % of the top & bottom layers and 0.5-oz. copper covering 90 % of the internal power plane
& ground plane layers.
D
3. To calculate the die temperature for a given power dissipation
Τj = Ambient Temperature + [ (Power Dissipation in Watts) * θja ]
FI
4. To calculate the case temperature for a given power dissipation
C
O
N
Τc = Τj - [ (Power Dissipation in Watts) * ψ jt ]
DS734A3
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
13
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
5.6 Switching Characteristics— RESET
Parameter
Symbol
Min
Max
Unit
Trstl
1
-
µs
Trst2z
-
100
ns
Configuration pins setup before RESET# high
Trstsu
50
-
ns
Configuration pins hold after RESET# high
Trsthld
20
-
ns
RESET# minimum pulse width low
All bidirectional pins high-Z after RESET# low
FT
RESET#
EN
D TI
EL A
L
PH D
I RA
HS[3:0]
All Bidirectional
Pins
Trst2z
Trstsu Trsthld
Trstl
C
O
N
FI
D
Figure 1. RESET Timing
14
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
DS734A3
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
5.7 Switching Characteristics — XTI
Parameter
Symbol
Min
Max
Unit
External Crystal operating frequency
Fxtal
10
30
MHz
XTI period
Tclki
33.3
100
ns
XTI high time
Tclkih
13.3
-
ns
XTI low time
Tclkil
13.3
-
ns
CL
10
18
pF
50
Ω
1
External Crystal Load Capacitance (parallel resonant)
External Crystal Equivalent Series Resistance
ESR
XTI
EN
D TI
EL A
L
PH D
I RA
FT
1.CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals which require a
CL outside this range should be avoided. The crystal oscillator circuit design should follow the crystal manufacturer’s recommendation for load capacitor selection.
t clkih
t clkil
Tclki
Figure 2. XTI Timing
5.8 Switching Characteristics — Internal Clock
Parameter
FI
D
Internal DCLK frequency
1
N
O
Min
Max
Fdclk
Fxtal
Fxtal
Fxtal
Fxtal
Fxtal
150
150
150
150
150
6.7
6.7
6.7
6.7
6.7
6.7
1/Fxtal
1/Fxtal
1/Fxtal
1/Fxtal
1/Fxtal
1/Fxtal
CS4852x-CQZ
CS4854x-CQZ
CS4856x-CQZ
CS4852x-DQZ
CS4854x-DQZ
CS4856x-DQZ
Internal DCLK period1
C
Symbol
DCLKP
CS4852x-CQZ
CS4854x-CQZ
CS4856x-CQZ
CS4852x-DQZ
CS4854x-DQZ
CS4856x-DQZ
Unit
MHz
ns
1. After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk
and remains locked until the next power-on reset.
DS734A3
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
15
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode
.
Parameter
Symbol
Min
Max
Units
SCP_CLK frequency
fspisck
-
25
MHz
SCP_CS# falling to SCP_CLK rising
tspicss
24
-
ns
SCP_CLK low time
tspickl
20
-
ns
SCP_CLK high time
tspickh
20
-
ns
Setup time SCP_MOSI input
tspidsu
5
-
ns
Hold time SCP_MOSI input
tspidh
5
-
ns
8
ns
20
ns
1
Typical
tspidov
-
tspiirqh
-
SCP_CS# rising to SCP_IRQ# falling
tspiirql
0
SCP_CLK low to SCP_CS# rising
tspicsh
24
SCP_CS# rising to SCP_MISO output high-Z
tspicsdz
-
20
ns
SCP_CLK rising to SCP_BSY# falling
tspicbsyl
-
3*DCLKP+20
ns
FT
SCP_CLK low to SCP_MISO output valid
SCP_CLK falling to SCP_IRQ# rising
EN
D TI
EL A
L
PH D
I RA
-
ns
ns
1.The specification fspisck indicates the maximum speed of the hardware. The system designer should be
aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of the input data
buffer.
tspicss
SCP_CS#
tspickl
0
SCP_CLK
fspisck
2
A5
D
tspidsu
7
0
A0
R/W
MSB
5
7
6
tspicsh
LSB
tspidov
tspicsdz
MSB
LSB
tspiirqh
N
FI
tspidh
SCP_MISO
6
tspickh
A6
SCP_MOSI
1
tspiirql
O
SCP_IRQ#
C
tspibsyl
SCP_BSY#
Figure 3. Serial Control Port - SPI Slave Mode Timing
16
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
DS734A3
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
5.10 Switching Characteristics — Serial Control Port - SPI Master Mode
Symbol
Min
Max
Units
fspisck
-
25
MHz
tspicss
-
-
ns
SCP_CLK low time
tspickl
SCP_CLK high time
tspickh
20
-
ns
20
-
ns
Setup time SCP_MISO input
tspidsu
9
-
ns
Hold time SCP_MISO input
tspidh
5
-
ns
1
SCP_CLK frequency
SCP_CS# falling to SCP_CLK rising
2
tspidov
-
tspicsl
7
SCP_CLK low to SCP_CS# rising
tspicsh
-
11*DCLKP +
(SCP_CLK PERIOD)/2
8
ns
-
ns
11*DCLKP +
(SCP_CLK PERIOD)/2
-
ns
3*DCLKP
-
ns
20
ns
EN
D TI
EL A
L
PH D
I RA
SCP_CLK low to SCP_MOSI output valid
SCP_CLK low to SCP_CS# falling
Typical
FT
Parameter
Bus free time between active SCP_CS#
tspicsx
SCP_CLK falling to SCP_MOSI output high-Z
tspidz
-
1.The specification fspisck indicates the maximum speed of the hardware. The system designer should be
aware that the actual maximum speed of the communication port may be limited by the firmware application.
2.SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer
to a tested parameter
.
tspicss
EE_CS#
tspickl
0
1
FI
SCP_CLK
D
tspicsl
O
SCP_MISO
N
fspisck
C
SCP_MOSI
A6
2
6
7
0
A0
R/W
MSB
5
6
7
tspicsx
tspicsh
tspickh
A5
LSB
tspidsu
tspidh
tspidov
tspidz
MSB
LSB
Figure 4. Serial Control Port - SPI Master Mode Timing
DS734A3
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
17
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
5.11 Switching Characteristics — Serial Control Port - I2C Slave Mode
Symbol
Min
fiicck
SCP_CLK low time
SCP_CLK high time
tiicckcmd
1.25
START condition to SCP_CLK falling
tiicstscl
1.25
-
µs
SCP_CLK falling to STOP condition
tiicstp
2.5
-
µs
Bus free time between STOP and START conditions
tiicbft
3
-
µs
Setup time SCP_SDA input valid to SCP_CLK rising
tiicsu
100
Hold time SCP_SDA input after SCP_CLK falling
tiich
20
SCP_CLK frequency
Max
Units
-
400
kHz
tiicckl
1.25
-
µs
tiicckh
1.25
-
µs
µs
EN
D TI
EL A
L
PH D
I RA
SCP_SCK rising to SCP_SDA rising or falling for
START or STOP condition
Typical
FT
Parameter
1
ns
-
ns
SCP_CLK low to SCP_SDA out valid
tiicdov
-
18
ns
SCP_CLK falling to SCP_IRQ# rising
tiicirqh
-
3*DCLKP + 40
ns
NAK condition to SCP_IRQ# low
tiicirql
SCP_CLK rising to SCB_BSY# low
tiicbsyl
-
3*DCLKP + 20
ns
3*DCLKP + 20
ns
1.The specification fiicck indicates the maximum speed of the hardware. The system designer should be
aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of the input data
buffer.
tiicckcmd
tiicckl
0
1
SCP_CLK
tiicckh
A6
7
8
0
tiicdov
A0
R/W
1
6
7
ACK
MSB
LSB
tiicckcmd
8
fiicck
tiicstp
tiicbft
ACK
tiicirqh
tiicirql
tiich
N
tiicsu
tiiccbsyl
O
SCP_IRQ#
tiicf
FI
SCP_SDA
6
D
tiicstscl
tiicr
C
SCP_BSY#
18
Figure 5. Serial Control Port - I2C Slave Mode Timing
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
DS734A3
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
5.12 Switching Characteristics — Serial Control Port - I2C Master Mode
Symbol
Min
Max
Units
fiicck
-
400
kHz
SCP_CLK low time
tiicckl
1.25
-
µs
SCP_CLK high time
tiicckh
1.25
-
µs
tiicckcmd
1.25
START condition to SCP_CLK falling
tiicstscl
1.25
-
µs
SCP_CLK falling to STOP condition
tiicstp
2.5
-
µs
Bus free time between STOP and START conditions
tiicbft
3
-
µs
Setup time SCP_SDA input valid to SCP_CLK rising
tiicsu
100
Hold time SCP_SDA input after SCP_CLK falling
tiich
20
tiicdov
-
SCP_CLK frequency
µs
EN
D TI
EL A
L
PH D
I RA
SCP_SCK rising to SCP_SDA rising or falling for START or
STOP condition
FT
Parameter
1
SCP_CLK low to SCP_SDA out valid
ns
-
ns
18
ns
1.The specification fiicck indicates the maximum speed of the hardware. The system designer should be
aware that the actual maximum speed of the communication port may be limited by the firmware application.
tiicckcmd
tiicckl
0
1
SCP_CLK
tiicstscl
6
tiicckh
A6
tiicf
7
8
0
tiicdov
A0
R/W
1
6
7
tiicckcmd
8
fiicck
ACK
MSB
LSB
tiicstp
tiicbft
ACK
FI
D
SCP_SDA
tiicr
tiich
Figure 6. Serial Control Port - I2C Master Mode Timing
C
O
N
tiicsu
DS734A3
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
19
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
5.13 Switching Characteristics — Digital Audio Slave Input Port
Symbol
Min
Max
Unit
Tdaiclkp
40
-
ns
-
45
55
%
Setup time DAI_DATAn
tdaidsu
10
-
ns
Hold time DAI_DATAn
tdaidh
5
-
ns
DAI_SCLK period
DAI_SCLK duty cycle
DAI_SCLK
tdaidh
EN
D TI
EL A
L
PH D
I RA
tdaidsu
FT
Parameter
DAI_DATAn
C
O
N
FI
D
Figure 7. Digital Audio Input (DAI) Port Timing Diagram
20
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
DS734A3
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
5.14 Switching Characteristics — DSD Slave Input Port
Min
40
78
78
1.024
2.048
20
20
-20
Typ
-
Max
60
3.2
6.4
20
FT
Symbol
tsclkl
tsclkh
(64x Oversampled)
(128x Oversampled)
DSD_A / _B valid to DSD_SCLK rising setup time
tsdlrs
DSD_SCLK rising to DSD_A or DSD_B hold time
tsdh
DSD clock to data transition (Phase Modulation mode)
tdpm
Unit
%
ns
ns
MHz
MHz
ns
ns
ns
EN
D TI
EL A
L
PH D
I RA
Parameter
MCLK Duty Cycle
DSD_SCLK Pulse Width Low
DSD_SCLK Pulse Width High
DSD_SCLK Frequency
Figure 8. Direct Stream Digital - Serial Audio Input Timing
t dpm
D
t dpm
FI
DSD_SC LK
(128Fs)
DSD_A, DSD_B
C
O
N
DSD_SC LK
(64Fs)
Figure 9. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode
DS734A3
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
21
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
5.15 Switching Characteristics — Digital Audio Output Port
Parameter
DAO_MCLK period
Symbol
Min
Max
Unit
Tdaomclk
40
-
ns
-
40
60
%
DAO_MCLK duty cycle
1
DAO_SCLK period for Master or Slave mode
Tdaosclk
40
-
ns
-
40
60
%
DAO_SCLK delay from DAO_MCLK rising edge,
DAO_MCLK as an input
tdaomsck
-
19
ns
DAO_LRCLK delay from DAO_SCLK transition, respectively3
tdaomstlr
-
DAO1_DATA[3..0], DAO2_DATA[1..0]
delay from DAO_SCLK transition3
tdaomdv
-
DAO_SCLK duty cycle for Master or Slave mode1
EN
D TI
EL A
L
PH D
I RA
Slave Mode (Output A0 Mode)4
FT
Master Mode (Output A1
Mode)1,2
DAO1_DATA[3..0], DAO2_DATA[1..0]
delay from DAO_SCLK transition3
tdaosdv
8
ns
10
ns
15
ns
1.Master mode timing specifications are characterized, not production tested.
2.Master mode is defined as the CS48500 driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input,
it is divided to produce DAO_SCLK, DAO_LRCLK.
3.This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK
is the point at which the data is valid.
4.Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
Tdaomclk
FI
D
DAO_MCLK
tdaomsck
C
O
N
DAO_SCLK
tdaomdv , tdaosdv
DAOn_DATAn
tdaomstlr
tdaomstlr
DAO_LRCLK
Figure 11. Digital Audio Port Timing, MCLK Master Mode
22
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
DS734A3
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
6. Ordering Information
The CS48500 family part number is described as follows:
CS485NI-XYZ
where
N - Product Number Variant
I - ROM ID Number
X - Product Grade
FT
Y - Package Type
Z - Lead (Pb) Free
Part No.
CS48520-CQZ
CS48540-CQZ
CS48540-DQZ
CS48560-CQZ
CS48560-DQZ
EN
D TI
EL A
L
PH D
I RA
Table 3. Ordering Information
Grade
Temp. Range
Commercial
0 to +70 °C
Commercial
0 to +70 °C
Automotive
-40 to +85 °C
Commercial
0 to +70 °C
Automotive
-40 to +85 °C
Package
48-pin LQFP
NOTE: Please contact the factory for availability of the -D (automotive grade) package.
7. Environmental, Manufacturing, & Handling Information
Table 4. Environmental, Manufacturing, & Handling Information
Model Number
MSL Rating*
Max Floor Life
260 °C
3
7 Days
D
CS48520-CQZ
Peak Reflow Temp
FI
CS48540-CQZ
CS48540-DQZ
N
CS48560-CQZ
O
CS48560-DQZ
C
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
DS734A3
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
23
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
8. Device Pinout Diagrams
GPIO18, DAO_MCLK
25
FT
GPIO4, HS2
26
GNDIO3
30
GPIO3, HS1
GPIO6, DAO2 _DATA0, HS3
31
27
GPIO7, HS4
32
VDD2
GND4
33
28
GPIO9, SCP_MOSI
34
GPIO5, XMTA
GPIO10, SCP__MISO / SDA
35
1
2
3
TEST
RESET#
DBDA
O
C
12
48
VDDIO1
VDDA (3.3V)
11
47
GPIO0
PLL_REF_RES
10
46
GPIO16, DAI1_DATA0
GNDA
9
45
D
XTO
N
44
29
GPIO11, SCP_CLK
48 LQFP
43
XTI
23
DAO_SCLK
GND3
21
DAO_LRCLK
20
DAO1_DATA0, HS0
19
FI
XTAL_OUT
CS48520
GND2
42
8
VDD3
DAI1_SCLK
41
7
GPIO13, SCP_BSY#, EE_CS#
GNDIO1
40
6
GNDIO4
VDDIO2
22
DAI1_LRCLK
39
24
EN
D TI
EL A
L
PH D
I RA
GPOI12, SCP_IRQ#
5
38
DBCK
GPIO8, SCP_CS#
4
37
GND1
VDDIO3
36
8.1 CS48520, 48-pin LQFP Pinout Diagram
GNDIO2
18
GPIO15, DAI2_SCLK
17
GPIO14, DAI2_LRCLK
16
VDD1
15
GPIO17, DAI2_DATA0
14
GPIO2
13
GPIO1
Figure 12. CS48520, 48-Pin LQFP Pinout
24
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
DS734A3
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
GPIO18, DAO_MCLK
GPIO5, XMTA
29
25
GNDIO3
30
GPIO4, DAO1_ DATA2, HS2
GPIO6, DAO2_DATA0, HS3
31
26
GPIO7, HS4
32
GPIO3, DAO1_ DATA1, HS1
GND4
33
27
GPIO9, SCP_MOSI
34
VDD2
GPIO10, SCP__MISO / SDA
35
28
GPIO11, SCP_CLK
FT
DAO_SCLK
10
11
12
GPIO0, DAI1_DATA1
VDDIO1
O
GND3
21
DAO_LRCLK
20
DAO1_DATA0, HS0
GNDIO2
18
GPIO15, DAI2_SCLK
17
GPIO14, DAI2_LRCLK
16
VDD1
15
GPIO17, DAI2_DATA0
14
GPIO2
13
GPIO1, DAI1_DATA2
C
GPIO16, DAI1_DATA0
48
9
VDDA (3.3V)
D
47
3
PLL_REF_RES
DBDA
46
2
GNDA
FI
45
RESET#
XTO
1
44
N
XTI
23
19
48 LQFP
43
TEST
XTAL_OUT
CS48540
GND2
42
8
VDD3
DAI1_SCLK
41
7
GPIO13, SCP_BSY#, EE_CS#
GNDIO1
40
6
GNDIO4
VDDIO2
22
DAI1_LRCLK
39
24
EN
D TI
EL A
L
PH D
I RA
GPOI12, SCP_IRQ#
5
38
DBCK
GPIO8, SCP_CS#
4
37
GND1
VDDIO3
36
8.2 CS48540, 48-pin LQFP Pinout Diagram
Figure 13. CS48540, 48-Pin LQFP Pinout
DS734A3
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
25
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
GPIO18, DAO_MCLK
25
FT
GPIO4, DAO1_ DATA2, HS2
GNDIO3
30
26
GPIO6, DAO2 _DATA0, HS3
31
GPIO3, DAO1_ DATA1, HS1
GPIO7, DAO2_D ATA1, HS4
32
VDD2
GND4
33
28
GPIO9, SCP_MOSI
34
GPIO5, DAO1_DATA3, X MTA
GPIO10, SCP__MISO / SDA
35
29
GPIO11, SCP_CLK
27
10
11
12
GPIO0, DAI1_DATA1, TM1, DSD1
VDDIO1
O
C
GPIO16, DAI1_DATA0, TM0, DSD0
48
9
VDDA (3.3V)
D
47
3
PLL_REF_RES
DBDA
46
FI
GNDA
2
45
RESET#
XTO
1
44
N
XTI
DAO_SCLK
GND3
21
DAO_LRCLK
20
DAO1_DATA0, HS0
19
48 LQFP
43
TEST
XTAL_OUT
CS48560
GND2
42
8
VDD3
DAI1_SCLK, DSD-CLK
41
7
GPIO13, SCP_BSY#, EE_CS#
GNDIO1
40
6
GNDIO4
22
DAI1_LRCLK, DAI1_DATA4, DSD5
39
VDDIO2
EN
D TI
EL A
L
PH D
I RA
GPOI12, SCP_IRQ#
23
5
38
DBCK
GPIO8, SCP_CS#
24
4
37
GND1
VDDIO3
36
8.3 CS48560,48-pin LQFP Pinout Diagram
GNDIO2
18
GPIO15, DAI2_SCLK
17
GPIO14, DAI2_LRCLK
16
VDD1
15
GPIO17, DAI2_DATA0, DSD4
14
GPIO2, DAI1_DATA3, TM3, DSD3
13
GPIO1, DAI1_DATA2, TM2, DSD2
Figure 14. CS48560, 48-Pin LQFP Pinout
26
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
DS734A3
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
9. Package Mechanical Drawings
9.1 48-pin LQFP Package Drawing
D
Number of Leads
48
MIN
NOM
MAX
1.60
0.05
0.15
1.35
1.40
1.45
0.17
0.22
0.27
9.00 BSC
7.00 BSC
0.50 BSC
9.00 BSC
7.00 BSC
0
7
0.45
0.60
0.75
1.00 REF
C
O
N
FI
A
A1
A2
b
D
D1
e
E
E1
theta
L
L1
EN
D TI
EL A
L
PH D
I RA
FT
48 LD LQFP (7 x 7 x 1.4 mm body)
NOTES:
1) Reference document: JEDEC MS-026
2) All dimensions are in millimeters and controlling dimension is in millimeters.
3) D1 and E1 do not include mold flash which is 0.25 mm max. per side.A1
4) Dimension b does not include a total allowable dambar protrusion of 0.08 mm max.
Figure 15. 48-Pin LQFP Package Drawing
DS734A3
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
27
CS48500 Data Sheet
32-bit Audio Decoder DSP Family
10. Revision History
Revision
Date
Changes
A1
JUL 2006
Advance release.
A2
JUL 2006
Updated pinout definition for pins 26 and 27. Updated typical power numbers.
A3
DEC 5 2006
C
O
N
FI
D
EN
D TI
EL A
L
PH D
I RA
FT
Updated sections 2.0, 4.2.1, 5.8, Table 3, Table 4, to show new device numbering scheme. Updated sections 8.1, 8.2, 8.3.
28
©Copyright 2006 Cirrus Logic, Inc.
CONFIDENTIAL
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