CMEDIA CMI8788

OxygenTMHD CMI8788
High Performance
PCI Audio Processor
Data Sheet v0.6
2005/09/12
C-Media High Performance PCI Audi o Controller
OxygenTM HD CMI8788 Datasheet v0 .6
NOTICES
THIS DOCUMENT IS PROVIDED “AS IS” WITH NO WARRANTIES
WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY,
NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY
WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, DOCUMENT
OR SAMPLE.
ALL RIGHTS RESERVED. NO PART OF THIS DOCUMENT MAY BE
REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS,
ELECTRONIC OR MECHANICAL, INCLUDING INFORMATION STORAGE
AND RETRIEVAL SYSTEMS, WITHOUT PERMISSION IN WRITING FROM
THE C-MEDIA ELECTRONICS, INC.
Third-party brands and names are the property of their respective owners.
Dolby® logo is the trademark of Dolby Lab.
DTS® logo is the trademark of DTS Lab.
Copyright 2004-2005 © C-Media Electronics Inc.
C-Media Electronics, Inc.
6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan 106, R.O.C.
TEL: 886-2-8773-1100
FAX: 886-2-8773-2211
http://www.cmedia.com.tw
For detailed product information, please contact [email protected]
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C-MEDIA CONFIDENTIAL
C-Media High Performance PCI Audi o Controller
OxygenTM HD CMI8788 Datasheet v0 .6
Contents
0.
1.
Revision History......................................................................................... 4
Features and software description ...................................................... 5
1.1
1.2
1.3
1.4
2.
3.
Block Diagram............................................................................................ 9
Pin Assignment ........................................................................................... 10
3.1
3.2
4.
Pinout Diagram .................................................................................. 10
Pin Descriptio n................................................................................... 11
Electrical Characteristics ....................................................................... 16
4.1
4.2
4.3
4.4
4.5
5.
Hardware Features ............................................................................. 5
Software Features............................................................................... 6
General Description ........................................................................... 7
Application......................................................................................... 8
Maximum Ratings.............................................................................. 16
Recommended Operation Conditions ................................................ 16
Power consumption............................................................................ 16
DC Characteristics ............................................................................. 17
EEPROM AC Timing Characteristics................................................ 17
4.5.1 I2 S SIGNAL TIMING.................................................................. 17
4.5.2 CONTROL INTERFACE TIMING - 3 - WIRE MODE............. 17
4.5.3 CONTROL INTERFACE TIMING - 2 - WIRE MODE............. 20
4.5.4 EEPROM INTERFACE TIMING ............................................... 21
4.5.5 EEPROM AC Timing Characteristics ......................................... 22
4.5.6 AC-LINK TIMING CHARACTERISTICS ................................ 23
Mechanical Specifications ...................................................................... 27
5.1
Package Dimension............................................................................ 27
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C-Media High Performance PCI Audi o Controller
OxygenTM HD CMI8788 Datasheet v0 .6
List of Figures
Figure 1. Block Diagram of OxygenT MHD CMI8788 ...................................................... 9
Figure 2. Pinout Diagram of OxygenT MHD CMI8788 ................................................... 10
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OxygenTM HD CMI8788 Datasheet v0 .6
0. Revision History
Date
Rev.
Release Note
2005/03/15
0.1
Preliminary vision
2005/04/18
0.2
Modify S/W features
2005/07/22
0.5
Edit for readability
2005/9/12
0.6
Modify S/W features
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OxygenTM HD CMI8788 Datasheet v0 .6
1. Features and General Description
1.1 Hardware Features
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PCI 2.2 interface with bus mastering and burst modes
Only one 24.576MHz oscillator is needed
4 synchronous I2 S output data stream pairs within 1 flexible output DMA
Programmable channel routing mechanism among the 4 I2 S output pairs
4 synchronous I2 S input data stream pairs spread in 3 input DMA’s (for Dolby
pro-audio applications)
Optionally, a multi-channel AC- link can support 2 AC97 codecs
Programmable HW monitoring routing from I2 S inputs to outputs
All I2 S I/O pairs support 32-bit PCM data transfer and adjustable sample rate (up to
192KHz)
Integrated 192k/24-bit S/PDIF transmitter with 1 dedicated S/PDIF OUT DMA
Integrated 192k/24-bit S/PDIF receiver in recording DMA
S/PDIF IN supports digital loopback path for switching between optical and RCA
connections
48k/16-bit front panel DMA for AC97 codec
2-wire master serial bus or 4-wire SPI (Serial Peripheral Interface) bus to control
I2 S codecs
2-wire slave serial bus to communicate with microcontroller unit (MCU)
Interrupt pin to inform external MCU to retrieve the data from the system driver
One MPU-401 MIDI UART port
EEPROM control interface
6 GPI phone jack detection pins
Advanced device-sensing technology indicates whether a speaker or a headphone
is plugged in the jack
9 direct-access GPIO pins
3 bonding-option bits for 8 identification possibilites
128-pin LQFP thin high-quality package
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OxygenTM HD CMI8788 Datasheet v0 .6
1.2 Software Features
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DTS® Interactive – a real-time 5.1 channel encoder that takes 2 or more channels
and encodes them into a DTS bit stream.
DTS® NeoPC - an up- mix matrix that turns any 2 channel aud io into 7.1 channel
surround sound
Dolby® Digital Live (AC-3) real-time 5.1 channel encoding bit-stream to facilitate
the connection with CE AV receiver
Dolby® Pro-Logic IIx surround processor, spreading stereo audio into 7.1 channel
surround sound
Renowned Dolby® Headphone technology, conveying 5.1 surround and 3D gaming
audio over stereo headphones
The latest Dolby® Virtual Speaker solution, creating amazing virtual surround
sound from a generic two-speaker configuration
C-Media FlexBassTM – configurable LFE channel crossover frequency (from 50 to
250Hz)
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C-Media Magic VoiceT M, a popular feature for disguising voice in online chatting
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C-Media Xear 3D™ 7.1 Virtual Speaker Shifter technology
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C-Media’s unique Karaoke functions: Microphone Echo, Key-shifting
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Individual 10-band EQ for each channel
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27 global reverberation environments
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Play3D demo program
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Supports most industrial standards of 3D sound for PC gaming, including EAX™
1.0&2.0, A3D™ 1.0, and DirectSound™
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Support 7.1 CH digital audio playback for WinXP, 2K, ME, 98SE (Microsoft®
DirectX V.9.0 and above is required)
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Linux driver available (without Dolby® and DTS ® technologies)
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OxygenTM HD CMI8788 Datasheet v0 .6
1.3 General Description
The CMI8788 is a high quality PCI 32-bit multi-channel audio processor that can be
built into home audio electronics or personal computers to provide high fidelity sound
playback and processing. It supports up to 12 output channels and 8 input channels. The
12 output channels are composed of 3 playback DMA’s, which are multi-channel DMA
(32 bits, 8 channels, 192k), S/PDIF DMA (32 bits, 2 channels, 192k), and front panel
DMA (16 bits, 2 channels, 48k). The 8 input channels are spread across 3 recording
DMA’s (32 bits, 192k) - recording A, B, and C DMA’s. The architecture of recording is
a unique point of CMI8788 that enables very flexible recording options for the user. The
details of the recording mode selection will be explained in the later sections.
The CMI8788 is compatible with all the popular codecs, from I2 S codecs with over
120dB quality to the usual AC97 codecs. This ability gives customers the flexibility to
design their products exactly the way they want them. The I2 S, AC-Link, 2-wire master
bus, and SPI interfaces are used to transfer audio data and control data between the
CMI8788 and codecs. To facilitate the connection with existing home audio electronics,
the CMI8788 has incorporated the S/PDIF transmitter and receiver with 192k sampling
rate.
An EEPROM interface is built for the CMI8788 in connection with the EEPROM to
store and retrieve the non-evaporable data for customer applications, such as board
configuration, sub- vendor and sub-system IDs of the PCI configuration, or any dynamic
data that customers want to restore at the next power-on.
The CMI8788 has an independent 2-wire slave bus to communicate with the micro
control unit (MCU). This interface is used as a medium for the system driver and the
MCU to exchange data. One of the applications of the 2-wire slave bus is to transmit the
control data from the remote controller to the system driver. The MPU-401 MIDI UART
is also integrated in the CMI8788.
There are six GPI phone jack detect pins in CMI8788, which can be used to distinguish
if a cable is plugged in the phone jack. The re are 9 GPIO pins on the chip, however
some of them are shared with other functions. The C-Media’s unique device sensing
technology is imple mented in CMI8788, which can indicate whether a speaker or a
headphone is plugged in the jack. Then according to this information, the system driver
can decide to turn on the C-Media’s X-ear 3D audio technology if appropriate.
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OxygenTM HD CMI8788 Datasheet v0 .6
1.4 Applications
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Pro-sumer high-quality PCI sound card for retailer market
Consumer sound card powered by Dolby® and DTS ® technologies
PC-based media center
Professional PC musician application
High-end motherboard requiring top audio quality
Audio up-sell for PC systems
Bundle selling with high-profile VGA cards
General purpose multi- channel I/O
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OxygenTM HD CMI8788 Datasheet v0 .6
2. Block Diagram
Figure 1. Block Diagram of OxygenTMHD CMI8788
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OxygenTM HD CMI8788 Datasheet v0 .6
3. Pin Assignment
3.1
Pinout Diagram
Figure 2. Pinout Diagram of OxygenTMHD CMI8788
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OxygenTM HD CMI8788 Datasheet v0 .6
3.2
Pin Descriptions
The following table gives the pin descriptions for the OxygenT MHD CMI8788.
Some of the pins perform multiple functions, so for the sake of consistency, a pin may
be listed more than once in the table. The abbreviations used in the pin description table
are expla ined below.
DI: digital input signal
DO: digital output signal
DIO: digital bidirectional signal
AI: analog input
PU: pull- up with 75KΩ resistor
PD: pull-down with 75KΩ resistor
#:
low active signal
Table 3.1 Pin description table of OxygenTMHD CMI8788
Symbol
Pin No.
Type
PCI Bus Interface
Description
XRST
119
DI
PCI Bus Reset.
XCLK33
120
DI
PCI Bus clock, 33MHz.
XIDSEL
5
DI
PCI Initialization Device Select. This is the chip select during PCI
configuration access.
XGNT#
121
DI
PCI Bus Grant. When active, PCI bus master is granted to
CMI8788.
122
DIO
PCI Bus Master Request. When active, the CMI8788 is requesting
to become a bus master.
XAD[31:0]
1-3, 7-11,
13-15, 25, 27,
28-31, 33,
35-38, 40-44,
123-126, 128
DIO
PCI Address / Data Bus
XCB#[3:0]
4, 16, 24, 34
DIO
PCI Bus Command / Byte Enable
XFRAME#
17
DIO
XDEVSEL#
21
DIO
XIRDY#
18
DIO
XTRDY#
20
DIO
PCI Cycle Frame. It is driven by the current master to indicate the
beginning and duration of an access
PCI Device Select. When active, indicates that the driving device
has decoded its address as the target of the current access.
PCI Initiator Ready. When active, indicates that the initiator can
complete the current data phase of the transaction.
PCI Target Ready. When active, indicates the target device can
complete the current data phase of the transaction.
XREQ#
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XSTOP#
22
DIO
PCI Stop. When active, indicates that the target is requesting that
the master stop the current transaction.
XPAR
23
DIO
PCI Parity. It is even parity across XAD[31:0] and XCB#[3:0].
XINTA#
118
DIO
PCI Interrupt Request A.
MPU-401 MIDI UART Interface
XTXD
54
XRXD
55
DIO, PU MP-401 MIDI transmitter (output). It is also used as XGPIO5~8
and I2S ADC 3 configuration (input, 0: GPIO5~8, 1: I2S ADC 3)
at the rising edge of XRST.
DI, PU MPU401 MIDI receiver.
I2S Interface
XDAC_MCLK
82
DO
I2S DAC master clock output.
XDAC_LRCK
83
DIO
I2S DAC Left/Right sample clock.
XDAC_BCLK
84
DIO
I2S DAC bit clock.
XDAC_SDOUT0
85
DO
I2S DAC channel 0,channel 1 serial data output.
XDAC_SDOUT1
86
DO
I2S DAC channel 2,channel 3 serial data output.
XDAC_SDOUT2
87
DO
I2S DAC channel 4,channel 5 serial data output.
XDAC_SDOUT3
88
DO
I2S DAC channel 6,channel 7 serial data output.
XADC1_MCLK
90
DO
I2S ADC 1 and I2S ADC 4 master clock output.
XADC1_LRCK
91
DIO
I2S ADC 1 Left/Right sample clock.
XADC1_BCLK
92
DIO
I2S ADC 1 bit clock.
XADC1_SDIN
XAC97_SDI1/
93
DI, PU I2S ADC 1 serial data input.
58
DI, PD I2S ADC 1 serial data input 1. This pin is shared with AC97 serial
data input 1, and determined by XSPI_DOUT/XA1 input
configuration at the rising edge of XRST.
XADC1_SDIN1
XADC2_MCLK
94
DO
I2S ADC 2 master clock output.
XADC2_LRCK
95
DIO
I2S ADC 2 Left/Right sample clock.
XADC2_BCLK
96
DIO
I2S ADC 2 bit clock.
XADC2_SDIN
97
XGPIO5/
XADC3_MCLK
98
XGPIO6/
XADC3_BCLK
99
XGPIO7/
XADC3_LRCK
100
XGPIO8/
XADC3_SDIN
101
DI, PU I2S ADC 2 serial data input.
DIO, PD I2S ADC 3 master clock output. This pin is shared with XGPIO5,
which is determined by XTXD input configuration at the rising
edge of XRST.
DIO, PD I2S ADC 3 bit clock. This pin is shared with XGPIO6, which is
determined by XTXD input configuration at the rising edge of
XRST.
DIO, PD I2S ADC 2 Left/Right sample clock. This pin is shared with
XGPIO7, which is determined by XTXD input configuration at
the rising edge of XRST.
DIO, PD GPIO8, default input. This pin is shared with XADC3_SDIN,
which determined by XTXD input configuration at the rising edge
of XRST.
AC-Link Interface
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XAC97_BCLK
63
DI, PU AC97 serial clock input8
XAC97_SDI0
62
DI, PD AC97 serial data input 0
XAC97_SDI1/
XADC1_SDIN1
58
DI, PD AC97 serial data input 1. This pin is shared with XADC1_SDIN1,
and determined by XSPI_DOUT/XA1 input configuration at the
rising edge of XRST.
XAC97_SYNC
61
DO
AC97 frame synchronization.
XAC97_SDO0
64
DO
AC97 serial data output 0.
XAC97_SDO1
59
DO
AC97 serial data output 1.
XAC97_RST0
60
DO
AC97 codec reset 0.
XAC97_RST1
57
DO
AC97 codec reset 1.
XAC97_MCLK
65
DO
AC97 master clock 24.5760M for AC97 codec.
Serial Port Interface
XSPI_DIN/
XMSDA
73
DIO, PU SPI data input. This pin is shared with 2-wire master serial data.
XSPI_CLK/
XMSCL
74
DIO, PU SPI clock output. This pin is shared with 2-wire master serial
clock.
XSPI_DOUT/
XA1
75
XSPI_CEN0/
XA0
77
XSPI_CEN1/
XCID0
78
XSPI_CEN2/
XCID1
79
DIO, PU SPI data output. This pin is shared with 2-wire Codec address A1.
It is also used as XAC97_SDI1 and XADC1_SDIN1
configuration at the rising edge of XRST (input, 1: XAC97_SDI1,
0: XADC1_SDIN1).
DIO, PU SPI chip enable, which select the codec #0 to be controlled. It is
shared with I2C Codec address A0. It is also used as XGPIO3~4
and SSCL/SSDA configuration (input, 1: GPIO3~4, 0:
SSCL/SSDA) at the rising edge of XRST.
DIO, PU SPI chip enable, which select the codec #1 to be controlled
(output). It is shared with codec ID 0 configuration (input) at the
rising edge of XRST.
DIO, PU SPI chip enable, which select the codec #2 to be controlled
(output). It is shared with codec ID 1 configuration (input) at the
rising edge of XRST.
XSPI_CEN3/
XCID2
80
XSPI_CEN4/
XEESK
XSPI_CEN5/
XEEDO
68
69
DIO, PU SPI chip enable, which select the codec #3 to be controlled
(output). It is shared with codec ID 2 configuration (input) at the
rising edge of XRST.
SPI chip enable, which select the codec #4 to be controlled. It is
DO
shared with EEPROM serial clock.
SPI chip enable, which select the codec #5 to be controlled. It is
DO
shared with EEPROM serial data out.
2-Wire Master Serial Bus
XMSDA/
XSPI_DIN
XMSCL/
XSPI_CLK
XA1/
XSPI_DOUT
73
DIO, PU 2-wire serial bus data. This pin is shared with SPI data input.
74
DIO, PU 2-wire serial bus clock. This pin is shared with SPI clock output.
75
DIO, PU 2-wire serial bus codec address A1. This pin is shared with SPI
data output. It is also used as XAC97_SDI1 and XADC1_SDIN1
configuration at the rising edge of XRST (input, 1: XAC97_SDI1,
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XA0/
XSPI_CEN0
77
0: XADC1_SDIN1).
DIO, PU 2-wire serial bus codec address A0. This pin is shared with SPI
chip enable, which select the codec #0 to be controlled. It is also
used as XGPIO3~4 and SSCL/SSDA configuration (input, 1:
GPIO3~4, 0: SSCL/SSDA) at the rising edge of XRST.
2-Wire Slave Serial Bus
XSSCL/
XGPIO3
XSSDA/
XGPIO4
XMCU_INT
52
DIO, PU 2-wire serial bus clock. This pin is shared with XGPIO3.
53
DIO, PU 2-wire serial bus data. This pin is shared with XGPIO4.
XSLAVE_RDY/
XGPIO1
50
72
DO
Interrupt output for external Micro Control Unit (MCU).
DIO, PD 2-wire serial bus data ready. This pin is shared with XGPIO1.
S/PDIF Interface
XSPDIFI
107
DI
S/PDIF receiver.
XSPDIFO
116
DO
S/PDIF transmitter.
EEPROM Interface
XEECS
67
XEESK/
XSPI_CEN4
68
XEEDI
66
XEEDO/
XSPI_CEN5
69
DIO, PD EEPROM chip enable (output). It is also used as power on
EEPROM CS delay configuration (input, 0: no delay, 1: delay 1
clock) at the rising edge of XRST
EEPROM serial clock. This pin is shared with SPI chip enable,
DO
which select the codec #4 to be controlled
DI, PU EEPROM serial data in
DO
EEPROM serial data out. This pin is shared with SPI chip enable,
which select the codec #5 to be controlled
Jack Detect GPI Interface
XGPI0
108
DI, PD JACK A detection input
XGPI1
109
DI, PD JACK B detection input
XGPI2
110
DI, PD JACK C detection input
XGPI3
111
DI, PD JACK D detection input
XGPI4
112
DI, PD JACK E detection input
XGPI5
113
DI, PD JACK F detection input
GPIO Interface
XGPIO0
49
DIO, PD GPIO0, default output Low.
XGPIO1/
XSLAVE_RDY
50
DIO, PD GPIO1, default output Low. This pin is shared with I2C Slave data
ready.
XGPIO2
51
DIO, PD GPIO2, default input.
XGPIO3/XSSCL
52
DIO, PU GPIO3, default output Low. This pin is shared with I2C Slave
serial clock.
XGPIO4/XSSDA
53
DIO, PU GPIO4, default input. This pin is shared with I2C Slave serial data
XGPIO5/
XADC3_MCLK
98
DIO, PD GPIO5, default output Low. This pin is shared with
XADC3_MCLK, which determined by XTXD input configuration
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XGPIO6/
XADC3_BCLK
99
XGPIO7/
XADC3_LRCK
100
XGPIO8/
XADC3_SDIN
101
at the rising edge of XRST.
DIO, PD GPIO6, default input. This pin is shared with XADC3_BCLK,
which determined by XTXD input configuration at the rising edge
of XRST.
DIO, PD GPIO7, default output Low. This pin is shared with
XADC3_LRCK, which determined by XTXD input configuration
at the rising edge of XRST.
DIO, PD GPIO8, default input. This pin is shared with XADC3_SDIN,
which determined by XTXD input configuration at the rising edge
of XRST.
Headphone Sensing Interface
XHPD_E/
DIO, PD Head phone detect enable. This pin is shared with test mode
selection at the rising edge of XRST
103
XTEST
XHPD_IN
104
AI
Head phone voltage input
XHPD_R1
105
AI
Head phone reference resistor 1
XHPD_R2
106
AI
Head phone reference resistor 2
Miscellaneous
XTAL1
46
DI
24.576Mhz OSC input
XTAL2
47
DO
OSC output
XRSTO
71
DO
External Codec reset, can be programmed as Active Low or High
with Register 0x50-bit 2
XPWDN
115
DO
Power Down output pin, Active Low, default High
DVDD
6, 19, 32, 45,
56, 76, 89,
117
3.3V power input
DGND
12, 26, 39, 48,
70, 81, 102,
114
Ground
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4. Electrical Characteristics
4.1 Maximum Ratings
Test Conditions
DVDD = 3.3V, DGND =0V,TA=+25o C
Parameter
Symbol
Min
Typ
Max
-
-55
-
150
o
o
Storge temperature
Units
C
Operating ambient temperature
-
0
25
75
C
DC supply voltage
-
3.0
3.3
3.6
V
I/O pin voltage
-
GND
-
VDD
V
Power dissipation
-
-
0.15
-
W
4.2 Recommended Operation Conditions
Test Conditions
DVDD = 3.3V, DGND =0V,TA=+25o C
Parameter
Symbol
Min
Typ
Max
Units
Input voltage range
-
VDD-0.3
VDD
VDD+0.3
V
Output voltage range
-
0
-
VDD
V
4.3 Power consumption
Test Conditions
DVDD = 3.3V, DGND =0V,TA=+25o C
Parameter
Symbol
Min
Typ
Max
Units
Supply current : power up
-
-
40
-
mA
Supply current : power down
-
-
10
-
uA
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4.4 DC Characteristics
Test Conditions
DVDD = 3.3V, DGND =0V,TA=+25o C
Parameter
Symbol
Min
Typ
Max
Units
Input voltage range
Vin
VDD-0.3
VDD
VDD+0.3
V
Output voltage range
Vout
0
-
VDD
V
High level input voltage
Vih
0.7VDD
-
-
V
Low level input voltage
Vil
-
-
0.3VDD
V
High level output voitage
Voh
2.4
-
-
V
Low level output voltage
Vol
-
0.4
V
Input leakage current
Iil
-10
-
10
uA
Output leakage current
Iol
-10
-
10
uA
Output buffer driver current
-
-
8
-
mA
SPDIF transmit output driver current
-
-
8
-
mA
4.5 AC Timing Characteristics
4.5.1 I2S SIGNAL TIMING
1. SYSTEM CLOCK TIMING
System Clock Timing Diagram
Test Conditions
DVDD = 3.3V, DGND =0V,TA=+25o C,fs=96KHz,MCLK=512fs,24 bit data,unless otherwise stated
System Clock Timing Parameters
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Parameter
Symbol
Min
Typ
Max
Units
MCLK clock cycle time
tmclk
20
-
-
ns
MCLK pulse width high
tmclkh
10
-
-
ns
MCLK pulse width high
tmclkl
10
-
-
ns
40
50
60
%
MCLK duty cycle
2. AUDIO INTERFACE TIMING
Audio Interface Timing Diagram
Test Conditions
DVDD = 3.3V, DGND =0V,TA=+25o C,fs=96KHz,MCLK=512fs,24 bit data,unless otherwise stated
Audio Interface Timing Parameters
Parameter
LRCK propagation delay from BCLK falling
Symbol
Min
Typ
Max
Units
Tdl
5
-
-
ns
Tdd
5
-
-
ns
edge
SDOUT propagation delay from BCLK falling
edge
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C-MEDIA CONFIDENTIAL
C-Media High Performance PCI Audi o Controller
OxygenTM HD CMI8788 Datasheet v0 .6
4.5.2 CONTROL INTERFACE TIMING - 3 - WIRE MODE
Control Interface Timing -3- Wire Diagram
Note: latch data at XSPI_CEN clock low mode , XSPI_CEN clock can be low or high mode
Test Conditions
DVDD = 3.3V, DGND =0V,TA=+25o C,SPI clock 160 ns,unless otherwise stated
Control Interface Timing -3- Wire Parameters
Parameter
Symbol
Min
Typ
Max
Units
Tscs
120
-
-
ns
XSPI_CLK pulse cycle time
Tscy
160
-
-
ns
XSPI_CLK pulse width low
Tscl
80
-
-
ns
XSPI_CLK pulse width high
Tsch
80
-
-
ns
XSPI_DOUT to XSPI_CLK set-up time
Tdsu
40
-
-
ns
XSPI_DOUT to XSPI_CLK hold time
Tdho
40
-
-
ns
XSPI_CEN rising to SCLK rising
Tcss
40
-
-
ns
XSPI_CLK rising edge to XSPI_CEN rising
edge
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C-MEDIA CONFIDENTIAL
C-Media High Performance PCI Audi o Controller
OxygenTM HD CMI8788 Datasheet v0 .6
4.5.3 CONTROL INTERFACE TIMING - 2 - WIRE MODE
Control Interface Timing -2- Wire Diagram
Test Conditions
DVDD = 3.3V, DGND =0V,TA=+25o C,2 wire,Fast speed mode,unless otherwise stated
Control Interface Timing -2- Wire Parameters
Parameter
Symbol
XMSCL frequency
Min
Typ
Max
Units
400
-
-
KHz
XMSCL pulse width low
t1
650
-
-
ns
XMSCL pulse width high
t2
1.3
-
-
us
Hold time (start condition)
t3
650
-
-
ns
Set-up time (start condition)
t4
650
-
-
ns
Data set-up time
t5
650
-
-
ns
XMSDI,XMSCL rise time
t6
100
-
-
ns
XMSDI,XMSCL fall time
t7
100
-
-
ns
Set-up time (stop condition)
t8
650
-
-
ns
Data hold time
t9
650
-
-
ns
Note: test parameters at 2 wire,Fast speed mode
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C-MEDIA CONFIDENTIAL
C-Media High Performance PCI Audi o Controller
OxygenTM HD CMI8788 Datasheet v0 .6
4.5.4 EEPROM INTERFACE TIMING
EEPROM Interface Timing Diagram
Test Conditions
DVDD = 3.3V, DGND =0V,TA=+25o C,unless otherwise stated
EEPROM Interface Timing Parameters
Parameter
Symbol
Min
Typ
Max
Units
XEESK clock frequency
tsk
555
-
-
KHz
XEESK high time
tskh
900
-
-
ns
XEESK low time
tskl
900
-
-
ns
XEECS setup time
tcss
900
-
-
ns
XEEDI setup time
tdis
900
-
-
ns
XEECS hold time
tcsh
900
-
-
ns
XEEDI hold time
tdih
2
-
-
ns
Output delay to “1”
tpd1
900
-
-
ns
Output delay to “0”
tpd0
30
-
-
ns
XEECS to status valid
tsv
30
-
-
ns
XEECS to XEEDO in high impedance
tdf
30
-
-
ns
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C-MEDIA CONFIDENTIAL
C-Media High Performance PCI Audi o Controller
OxygenTM HD CMI8788 Datasheet v0 .6
4.5.5 EEPROM AC Timing Characteristics
Symbol
fsk
tskh
tskl
tcss
tcsh
tdis
tdih
tpd0
tpd1
tsv
tdf
Description
SK Clock Frequency
SK High Time
SK Low Time
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to “0”
Output Delay to “1”
CS to Status Valid
CS to DO High Impedance
Min
0
500
500
100
0
200
200
Max
0.5
500
500
500
200
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C-MEDIA CONFIDENTIAL
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C-Media High Performance PCI Audi o Controller
OxygenTM HD CMI8788 Datasheet v0 .6
4.5.6 AC-LINK TIMING CHARACTERISTICS
Test Conditions
DVDD = 3.3V, DGND =0V,TA=+25o C ,unless otherwise stated
1. COLD RESET
Cold Reset Timing Diagram
Cold Reset Timing Parameters
Parameter
XAC97_RST active low pulse width
XAC97_RST inactive to XAC97_BCLK startup
Symbol
Min
Typ
Max
Units
Trst_low
1.7
-
-
us
Trst2clk
168
-
-
ns
delay
# denotes active low.
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C-MEDIA CONFIDENTIAL
C-Media High Performance PCI Audi o Controller
OxygenTM HD CMI8788 Datasheet v0 .6
2. WARM RESET
Warm Reset Diagram
Warm Reset Parameters
Parameter
XAC97_SYNC active high pulse width
XAC97_SYNC inactive to XAC97_BCLK startup
Symbol
Min
Typ
Max
Units
Tsync_high
1.2
-
-
us
Tsync2clk
168
-
-
ns
delay
3. AC-LINK CLOCKS
BIT_CLK to SYNC Timing Diagram
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C-MEDIA CONFIDENTIAL
C-Media High Performance PCI Audi o Controller
OxygenTM HD CMI8788 Datasheet v0 .6
BIT_CLK to SYNC Timing Parameters
Parameter
Symbol
XAC97_BCLK frequency
XAC97_BCLK period
Tclk_period
Min
Typ
Max
Units
12.288
-
-
MHz
81.4
-
-
ns
750
-
-
ps
XAC97_BCLK output jitter
XAC97_BCLK high pulsewidth (note 1)
Tclk_high
40.7
-
-
ns
XAC97_BCLK low pulse width (note 1)
Tclk_low
40.7
-
-
ns
48.0
-
-
kHz
Tsync_period
20.8
-
-
us
XAC97_SYNC high pulse width
Tsync_high
1.3
-
-
us
XAC97_SYNC low_pulse width
Tsync_low
19.5
-
-
us
XAC97_SYNC frequency
XAC97_SYNC period
Note: Worst case duty cycle restricted to 45/55.
4. DATA SETUP AND HOLD
Data Setup and Hold diagram
Data Setup and Hold Parameters
Parameter
Setup to falling edge of
Hold from falling edge of
XAC97_BCLK
XAC97_BCLK
Symbol
Min
Typ
Max
Units
Tsetup
30
-
-
ns
Thold
30
-
-
ns
Note: Setup and hold time parameters for SDATA_IN are with respect to the AC ‘97 Controller.
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C-MEDIA CONFIDENTIAL
C-Media High Performance PCI Audi o Controller
OxygenTM HD CMI8788 Datasheet v0 .6
5. SIGNAL RISING AND FALLING TIMES
Signal Rising and Falling Times Diagram
Signal Rising and Falling time Parameters
Parameter
Symbol
Min
Typ
Max
Units
XAC97_BCLK rising time
Triseclk
6
-
-
ns
XAC97_BCLK falling time
Tfallclk
6
-
-
ns
XAC97_SYNC rising time
Trisesync
6
-
-
ns
XAC97_SYNC falling time
Tfallsync
6
-
-
ns
XAC97_SDI rising time
Trisedin
6
-
-
ns
XAC97_SDI falling time
Tfalldin
6
-
-
ns
XAC97_SDO rising time
Trisedout
6
-
-
ns
XAC97_SDO falling time
Tfalldout
6
-
-
ns
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C-MEDIA CONFIDENTIAL
C-Media High Performance PCI Audi o Controller
OxygenTM HD CMI8788 Datasheet v0 .6
5. Mechanical Specification
5.1 Package Dimension
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C-MEDIA CONFIDENTIAL
C-Media High Performance PCI Audi o Controller
OxygenTM HD CMI8788 Datasheet v0 .6
- End of Datasheet -
C-Media Electronics, Inc.
6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan 106, R.O.C.
TEL: 886-2-8773-1100
FAX: 886-2-8773-2211
http://www.cmedia.com.tw
For detailed product information, please contact [email protected]
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C-MEDIA CONFIDENTIAL