CONEXANT BT864AKRF

Bt864A/Bt865A
YCrCb to NTSC/PAL Digital Video Encoder
Data Sheet
100138C
February 2003
Ordering Information
Model Number
Description
Package
Bt864AKRF
YCrCb to NTSC/PAL Digital Video Encoder without Macrovision
52-Pin MQFP
Bt865AKRF
YCrCb to NTSC/PAL Digital Video Encoder with Macrovision
52-Pin MQFP
Revision History
Revision
Date
Description
A
08/26/97
Initial release (document L865A)
B
09/26/00
Company name change
C
02/17/03
Incorporates two Erratas: 102084A and d864er3 (100184B)
© 2003, Conexant Systems, Inc.
All Rights Reserved.
Information in this document is provided in connection with Conexant Systems, Inc. (“Conexant”) products. These materials are provided by
Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no responsibility for errors or
omissions in these materials. Conexant may make changes to specifications and product descriptions at any time, without notice. Conexant
makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to its specifications and product descriptions.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Conexant’s Terms and Conditions of Sale for such products, Conexant assumes no liability whatsoever.
THESE MATERIALS ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE
AND/OR USE OF CONEXANT PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR
OTHER INTELLECTUAL PROPERTY RIGHT. CONEXANT FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF
THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. CONEXANT SHALL NOT BE LIABLE
FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES
OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS.
Conexant products are not intended for use in medical, lifesaving or life sustaining applications. Conexant customers using or selling Conexant
products for use in such applications do so at their own risk and agree to fully indemnify Conexant for any damages resulting from such
improper use or sale.
The following are trademarks of Conexant Systems, Inc.: Conexant and the Conexant C symbol. Product names or services listed in this
publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their
respective owners.
For additional disclaimer information, please consult Conexant’s Legal Information posted at www.conexant.com which is incorporated by
reference.
Reader Response: Conexant strives to produce quality documentation and welcomes your feedback. Please send comments and suggestions
to [email protected] For technical questions, contact your local Conexant sales office or field applications engineer.
ii
Conexant
100138C
02/17/03
Bt864A/Bt865A
YCrCb to NTSC/PAL Digital Video Encoder
Data Sheet
The Bt864A/Bt865A is specifically designed for video systems requiring the
generation of composite, Y/C (S-video) or RGB (SCART) video signals from an 8- or
16-bit YCrCb digital video stream. Worldwide video standards are supported including
NTSC-M (N. America, Taiwan, Japan), PAL-B,D,G,H,I (Europe, Asia), PAL–M (Brazil),
PAL-N (Uruguay, Paraguay) and PAL–Nc (Argentina). The Bt864A and Bt865A are
functionally identical, with the exception that Bt865A can output the Macrovision level
7 anticopy algorithm.
Horizontal sync (HSYNC*) and vertical sync (VSYNC*) may be configured as inputs
(slave mode) or outputs (master mode). BLANK* is an input and may be externally
controlled. Horizontal and vertical blanking are automatically generated. The rise and
fall times of sync, the burst envelope, and closed caption data are internally
controlled.
Distinguishing Features
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
Analog luminance (Y) and chrominance (C) information is available on the Y and C
outputs for interfacing to S-video equipment. The composite analog video signal is
output simultaneously onto two outputs. This allows one output to provide baseband
composite video while the other drives an RF modulator. Analog RGB is also available
to allow for support of the European SCART/PeriTV interface.
‹
‹
‹
‹
‹
Functional Block Diagram
‹
TTXDAT TTXREQ SDA
SCL
VBIAS VREF
8- or 16-bit 4:2:2 YCrCb inputs
NTSC-M/PAL/PAL–M/PAL–N/PAL–Nc
composite video outputs
S-Video/RGB (SCART) outputs
CCIR 601 or square pixel operation
2x oversampling
10-bit DACs
Master or slave video timing
Auto mode detection function
(slave mode)
Interlaced/noninterlaced operation
Macrovision 7 support (Bt865A only)
Closed caption encoding
Teletext encoding (WST system B)
I2C Interface
On-board voltage reference
Power-down modes
Programmable luma delay (singlechannel)
5 V or 3.3 V supply voltage
Copy Generation Management System
(CGMS)
FSADJUST
Related Products
‹
COMP
Internal
VREF
CLK
‹
‹
‹
Bt852
Bt856/7
Bt864/5
Bt866/7
10
DAC
P[7:0]
Y[7:0]
RESET*
HSYNC*
CVBS/B
10
2x
Upsampling
Latch
VSYNC*
BLANK*
1.3 MHz
LPF
Mod.
and
Mixer
Color
Space
Convert 10
DAC
CVBS/G
Applications
‹
‹
‹
DAC
Y/CVBS ‹
DAC
C/R
‹
10
‹
FIELD
‹
SLAVE
‹
VDD3V
100138C
02/17/03
ALTADDR
SLEEP
Digital cable systems
Satellite television setup boxes (DBS/DSS)
DVD players
Digital VCR (DVC, DVHS)
VideoCD players
Portable VideoCD players
Digital cameras
PC add-on cards
RGBOUT
Conexant
iii
iv
Conexant
100138C
02/17/03
Contents
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
1
Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
100138C
02/17/03
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Clock TIming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Pixel Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3.1 8-bit YCrCb Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3.2 16-bit YCrCb Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3.3 Pixel Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
HSYNC* Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.5.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.5.2 Sync and Burst Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.5.3 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1.5.4 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1.5.5 FIELD Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
1.5.6 Pixel Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
1.5.7 Burst Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
1.5.8 Digital Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
1.5.9 Chrominance Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
1.5.10 Subcarrier Phasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
1.5.11 Vertical Blanking Intervals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
1.5.12 BLANK* Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
1.5.13 Noninterlaced Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
Power Saving Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
Pixel Input Ranges and Colorspace Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
1.7.1 YC Inputs (4:2:2 YCrCb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
1.7.2 DAC Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23
Closed Captioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
Conexant
v
Bt864A/Bt865A Data Sheet
1.9
1.10
1.11
1.12
1.13
1.14
1.15
2
3.4
3.5
3.6
2-1
2-1
2-1
2-3
Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power and Ground Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 Device Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 Power Supply Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3 COMP Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.4 VREF Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.5 VBIAS Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Analog Signal Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 ESD and Latchup Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2 Clock and Subcarrier Stability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.3 Mutual Inductance Concerns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.4 Reset Precautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.5 Filtering RF Modulator Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.6 Luminance Delay on CVBS/B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 Data Transfer on the I2C Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-1
3-3
3-3
3-3
3-3
3-4
3-4
3-4
3-4
3-5
3-5
3-5
3-5
3-6
3-7
3-7
3-8
3-9
3-9
Parametric Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1
4.2
vi
Essential Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Important Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Writing Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PC Board Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1
3.2
3.3
4
1-25
1-27
1-27
1-27
1-28
1-28
1-29
1-29
1-29
1-29
1-30
1-30
1-30
1-30
1-30
Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
2.2
2.3
2.4
3
Teletext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9.1 CCIR601 Operation (13.5 MHz pixel rate). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9.2 Square Pixel Operation (14.75 MHz pixel rate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9.3 Teletext Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9.4 Teletext Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Copy Generation Management System (CGMS) Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Anticopy Process (Bt865A Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Color Bars. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCART/PeriTV Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.15.1 Luminance or CVBS (Y/CVBS) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.15.2 Chrominance or Red (C/R) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.15.3 Composite Video or Blue (CVBS/B) Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.15.4 Composite Video or Green (CVBS/G) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
AC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Conexant
100138C
02/17/03
Figures
Figure 1-1.
Figure 1-2.
Figure 1-3.
Figure 1-4.
Figure 1-5.
Figure 1-6.
Figure 1-7.
Figure 1-8.
Figure 1-9.
Figure 1-10.
Figure 1-11.
Figure 1-12.
Figure 1-13.
Figure 1-14.
Figure 1-15.
Figure 1-16.
Figure 1-17.
Figure 1-18.
Figure 1-19.
Figure 1-20.
Figure 1-21.
Figure 1-22.
Figure 1-23.
Figure 1-24.
Figure 1-25.
Figure 1-26.
Figure 1-27.
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
Figure 3-5.
Figure 4-1.
Figure 4-2.
100138C
02/17/03
Bt864A/Bt865A Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
HSYNC* Timing in Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Interlaced 525-Line (TSC) Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Interlaced 525-Line (PAL-M) Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Interlaced 625-Line (PAL-B, D, G, H, I, Nc) Video Timing . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Interlaced 625-Line (PAL-B, D, G, H, I, Nc) Video Timing . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Interlaced 625-Line (PAL-N) Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Interlaced 625-Line (PAL-N) Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Noninterlaced 262-Line (NTSC) Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Noninterlaced 262-Line (PAL-M) Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Noninterlaced 312-Line (PAL-B, D, G, H, I, N, Nc) Video Timing . . . . . . . . . . . . . . . . . . . 1-14
Three-Stage Chrominance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Three-Stage Chrominance Filter (Passband) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Luminance 2X Upsampling Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Luminance 2X Upsampling Filter Response (Passband) . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
DAC Sinx/x Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23
DAC Sinx/x Response (Passband) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
Teletext Timing for Tb864A/Bt865A Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
PQ Ratio Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27
Typical CGMS Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28
Y (Luminance) Video Output Waveform SETUPDIS = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31
Y (Luminance) Video Output Waveform SETUPDIS = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32
C (Chrominance) Video Output Waveform SETUPDIS = 0 . . . . . . . . . . . . . . . . . . . . . . . . 1-33
C (Chrominance) Video Output Waveform SETUPDIS = 1 . . . . . . . . . . . . . . . . . . . . . . . . 1-34
CVBS (Composite) Video Output Waveform SETUPDIS = 0 . . . . . . . . . . . . . . . . . . . . . . . 1-35
CVBS (Composite) Video Output Waveform SETUPDIS = 1 . . . . . . . . . . . . . . . . . . . . . . . 1-36
Simplified Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Example Power Plane Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Example of Mutual Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Wiring for the Reset Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
I2C Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
YCrCb Video Input and Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
52-Pin Metric Quad Flatpack (MQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Conexant
vii
Bt864A/Bt865A Data Sheet
viii
Conexant
100138C
02/17/03
Tables
Table 1-1.
Table 1-2.
Table 1-3.
Table 1-4.
Table 1-5.
Table 1-6.
Table 1-7.
Table 1-8.
Table 1-9.
Table 1-10.
Table 1-11.
Table 1-12.
Table 1-13.
Table 1-14.
Table 2-1.
Table 2-2.
Table 3-1.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
100138C
02/17/03
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Field Resolution and Clock Rates for Various Modes of Operation . . . . . . . . . . . . . . . . . . . 1-15
Horizontal Counter Values for Various Video Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
DAC Coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23
Legal Values to TXHS and TXHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
Teletext Clock P and Q Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27
DAC Output Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30
Y (Luminance) Video Output Truth Table SETUPDIS = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31
Y (Luminance) Video Output Truth Table SETUPDIS = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32
C (Chrominance) Video Output Truth Table SETUPDIS = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 1-33
C (Chrominance) Video Output Truth Table SETUPDIS = 1 . . . . . . . . . . . . . . . . . . . . . . . . . 1-34
CVBS (Composite) Video Output Truth Table SETUPDIS = 0 . . . . . . . . . . . . . . . . . . . . . . . 1-35
CVBS (Composite) Video Output Truth Table SETUPDIS = 1 . . . . . . . . . . . . . . . . . . . . . . . 1-36
RGB Output Table (RGBOUT = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37
Read-Back Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Register Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Recommended Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
DC Characteristics (VDD = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
AC Characteristics (VDD = 5 V, VAA = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Conexant
ix
Bt864A/Bt865A Data Sheet
x
Conexant
100138C
02/17/03
1
Circuit Description
1.1
Pin Descriptions
Pin names, input/output assignments, numbers, and descriptions are listed in
Table 1-1. Figure 1-1 illustrates the Bt864A/Bt865A pinout diagram, and Figure 1-2
details the block diagram.
Table 1-1.
Pin Assignments (1 of 2)
Pin Name
I/O
Pin #
Description
CLK
I
43
2x pixel clock input (TTL compatible).
RESET*
I
47
Reset control input (TTL compatible). A logical zero disables and resets video timing
(horizontal, vertical, subcarrier counters to the start of VSYNC of first field) and resets
the I2C interface (but does not reset I2C registers). RESET* must be a logical one for
normal operation.
BLANK*
I
48
Composite blanking control input (TTL compatible). BLANK* is registered on the rising
edge of CLK. The P[7:0] and Y[7:0] inputs are ignored while BLANK* is a logical zero.
VSYNC*
I/O
49
Vertical sync input/output (TTL compatible). As an output (master mode operation),
VSYNC* is output following the rising edge of CLK. As an input (slave mode operation),
VSYNC* is registered on the rising edge of CLK.
HSYNC*
I/O
50
Horizontal sync input/output (TTL compatible). As an output (master mode operation),
HSYNC* is output following the rising edge of CLK. As an input (slave mode operation),
HSYNC* is registered on the rising edge of CLK.
YCrCb pixel inputs (TTL compatible) in 8-bit YCrCb mode. CrCb pixel inputs (TTL
compatible) in 16-bit YCrCb mode. A higher index corresponds to a greater bit significance.
P[7:0]
I
35–28
Y[7:0]
I
25, 24, 21–16 Y pixel inputs (TTL compatible) in 16-bit YCrCb mode. Y[7] enables internal color bars when
operating in 8-bit YCrCb mode. A higher index corresponds to a greater bit significance.(1)
TTXDAT
I
27
Teletext bit stream input (TTL compatible).(1)
TTXREQ
O
38
Teletext request output (TTL compatible).
ALTADDR
I
26
Alternate slave address input (TTL compatible). A logical one configures the device to
respond to an I2C address of 0x88; a logical zero configures the device to respond to an
I2C address of 0x8A.(1)
SLAVE
I
42
Slave/master mode select input (TTL compatible). A logical one configures the device for
slave video timing operation. A logical zero configures the device for master video timing
operation. This pin may be connected directly to VDD or GND.
RGBOUT
I
14
Analog RGB control input (TTL compatible). A logical one configures the device to
output analog RGB (RGBOUT mode) and one composite video output. A logical zero
configures the device to generate S-video along with two composite video outputs. This
pin may be connected directly to VDD or GND. The RGBOUT pin is logically ORed with
the RGBO register bit.
100138C
02/17/03
Conexant
1-1
Circuit Description
Table 1-1.
Bt864A/Bt865A Data Sheet
Pin Assignments (2 of 2)
Pin Name
I/O
Pin #
Description
FIELD
O
15
Field control output (TTL compatible). FIELD transitions after the rising edge of CLK, two
clock cycles following falling VSYNC*. It is a logical zero during FIELD 1 and is a logical
one during FIELD 2.
SLEEP
I
39
Power-down control input (TTL compatible). A logical one configures the device for
power-down mode. A logical zero configures the device for normal operation. This pin
may be connected directly to VDD or GND.
SDA
I/O
40
Serial interface data input/output (TTL compatible). Data is written to and read from the
device via this serial bus.
SCL
I
41
Serial interface clock input (TTL compatible). The maximum clock rate is 100 kHz.
VDD3V
I
44
Input threshold adjustment. When low, indicates nominal supply voltage of 5 volts.
When high, indicates nominal supply voltage of 3.3 volts.
CVBS/B
O
8
Composite video or Blue (with blanking and sync, and optionally, Macrovision encoding).
Optional luma delay channel for composite video output.
6
Analog ground for pin CVBS/B.
10
Composite video or Green (with blanking and sync, and optionally, Macrovision encoding).
7
Analog ground for pin CVBS/G.
12
Modulated chrominance, or Red.
9
Analog ground for pin C/R.
13
Luminance or composite video (with blanking, sync, and optionally, Macrovision
encoding, and/or closed-captioning encoding).
11
Analog ground for pin Y/CVBS.
AGND (CVBS/B)
CVBS/G
O
AGND (CVBS/G)
C/R
O
AGND (C/R)
Y/CVBS
O
AGND (Y/CVBS)
FSADJUST
I
1
Full-scale adjust control pin. A resistor (RSET) connected between this pin and GND
controls the full-scale output current on the analog outputs. For standard operation, use
the nominal RSET values shown under Recommended Operating Conditions.
VBIAS
O
2
DAC bias voltage. A 0.1 µF ceramic capacitor must be used to decouple this pin to GND.
The capacitor must be as close to the device as possible to keep lead lengths to an
absolute minimum.
VREF
O
3
Voltage reference pin. A 0.1 µF ceramic capacitor must be used to decouple this pin to
GND. The capacitor must be as close to the device as possible to keep lead lengths to an
absolute minimum.
COMP
O
5
Compensation pin. A 0.1 µF ceramic capacitor must be used to decouple this pin to VAA.
The capacitor must be as close to the device as possible to keep lead lengths to an
absolute minimum.
VAA
–
4
Analog power. Refer to PC Board Considerations section of this document.
VDD
–
37, 23, 46
Digital power. Refer to the PC Board Considerations section of this document.
AGND
–
51, 52
Analog ground. Refer to the PC Board Considerations section of this document.
GND
–
22, 36, 45
Digital ground. Refer to the PC Board Considerations section of this document.
FOOTNOTE:
(1)
1-2
Any unused inputs should not be left floating.
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
Circuit Description
52
51
50
49
48
47
46
45
44
43
42
41
40
AGND
AGND
HSYNC*
VSYNC*
BLANK*
RESET*
VDD
GND
VDD3V
CLK
SLAVE
SCL
SDA
Figure 1-1. Bt864A/Bt865A Pinout Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
SLEEP
TTXREQ
VDD
GND
P[7]
P[6]
P[5]
P[4]
P[3]
P[2]
P[1]
P[0]
TTXDAT
RGBOUT
FIELD
Y[0]
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
GND
VDD
Y[6]
Y[7]
ALTADDR
14
15
16
17
18
19
20
21
22
23
24
25
26
FS ADJUST
VBIAS
VREF
VAA
COMP
AGND
AGND
CVBS/B
AGND
CVBS/G
AGND
C/R
Y/CVBS
100138_002
100138C
02/17/03
Conexant
1-3
1-4
Conexant
VDD3V
SLEEP
RGBOUT
CLK
Y[7:0]
P[7:0]
ALTADDR
SCL
SDA
8
8
DEMUX,
4:2:2 -> 4:4:4
Upsample
Magnitude
Scaling
I 2C
Interface
U/V 10
Y 10
+
NTSC
Blanking
Pedestal
RESET*
BLANK*
SLAVE
+
1.3 MHz LPF
and 2X
Upsample
10
Sync
Rise/Fall
Expander
Video
Timing
Control
10
BLANK*
10
Color
Space
Convert
Luminance
2X
Upsample
R
B
G
TTXREQ
Teletext/
CGMS
TTXDAT
Modulator
and
Mixer
Closed
Captioning,
Macrovision
FIELD
HSYNC*
VSYNC*
Luma
Delay
VREF
Internal
Voltage
Reference
VBIAS
+
+
10
9
10
9
9
10
10
10
FSADJUST
DAC
DAC
DAC
DAC
C/R
CVBS/B
CVBS/G
Y/CVBS
COMP
Circuit Description
Bt864A/Bt865A Data Sheet
Figure 1-2. Detailed Block Diagram
100138_003
100138C
02/17/03
Bt864A/Bt865A Data Sheet
1.2
Circuit Description
Clock TIming
A clock signal with a frequency twice the pixel sampling rate must be present at the CLK
pin. The device generates an internal pixel CLOCK that in slave mode is synchronized to
the HSYNC* pin. This signal is used to increment the horizontal pixel and vertical line
counters and to register the pixel (P[7:0], Y[7:0], TTXDAT, RESET*, BLANK*, SLAVE,
HSYNC*, and VSYNC*) inputs. All setup and hold timing specifications are measured
with respect to the rising edge of CLK.
1.3
Pixel Input Timing
1.3.1
8-bit YCrCb Input Mode
The 8-bit YCrCb multiplexed input mode is selected by default. Multiplexed Y, Cb, and Cr
data is input through the P[7:0] inputs. By default, the input sequence for active video
pixels must be Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3, etc. in accordance with CCIR656.
1.3.2
16-bit YCrCb Input Mode
The 16-bit mode is selected by setting the YC16 register bit. Y data is input through the
Y[7:0] inputs. Multiplexed Cb and Cr data is input through the P[7:0] inputs.
1.3.3
Pixel Synchronization
The default input pixel sequence is such that the next clock after HSYNC* goes low
will be the start of the 4-byte Cb/Y/Cr/Y sequence in 8-bit mode, or Y/Cb sample pair
in 16-bit mode. This is true for slave mode, and for master mode with the default
HSYNC* timing. This sequence can be changed by the SYNCDLY and CBSWAP bits
in both master and slave modes, or by using the variable HSYNC* timing in master
mode.
The SYNCDLY bit will decrease the delay between the HSYNC* pin and the analog
output by one clock cycle. The pixel-to-analog out timing is unaffected. This makes
the next pixel after the falling edge of HSYNC* the last Y of the Cb/Y/Cr/Y sequence
in 8-bit mode.
The CBSWAP bit will shift the sequence at the input such that the next sample after the
falling edge of HSYNC* will be the Cr sample of the Cb/Y/Cr/Y sequence in 8-bit mode,
or the Y/Cr sample pair in 16-bit mode. The relationship between the HSYNC* pin and
the analog output is unaffected, as is the pixel-to-analog out timing.
100138C
02/17/03
Conexant
1-5
Circuit Description
Bt864A/Bt865A Data Sheet
1.4
HSYNC* Timing
1.4.1
Master Mode
There are two HSYNC* timing modes in master mode; default mode and variable
HSYNC* timing mode. The variable HSYNC* timing mode is enabled by setting
ADJHSYNC high. This mode allows the user to specify the placement of the falling
and rising edges of HSYNC* by using the HSYNCF and HSYNCR registers,
respectively. The values of registers HSYNCF and HSYNCR correspond to the pixel
count of the internal pixel counter (see Figure 1-3). HSYNCF and HSYNCR cannot
be zero and cannot be equal. Values must also be less than or equal to the total
horizontal resolution given in Table 1-2. If the internal pixel counter resets before the
rising edge occurs, the part will not automatically reset, but will wait until the pixel
counter reaches the specified HSYNCR value. The placement of the analog horizontal
sync pulse is fixed relative to the internal pixel counter, therefore when the rising and
falling edges of HSYNC* are moved, the pipeline delay between the HSYNC* pulse
and the analog horizontal sync pulse is altered. In this mode, the pipeline delay from
HSYNC* to analog sync out is 40–(2*HSYNCF) if SYNCDLY = 0, and 41–
(2*HSYNCF) if SYNCDLY = 1. In the default HSYNC* timing mode, the placement
of the edges of the HSYNC* pulse are fixed, with the exception of the one clock delay
available through the register SYNCDLY. In this mode, the pipeline delay from
HSYNC* to analog sync out is 40 clocks if SYNCDLY = 0, and 41 clocks if
SYNCDLY = 1. In the default mode, the delay from internal horizontal pixel counter
reset to the falling edge of HSYNC* is 2 clocks.
1-6
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
Circuit Description
Figure 1-3. HSYNC* Timing in Master Mode
Reset
(4) 1
Internal Pixel
Clock/Counter
2
(4) 1
3 ...
Pixel Count
Internal
Horizontal Reset
2
3 ...
Pixel Count
Default
Default
(3)
HSYNC*
(2)
(1)
(1)
Horizontal Sync
Pipeline Delay
Analog Output
Video Waveform
(2)
Active
Video
Color
Burst
GENERAL NOTE: Waveforms not to scale.
FOOTNOTE:
(1) One clock delay (1/2 pixel) of HSYNC* FALLING EDGE, using register SYNCDLY.
(2) Falling edge of HSYNC* is definable in variable HSYNC* timing mode, using the register HSYNCF.
(3) Rising edge of HSYNC* is definable in variable HSYNC* timing mode, using the register HSYNCR.
(4) Maximum horizontal resolution (see Table 1-2).
100138_004
1.4.2
Slave Mode
Slave mode does not support a variable HSYNC* timing mode. The default pipeline
delay from the HSYNC* falling edge to analog sync out falling edge is 47 clocks if
SYNCDLY = 0, and 46 clocks if SYNCDLY = 1. The default delay from the falling
edge of HSYNC* input to internal horizontal pixel counter reset is 5 clocks. In both
master and slave modes, the pixel data pipeline delay is 52 clocks.
100138C
02/17/03
Conexant
1-7
Circuit Description
Bt864A/Bt865A Data Sheet
1.5
Video Timing
The width of the analog horizontal sync pulses and the start and end of color burst are
automatically calculated and inserted for each mode according to ITU-RBT.470-3.
Color burst is disabled on appropriate scan lines. Serration and equalization pulses are
generated on appropriate scan lines. In addition, rise and fall times of sync, closedcaption data transitions, and the burst envelope are internally controlled. Figure 1-4
through show the timing characteristics for various Bt864A/Bt865A modes of
operation.
Figure 1-4. Interlaced 525-Line (TSC) Video Timing
VSYNC*
RESET*
Analog
FIELD 1
523
524
525
1
2
4
3
5
6
7
8
9
10
22
BURST PHASE
Analog
FIELD 2
261
262
263
264
265
266
267
268
269
270
271
272
285
Analog
FIELD 3
523
524
525
1
2
4
3
5
6
7
8
9
10
22
BURST PHASE
Analog
FIELD 4
261
262
263
264
265
266
267
268
269
270
271
272
285
Burst begins with positive half-cycle
Burst Phase = Reference Phase = 180˚ relative to B–Y
Burst begins with negative half-cycle
Burst Phase = Reference Phase = 180˚ relative to B–Y
GENERAL NOTE:
SMPTE line numbering convention rather than ITU-R BT.470-3 is used. EVBI = 0.
100138_005
1-8
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
Circuit Description
Figure 1-5. Interlaced 525-Line (PAL-M) Video Timing
VSYNC*
RESET*
Analog
FIELD 1
523
524
525
1
2
4
3
5
6
7
8
9
10
11
12
22
273
274
285
11
12
22
273
274
285
BURST PHASE
Analog
FIELD 2
261
262
263
264
265
266
267
268
269
270
271
272
Analog
FIELD 3
523
524
525
1
2
4
3
5
6
7
8
9
10
BURST PHASE
Analog
FIELD 4
261
262
263
264
265
266
267
268
269
270
271
272
Burst Phase = Reference Phase = 135˚ relative to U
PAL Switch = 0, +V Component
Burst Phase = Reference Phase + 90˚ = 225˚ relative to U
PAL Switch = 1, –V Component
GENERAL NOTE:
SMPTE line numbering convention rather than ITU-R BT.470-3 is used. EVBI = 0.
100138_006
100138C
02/17/03
Conexant
1-9
Circuit Description
Bt864A/Bt865A Data Sheet
Figure 1-6. Interlaced 625-Line (PAL-B, D, G, H, I, Nc) Video Timing
VSYNC*
Analog
FIELD 1
RESET*
620
621
622
623
624
625
1
2
3
4
5
6
7
23
24
–U PHASE
Analog
FIELD 2
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog
FIELD 3
620
621
622
623
624
625
1
2
3
4
5
6
7
23
24
Analog
FIELD 4
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
FIELD One
Burst
Blanking
Intervals
FIELD Two
FIELD Three
FIELD Four
Burst Phase = Reference Phase = 135˚ relative to U
PAL Switch = 0, +V Component
Burst Phase = Reference Phase + 90˚ = 225˚ relative to U
PAL Switch = 1, –V Component
GENERAL NOTE: EVBI = 0.
100138_007
1-10
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
Circuit Description
Figure 1-7. Interlaced 625-Line (PAL-B, D, G, H, I, Nc) Video Timing
VSYNC*
Analog
FIELD 5
620
621
622
623
624
625
1
2
3
4
5
6
7
23
24
–U PHASE
Analog
FIELD 6
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog
FIELD 7
620
621
622
623
624
625
1
2
3
4
5
6
7
23
24
Analog
FIELD 8
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
FIELD Five
Burst
Blanking
Intervals
FIELD Six
FIELD Seven
FIELD Eight
Burst Phase = Reference Phase = 135˚ relative to U
PAL Switch = 0, +V Component
Burst Phase = Reference Phase + 90˚ = 225˚ relative to U
PAL Switch = 1, –V Component
GENERAL NOTE: EVBI = 0.
100138_008
100138C
02/17/03
Conexant
1-11
Circuit Description
Bt864A/Bt865A Data Sheet
Figure 1-8. Interlaced 625-Line (PAL-N) Video Timing
VSYNC*
Analog
FIELD 1
RESET*
620
621
622
623
624
625
1
2
3
4
5
6
7
23
24
–U PHASE
Analog
FIELD 2
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog
FIELD 3
620
621
622
623
624
625
1
2
3
4
5
6
7
23
24
Analog
FIELD 4
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
FIELD One
Burst
Blanking
Intervals
FIELD Two
FIELD Three
FIELD Four
Burst Phase = Reference Phase = 135˚ relative to U
PAL Switch = 0, +V Component
Burst Phase = Reference Phase + 90˚ = 225˚ relative to U
PAL Switch = 1, –V Component
GENERAL NOTE: EVBI = 0.
100138_009
1-12
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
Circuit Description
Figure 1-9. Interlaced 625-Line (PAL-N) Video Timing
VSYNC*
Analog
FIELD 5
620
621
622
623
624
625
1
2
3
4
5
6
7
23
24
–U PHASE
Analog
FIELD 6
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog
FIELD 7
620
621
622
623
624
625
1
2
3
4
5
6
7
23
24
Analog
FIELD 8
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
FIELD Five
Burst
Blanking
Intervals
FIELD Six
FIELD Seven
FIELD Eight
Burst Phase = Reference Phase = 135˚ relative to U
PAL Switch = 0, +V Component
Burst Phase = Reference Phase + 90˚ = 225˚ relative to U
PAL Switch = 1, –V Component
GENERAL NOTE: EVBI = 0.
100138_010
100138C
02/17/03
Conexant
1-13
Circuit Description
Bt864A/Bt865A Data Sheet
Figure 1-10. Noninterlaced 262-Line (NTSC) Video Timing
VSYNC*
RESET*
258
259
260
261
262
1
2
3
4
5
6
7
18
GENERAL NOTE:
CCIR 624 line numbering convention. EVBI = 0.
100138_011
Figure 1-11. Noninterlaced 262-Line (PAL-M) Video Timing
VSYNC*
RESET*
258
259
260
261
262
1
2
3
4
5
6
7
8
9
10
18
GENERAL NOTE:
CCIR 624 line numbering convention. EVBI = 0.
100138_012
Figure 1-12. Noninterlaced 312-Line (PAL-B, D, G, H, I, N, Nc) Video Timing
VSYNC*
RESET*
308
309 310
311
312
1
2
3
4
5
6
22
23
24
GENERAL NOTE: EVBI = 0.
100138_013
1-14
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
1.5.1
Circuit Description
Reset
If the RESET* pin is held low during a single rising edge of CLK, the subcarrier
phase is set to zero, and the horizontal and vertical counters are held to the first pixel
and second line of FIELD1. Counting resumes on the first rising edge of CLK after
rising RESET*.
A software reset will occur immediately after writing a 1 to register SRESET. This
will reset all software-programmable register bits to zero.
On power-up, the Bt864A/Bt865A will automatically perform a timing and software
reset. The power-up state has the following configuration: interlaced, NTSC CCIR601
black burst (no active video), and zero chroma scaling. Setting register EACTIVE will
enable active video. On power-up, the DACs are disabled for 8 fields or until register
0x67 (0xCE as 8-bit address) is written.
1.5.2
Sync and Burst Timing
Table 1-2 lists the resolutions and clock rates for the various modes of operation.
Table 1-2.
Field Resolution and Clock Rates for Various Modes of Operation
Active Luminance Resolution
(pixels)
Operating Mode
Total Resolution (pixels)
Non
Interlaced
Interlaced
Luminance
Pixel
Frequency
(MHz)
858 ± 1
262 ± 1/4
262.5 ± 1/4
13.5000
575
864 ± 1
312 ± 1/4
312.5 ± 1/4
13.5000
241
482
780 ± 1
262 ± 1/4
262.5 ± 1/4
12.2727
287
575
944 ± 1
312 ± 1/4
312.5 ± 1/4
14.7500
Horizontal
Vertical
Horizontal
Porch = 0
Non
Interlaced
Field
Interlaced
Frame
NTSC/PAL–MCCIR601
711
241
482
PAL–B, D, G, H, I, N, Nc
CCIR601
702
287
NTSC/PAL–M Square Pixel
647
PAL–B, D, G, H, I, N, Nc
Square Pixel
767
Vertical
GENERAL NOTE:
1. Tolerances apply to slave mode. Cumulative errors over color frame interval may result in subcarrier glitches.
2. Due to upsampling filter response, pixels near the boundary of the active definition will be reduced in amplitude due to
averaging with the blank level.
100138C
02/17/03
Conexant
1-15
Circuit Description
Bt864A/Bt865A Data Sheet
Table 1-3 lists the horizontal counter values for the end of horizontal sync, start of
color burst, end of color burst, and the first active pixel for the various modes of
operation. The front porch is the interval before the next expected falling HSYNC*
when outputs are automatically blanked.
The horizontal sync width is measured between the 50% points of the falling and
rising edges of horizontal sync.
The start of color burst is measured between the 50% point of the falling edge of
horizontal sync and the first 50% point of the color burst amplitude (nominally +20
IRE for NTSC/PAL–M and 150 mV for PAL–B, D, G, H, I, N, Nc above the blanking
level).
The end of color burst is measured between the 50% point of the falling edge of
horizontal sync and the last 50% point of the color burst envelope (nominally +20 IRE
for NTSC/PAL–M and 150 mV for PAL–B, D, G, H, I, N, Nc above the blanking
level).
Table 1-3.
Horizontal Counter Values for Various Video Timings
Horizontal Counter Value
Operating Mode
Equalization
Pulse Width
Horizontal/
Serration
Pulse Width
Start of Burst
Duration of
Burst
Back Porch
Front Porch(1)
HCNT
µs
HCNT
µs
HCNT
ms
HCNT
µs
HCNT
ms
HCNT
µs
NTSC CCIR601
32
2.37
63
4.67
72
5.33
34
2.52
127
9.41
20
1.48
PAL–M CCIR601
32
2.37
63
4.67
78
5.78
34
2.52
127
9.41
20
1.48
NTSC Square
29
2.36
58
4.73
65
5.30
31
2.53
115
9.37
18
1.47
PAL–M Square
29
2.36
58
4.73
71
5.79
31
2.53
115
9.37
18
1.47
PAL-B CCIR601
32
2.37
63
4.67
76
5.63
30
2.22
142
10.52
20
1.48
PAL–Nc CCIR601
32
2.37
63
4.67
76
5.63
34
2.52
142
10.52
20
1.48
PAL–B Square
35
2.37
69
4.68
83
5.63
33
2.24
155
10.51
22
1.49
PAL-Nc Square(2)
35
2.37
69
4.68
83
5.63
37
2.51
155
10.51
22
1.49
GENERAL NOTE:
1. HCNT refers to the number of luminance pixel periods; there are twice as many CLK periods as HCNT periods.
2. Odd counts at front porch transitions indicate invalid chroma framing.
FOOTNOTE:
(1)
In slave mode, since Front Porch timing is triggered by the previous HSYNC pulse, any deviation from nominal line length can
affect the front porch duration.
(2) PAL-Nc refers to the PAL format used in Argentina (Combination N).
1-16
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
1.5.3
Circuit Description
Master Mode
Horizontal sync (HSYNC*) and vertical sync (VSYNC*) are generated from internal
timing and from optional software bits. HSYNC* and VSYNC* are output following
the rising edge of CLK.
The HSYNC* output may be configured to have standard video timing (4.7 µs wide,
asserted at start of a line default after RESET cycle) or it may be programmed to specify
the start of HSYNC* (10-bit value) and the end of HSYNC* (10-bit value). VSYNC* is
asserted for 3 scan lines for 262/525 line formats and 2.5 scan lines for 312/625 line
formats (except for PAL-N which is 3 scan lines). When HSYNC* is configured for
standard video timing, coincident falling edges of HSYNC* and VSYNC* indicate the
beginning of the first field (CCIR convention). Auto mode detection is not applicable
under master mode operation.
1.5.4
Slave Mode
The horizontal counter is incremented on every other rising edge of CLK. A falling
edge of HSYNC* resets it to one, indicating the start of a new line.
The vertical counter is incremented on the falling edge of HSYNC*. A falling edge of
VSYNC* resets it to one, indicating the start of a new field (interlaced operation) or
frame (noninterlaced operation).
A falling edge of VSYNC* that occurs within ±1/4 of a scan line from the falling edge
of HSYNC* indicates the beginning of FIELD 1. A falling edge of VSYNC* that
occurs within ±1/4 scan line from the center of the line indicates the beginning of
FIELD 2. Referring to Figure 1-4 through , start of VSYNC* occurs on the falling
HSYNC* at the beginning of the next expected FIELD 1 and halfway between
expected falling HSYNC* edges at the beginning of the next expected FIELD 2.
HSYNC* and VSYNC* must remain low for at least 2 CLK cycles. The operating
mode (NTSC/PAL, interlaced/noninterlaced, square pixel/CCIR601, and setup) is
automatically determined when configured as a slave when the SETMODE bit is zero.
525-line operation is assumed, unless 625-line operation is detected by the number of
lines in a field. Interlaced operation is detected by observing the sequence of FIELD 1
or FIELD 2; if the field timing (odd follows odd, even follows even) is repeated, then
noninterlaced mode is assumed. The frequency of operation (square pixels or CCIR)
is detected by counting the number of clocks per line. The pixel rate is assumed to be
13.5 MHz unless the exact horizontal count for square pixels, ±1 count, is detected in
between two successive falling edges of HSYNC*.
NOTE:
Square pixel 625-line operation with this sequence requires one frame to
stabilize.
By setting SETMODE = 1, the video format control register bits (VIDFORM [3:0],
SETUPDIS, NONINTL, and SQUARE) will determine the operating mode.
100138C
02/17/03
Conexant
1-17
Circuit Description
1.5.5
Bt864A/Bt865A Data Sheet
FIELD Output
The FIELD output indicates whether FIELD 1 (logical zero) or FIELD 2 (logical one)
is being generated. This corresponds directly to the “bottom/top” convention of some
MPEG decoders. Field transitions after the rising edge of CLK, two clock periods
after the falling edge of VSYNC* if SYNCDLY = 0, or three clock periods after the
falling edge of VSYNC* if SYNCDLY = 1.
To invert the sense of the FIELD output, set the FIELDI bit to a logical one.
1.5.6
Pixel Blanking
BLANK* is registered on the rising edge of CLK. For video outputs, BLANK* is
pipelined to match the luminance and chrominance paths and is applied to the digital
video before analog conversion. The automatic horizontal blanking sequence
described in Table 1-3 takes precedence over the BLANK* input.
1.5.7
Burst Blanking
For interlaced NTSC, color burst information is automatically disabled on scan lines
1–9 and 264–272, inclusive. (SMPTE line numbering convention.)
For interlaced PAL-M color burst information is automatically disabled on scan lines
1–11 and 263–273 and 525 of FIELD 1 and FIELD 2 and scan lines 1–10 and 262–
272 of FIELDs 3 and 4.
For interlaced PAL–B, D, G, H, I, N, Nc, color burst information is automatically
disabled on scan lines 1–6, 310–318, and 623–625, inclusive, for FIELDs 1, 2, 5, and
6. During FIELDs 3, 4, 7, and 8, color burst information is disabled on scan lines 1–5,
311–319, and 622–625, inclusive.
For noninterlaced NTSC, color burst information is automatically disabled on scan
lines 1–6 and 260–262, inclusive.
For noninterlaced PAL-M, color burst information is automatically disabled on scan
lines 1–10 and 260–262.
For noninterlaced PAL–B, D, G, H, I, N, Nc, color burst information is automatically
disabled on scan lines 1–6 and 310–312, inclusive. See Figure 1-4 through .
1.5.8
Digital Processing
The input is scaled to YUV format. For the CVBS, Y, and C outputs, the UV
components are low-pass filtered with a filter response shown in Figure 1-13 and 1-14
(linearly scalable by clock frequency). The Y and filtered UV components are
upsampled to CLK frequency by a digital filter whose response is shown in
Figure 1-15 and 1-16. For the RGB outputs, the scaled YUV is color space converted
and output.
1.5.9
Chrominance Disable
The chrominance subcarrier may be turned off by setting the DCHROMA bit to a logical
one. This kills burst as well, providing luminance only signals on the CVBS outputs and a
static blank level on the C/R output (RGBOUT = 0).
1-18
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
Circuit Description
Figure 1-13. Three-Stage Chrominance Filter
5
0
–5
Attenuation (dB)
–10
–15
–20
–25
–30
–35
–40
–45
0
1
2
4
3
5
6
Frequency (MHz)
CLK = 27 MHz
100138_014
Figure 1-14. Three-Stage Chrominance Filter (Passband)
0.5
0
Attenuation (dB)
–0.5
–1
–1.5
–2
–2.5
–3
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Frequency (MHz)
CLK = 27 MHz
100138_015
100138C
02/17/03
Conexant
1-19
Circuit Description
Bt864A/Bt865A Data Sheet
Figure 1-15. Luminance 2X Upsampling Filter Response
0
Attenuation (dB)
–10
–20
–30
–40
–50
–60
0
2
4
6
8
10
12
Frequency (MHz)
CLK = 27 MHz
100138_016
Figure 1-16. Luminance 2X Upsampling Filter Response (Passband)
0.5
0
Attenuation (dB)
–0.5
–1
–1.5
–2
–2.5
–3
0
2
4
6
8
10
12
Frequency (MHz)
CLK = 27 MHz
100138_017
1-20
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
1.5.10
Circuit Description
Subcarrier Phasing
In order to maintain correct SC-H phasing, the subcarrier phase is set to zero on the
falling edge of HSYNC* associated with VSYNC* every four (NTSC) or eight (PAL)
fields, unless the SCRESET bit is set to a logical one.
In slave mode, falling HSYNC* may lag falling VSYNC* by 1/4 scan line but cannot
precede falling VSYNC* by more than seven CLK periods for correct SC-H reset.
Setting SCRESET to one may be useful in situations where the ratio of CLK/2 to
HSYNC* edges in a color frame is noninteger, which could produce a significant
phase impulse by resetting to zero.
1.5.11
Vertical Blanking Intervals
For interlaced NTSC/PAL–M, if EVBI = 0, scan lines 1–21 and 263–284, inclusive,
are always blanked regardless of the BLANK* input (SMPTE line numbering
convention).
For interlaced PAL–B, D, G, H, I, N, Nc, if EVBI = 0, scan lines 1–23, 311–335, and
624–625, inclusive, are always blanked regardless of the BLANK* input.
For noninterlaced NTSC/PAL–M, if EVBI = 0, scan lines 1–17 and 261–262,
inclusive, are always blanked regardless of the BLANK* input. For noninterlaced
PAL–B, D, G, H, I, N, Nc, if EVBI = 0, scan lines 1–22 and 311–312, inclusive, are
always blanked regardless of the BLANK* input.
Alternately, all displayed lines in the vertical blanking interval (10–21 and 273–284
for interlaced NTSC/PAL–M; 6–23 and 320–335 for interlaced PAL–B, D, G, H, I, N,
Nc; 10–21 for noninterlaced NTSC/PAL–M, 7–23 for noninterlaced PAL–B, D, G, H,
I, N, Nc) may be enabled by setting the EVBI bit to a logical one (except for caption
lines controlled by bits ECCF1 or ECCF2, or the Macrovision process).
1.5.12
BLANK* Pin
The BLANK* pin can be used to BLANK any portion of the active display lines
(including those enabled by EVBI) by driving the pin to a logical zero.
1.5.13
Noninterlaced Operation
When the Bt864A/Bt865A is programmed for noninterlaced master mode, the
Bt864A/Bt865A always displays FIELD 1, meaning that the falling edges of
HSYNC* and VSYNC* will be output coincidentally. FIELD will be held low if
FIELDI = 0. Additionally, a 30 Hz offset will be subtracted from the color subcarrier
frequency while in NTSC mode so that the color subcarrier phase will be inverted
from field to field.
Transition from interlaced to noninterlaced in master mode, occurs during FIELD 1 to
prevent synchronization disturbance. In slave mode, transition occurs after a
subsequent falling edge of VSYNC*.
NOTE:
100138C
02/17/03
Consumer VCRs can record noninterlaced video with minor noise artifacts,
but special effects (e.g., scan > 2x) may not function properly.
Conexant
1-21
Circuit Description
1.6
Bt864A/Bt865A Data Sheet
Power Saving Modes
In SLEEP power-down mode (SLEEP pin set to 1), all analog and digital circuitry is
disabled, and total device current consumption approaches 0 mA. Register states are
preserved, but other chip functionality (including I2C communication) is disabled.
This mode should be set when the Bt864A/Bt865A may be subjected to clock and
data frequencies outside its functional range.
In DACOFF power-down mode, (DACOFF register is set to 1) all DACs are disabled
and analog current is reduced to approximately 0 mA. All other digital circuitry
remains operational, permitting system timing and other functions to continue.
When DACs are disabled by either SLEEP or DACOFF, VREF will go to approximately
0.5 V below VAA.
1.7
Pixel Input Ranges and Colorspace Conversion
1.7.1
YC Inputs (4:2:2 YCrCb)
Y has a nominal range of 16–235; Cb and Cr have a nominal range of 16–240, with
128 equal to zero. Values of 0 and 255 are interpreted as 1 and 254, respectively. Y
values of 1–15 and 236–254, and CrCb values of 1–15 and 241–254, are interpreted as
valid linear values.
The SETUPDIS bit will alter pixel scaling and disable or enable the 7.5 IRE setup.
When this bit is enabled, PAL–B, D, G, H, I, N, Nc video can be generated using
NTSC/PAL–M blanking levels and 7.5 IRE setup, and NTSC/PAL–M pixel scaling is
performed (Y range of 16–235 represents 7.5–100 IRE); or, NTSC/PAL–M video can
be generated using PAL–B, D, G, H, I, N, Nc scaling (Y range of 16–235 represents
0–100 IRE) without the 7.5 IRE setup. NTSC/PAL–M mode with setup disabled has
2% less black-to-white range than NTSC/PAL–M mode with setup enabled.
For RGBOUT mode, 4:2:2 YCrCb digital component video will be upsampled to
4:4:4 and used to generate composite video and will be converted to the RGB
colorspace to drive the RGB DACs. The Y input range of 16–235 will produce a range
of 0.7 V at the output. Since YC values outside of the nominal range are allowed, the
black level is raised above zero volts to allow for Y values less than 16, and the output
range of the DACs can exceed 0.7 V to allow for Y values above 235. The conversion
is linearly scaled in the overshoot and undershoot regions. The following matrix,
based on CCIR601, is used to convert YCrCb to RGB:
‹ R = Y + 1.371*Cr
‹ G = Y – 0.699*Cr – 0.337*Cb
‹ B = Y + 1.733*Cb
Values are rounded to 9 bits at the DAC.
1-22
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
1.7.2
Circuit Description
DAC Coding
For all video formats, the input luma and chroma values are scaled internally such
that, after sync and setup (if enabled) are added, the output from sync to 100% white
(for CVBS/Y outputs) is approximately 1.00 V.
In addition, the chroma is boosted to compensate for the sinx/x rolloff due to the DAC
(see Figures 1-17 and 1-18). The amount of boost is determined by SETUPDIS.
Table 1-4 summarizes the blank, black, and 100% white DAC codes and chroma gain
values as a function of SETUPDIS.
Table 1-4. DAC Coding
SETUPDIS
Blank
Black
100% White
Chroma Gain
0
228
272
801
1.02944
1
224
224
800
1.0458
Figure 1-17. DAC Sinx/x Response
0
–0.5
–1
Attenuation (dB)
–1.5
–2
–2.5
–3
–3.5
–4
–4.5
–5
0
2
4
6
8
10
12
Frequency (MHz)
CLK = 27 MHz
100138_018
100138C
02/17/03
Conexant
1-23
Circuit Description
Bt864A/Bt865A Data Sheet
Figure 1-18. DAC Sinx/x Response (Passband)
0
–0.1
–0.2
Attenuation (dB)
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1
0
1
2
3
4
5
6
Frequency (MHz)
CLK = 27 MHz
100138_019
1.8
Closed Captioning
The Bt864A/Bt865A encodes NTSC/PAL–M closed captioning on scan line 21 and
NTSC/PAL–M extended data services on scan line 284. Four 8-bit registers (CCF1B1,
CCF1B2, CCF2B1, and CCF2B2) provide the data while bits ECCF1and ECCF2
enable display of the data. A logical zero corresponds to the blanking level of 0 IRE,
while a logical one corresponds to 50 IRE above the blanking level.
Closed captioning for PAL–B, D, G, H, I, N, Nc is similar to that for NTSC. Closed
caption encoding is performed for 625-line systems according to the system proposed
by the National Captioning Institute; clock and data timing is identical to that of
NTSC system, except that encoding is provided on lines 22 and 335.
The Bt864A/Bt865A generates the clock run-in and appropriate timing automatically.
Pixel inputs are ignored during CC encoding. See FCC Code of Federal Regulations
(CFR) 47 Section 15.119 (10/91 edition or later) for programming information.
EIA608 describes ancillary data applications for FIELD 2 Line 21 (line 284).
When CCF1B2 is written, CCSTAT1 is set; when CCF2B2 is written CCSTAT2 is set
(CCSTAT1 and CCSTAT2 are defined in Table 2-1). After the closed-caption bytes
for FIELD 1 are encoded, CCSTAT1 is cleared; after the closed-caption bytes for
FIELD 2 are encoded, CCSTAT2 is cleared. If the ECCGATE bit is set, no further
encoding will be performed until the appropriate registers are again written; a NULL
with odd parity will be transmitted on the appropriate closed caption line in that case.
User must set the odd parity bit. If the ECCGATE bit is not set, the user must rewrite
the closed-caption registers prior to reaching the closed-caption line, otherwise the
last bytes will be re-encoded.
1-24
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
Circuit Description
Closed-caption will override EVBI inserted data on lines 21 and 284 for 525-line
formats, and lines 22 and 335 for 625-line formats. Closed-caption will be overridden
by teletext if teletext is enabled on these lines.
Closed caption data registers are double buffered and can be loaded without the risk of
corrupting data as it is being encoded onto the appropriate video line (line 21 or 284
for 525-line formats, line 22 or 335 for 625-line formats).
1.9
Teletext
Teletext encoding is accomplished via a two-wire interface, TTXDAT and TTXREQ,
and internal registers that are programmed through the I2C interface. Teletext
encoding in the Bt864A/Bt865A conforms to Teletext B for 625/50 television
systems. See “Recommendation 653-1 Teletext Systems” for further information
about the standard. Teletext should be disabled for 525-line television systems.
The internal registers allow for the enable/disable of teletext and the programming of
the start and stop of the TTXREQ signal, the active teletext lines in an FIELD 1, and
the active teletext lines in FIELD 2. Active teletext lines override closed caption,
Macrovision, the BLANK* input, and active video. See the “Internal Registers”
section for more details.
The TTXREQ signal is generated by the encoder to indicate to external devices when
teletext data is required. The start and end of the TTXREQ signal waveform is
determined by the value of registers TXHS and TXHE, respectively. The values of
registers TXHS and TXHE correspond to the internal clock (CLK) counter (see
Figure 1-19). The proper selection of these edges will allow the user to adjust for the
propagation delay of the teletext source, so that the teletext data is provided to the
TTXDAT pin at the proper time. If the falling edge of TTXREQ does not occur by the
end of the video line, the beginning of the new video line will automatically reset
TTXREQ. Legal values for these registers are given in Table 1-5.
The data to TTXDAT is sampled on every rising input clock edge and must meet the
following protocol for proper teletext data insertion. The protocol demands that the
teletext data bit duration is the required number of CLKs.
Internal to the chip is a sequencer and a data shaper to minimize the jitter. Using the
midpoint of the falling edge of the horizontal sync pulse as it appears at the output Y/
CVBS or CVBS/G, the teletext data protocol must begin 262 to 264 CLKs later for
CCIR601(13.5 MHz pixel rate) or 286 to 288 CLKs later for Square Pixel Operation
(14.75 MHz pixel rate). Relative to the internally generated teletext window, the
protocol must start 5 to 7 clocks earlier. The teletext window begins at 10.2 µsec from
the horizontal sync pulse's falling edge and the data rate is the specified 6.9375 Mbits/
sec.
100138C
02/17/03
Conexant
1-25
Circuit Description
Bt864A/Bt865A Data Sheet
Figure 1-19. Teletext Timing for Tb864A/Bt865A Encoder
(1)
TTXREQ
(2)
tPD(3)
(4)
tTTXINT
TTXDAT
tTTXOWS(5)
CVBS(6)
CVBS/G
Y/CVBS
tTTXIWS(7)
Internal
Horizontal
Reset
Internal
Clock (CLK)
Counter(9)
(8)
2 3 4 5...
2 3 4 5...
GENERAL NOTE:
1. TXE is enabled and video line is a valid teletext line. See "teletext" on page 1-26.
FOOTNOTE:
(1) Placement of rising edge of TTXREQ is definable using register TXHS[10:0].
(2) Placement of falling edge of TTXREQ is definable using register TXHE[10:0].
(3) TTXREQ is generated by the encoder using programmable registers TXHS and TXHE. This allows the user to adjust for
the propagation delay (tPD) in CLK cycles of the teletext data source.
(4) TTXDAT is supplied to the encoder at the proper time to be interpolated by the encoder (t
TTXINT) and inserted into
the video output signals. The Teletext data must follow the correct protocol. See "Teletext" on page 1-26.
(5) t
TTXOWS is the start of the teletext output window and is fixed internally by the encoder at 10.2 usec.
(6) Luma Delay is set to zero.
(7) t
TTXIWS is the start of the teletext input window and is fixed internally.
(8) If the falling edge of TTXREQ does not occur by the end of a video line, the beginning of a new line will automatically
reset TTXREQ.
(9) 2 clock (CLK) counts = 1 pixel clock count.
100138_020
Table 1-5.
1-26
Legal Values to TXHS and TXHE
Pixel rate
TXHS
TXHE
Min. Value
13.5 MHz
2
TXHS + 2
Max. Value
13.5 MHz
0x6BE
0x7FF
Min. Value
14.75 MHz
2
TXHS + 2
Max. Value
14.75 MHz
0x75E
0x7FF
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
1.9.1
Circuit Description
CCIR601 Operation (13.5 MHz pixel rate)
The bit duration follows this pattern which repeats every 37 teletext bits. Each teletext data
bit is carried by four CLKs except bits 10, 19, 28, and 37 which are three CLKs in
duration. This pattern continues until all 360 bits (1402 CLKs) have been transferred.
1.9.2
Square Pixel Operation (14.75 MHz pixel rate)
This bit pattern repeats after every 111 teletext bits: After every teletext bit that is carried
by five CLKs the next three teletext bits are carried by four CLKs except for the first bit of
the pattern which is five CLKs in duration and only the next two bits are carried by four
CLKs. This pattern continues until all 360 bits (1531 CLKs) have been transferred. The
repeating bit duration pattern starting at bit 1 would be:
1.9.3
Bit number:
1 2 3 4 5 6 7 8 9
10
11
12
13
14
15...
Duration in
CLKs:
5 4 4 5 4 4 4 5 4
4
4
5
4
4
4...
Teletext Clock Generation
Figure 1-20 shows how to generate a teletext clock using a P:Q ratio counter for
shifting out the teletext data serially to the Bt864A/Bt865A. The diagram is for
illustrative purposes only. The actual implementation is left to the user.
Figure 1-20. PQ Ratio Counter
ADDER
A
P
MODULO
Q
REGISTER
SUM
B
CLK
CO
RSTN
ENABLE_TTX_CLK
D
Q
Teletext Clock
CLK
100138_021
Table 1-6. Teletext Clock P and Q Values
100138C
02/17/03
CLK
Pixel Rate
P
Q
27 MHz
13.5 MHz
37
144
29.5 MHz
14.75 MHz
111
472
Conexant
1-27
Circuit Description
1.9.4
Bt864A/Bt865A Data Sheet
Teletext Clock Output
The Bt864A/Bt865A can output the teletext clock from the TTXREQ pin by setting
TXRM = 1. In this mode, this teletext clock would only be output on active teletext lines
and each line would have exactly 360 clocks to be used to synchronize the teletext data to
the Bt864A/Bt865A. The rising edge of clock could be used to latch the data on the output
of the device providing the teletext data. The falling of the clock indicates that the
Bt864A/Bt865A has received the teletext data.
1.10
Copy Generation Management System (CGMS)
Encoding
Copy Generation Management System (CGMS) is used in 525-line systems on lines
20 and 283 (a.k.a. line 20, field 2). The CGMS data is 20 bits long and is entered on
register bits WSDAT[20:1].
‹ Set register bit EWSF1 to 1 to enable CGMS on field 1, line 20.
‹ Set register bit EWSF2 to 1 to enable CGMS on field 2, line 283.
Although there is no clock run-in in CGMS, a reference pulse is provided
automatically.
CRC data is not calculated and must be provided by the user. Figure 1-21 illustrates a
typical CGMS signal. Note that bit 1 is closest to the HSYNC pulse and bit 20 is
farthest. The amplitude of the CGMS pulses are 70 IRE when high, and 0 IRE when
low. For further CGMS details, see specifications EIA-J CPR-1202, EIA-J CPR-1204,
and IEC 61880.
Figure 1-21. Typical CGMS Waveform
V
IRE
1.0
100
0.786
70
0.286
0
Reference
Bit No.
1
2
3
.. .. ..
20
2.235 µs ± 50 ns
0
–40
11.2 µs ± 0.3 µs
49.1 µs ± 0.44 µs
Line 20/283
100138_036
1-28
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
1.11
Circuit Description
Anticopy Process (Bt865A Only)
The anticopy process contained within the Bt865A is implemented according to the
Macrovision version 7 specification developed by Macrovision Corporation in
Sunnyvale, California. All luminance, chrominance, and composite video waveforms
include the Macrovision Anticopy Process. The Bt865A incorporates an anticopy
process technology that is protected by U.S. patents and other intellectual property
rights. The anticopy process is licensed for noncommercial, home use only. Reverse
engineering or disassembly is prohibited.
Conexant cannot ship Bt865A encoders to any customer until that customer has been
licensed by Macrovision. Contact Macrovision Corporation to facilitate this license
agreement. Parties who have obtained a Macrovision license may receive the Bt865A
Macrovision Supplement by contacting Conexant.
1.12
Internal Color Bars
The Bt864A/Bt865A can be configured to internally generate colorbar test patterns
(100/7.5/75/7.5 with SETUPDIS = 0 for NTSC/PAL-M,N; 100/0/75/0 with
SETUPDIS = 1 for NTSC–Japan, PAL, BDGHI, Nc).
Internal color bars can be enabled by setting the ECBAR bit to a logical one. In 8-bit
YCrCb mode, setting the Y[7] pin to a logical one also enables color bars, thereby
simplifying testing of various modes. Internal color bars can be enabled in all video
formats.
1.13
SCART/PeriTV Support
RGBOUT mode can be enabled by setting the RGBOUT pin to a logical one, or by
setting register bit RGBO. The Bt864A/Bt865A can generate analog RGB video
signals to interface to a SCART/PeriTV connector (see Table 1-7). Composite video
will be present on the Y/CVBS DAC. RGB outputs are nominally 700 mVpp (black to
white without setup).
1.14
I2C Interface
A simplified 100 kbps I2C interface is provided for programming the registers. CLK must
be applied and remain stable for I2C communication. Activating SLEEP or RESET* will
disable I2C communication.
100138C
02/17/03
Conexant
1-29
Circuit Description
1.15
Bt864A/Bt865A Data Sheet
Analog Outputs
All digital-to-analog converters are designed to drive standard video levels into a
combined RLOAD of 37.5 Ω. Unused outputs should be connected directly to ground
to minimize supply switching currents. In standard mode, one S-Video (Y/C), and two
composite video outputs are available. In RGBOUT mode, one composite video
output along with analog RGB are available (see Table 1-7). If the SLEEP pin is high
or DACOFF = 1, the DACs are essentially turned off and only the leakage current is
present. The D/A converter values for 100% saturation, 100% amplitude color bars
are shown in Figures 1-22 through 1-27. Both composite video and analog RGB video
(to provide support for SCART/PeriTV) may be generated simultaneously.
Table 1-7. DAC Output Cross-Reference
Pin Number
Pin Function
DAC Name
1.15.1
Signal
AGND
Std Mode
RGB Out Mode
CVBS/B
8
6
CVBS
B
CVBS/G
10
7
CVBS
G
C/R
12
9
C
R
Y/CVBS
13
11
Y
CVBS
Luminance or CVBS (Y/CVBS) Output
Digital luminance information drives the 10-bit D/A converter that generates the
analog Y video output (Figures 1-22 and 1-23 and Tables 1-8 and 1-9). This DAC can
also provide CVBS for SCART/PeriTV synchronization when RGBOUT is enabled.
1.15.2
Chrominance or Red (C/R) Output
Digital chrominance information drives the 10-bit D/A converter that generates the
analog C video output (Figures 1-24 and 1-25 and Tables 1-10 and 1-11). This DAC
can also provide Red for SCART/PeriTV when RGBOUT is enabled.
1.15.3
Composite Video or Blue (CVBS/B) Output
Digital composite video information drives the 10-bit D/A converter that generates
the analog NTSC or PAL video output (Figures 1-26 and 1-27 and Tables 1-12 and
1-13). This DAC can also provide Blue for SCART/PeriTV when RGBOUT is
enabled. An optional luminance delay can be enabled on this pin (in standard mode
only) by setting the LUMADLY bits. The luma can be delayed 0 to 3 pixels (up to
200–245 ns) to compensate for group delays introduced in the chroma path by
external filters or vestigial sideband processing.
1.15.4
Composite Video or Green (CVBS/G) Output
Digital composite video information drives the 10-bit D/A converter that generates
the analog video output (Table 1-14). This DAC can also provide Green for SCART/
PeriTV when RGBOUT mode is enabled.
1-30
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
Circuit Description
801
Black
Blue
Red
Magenta
1.000
Green
26.68
Cyan
V
Yellow
mA
White
Figure 1-22. Y (Luminance) Video Output Waveform SETUPDIS = 0
White Level
790
644
583
489
100 IRE
429
332
9.07
7.60
0.340
0.285
Black Level
Blank Level
7.5 IRE
40 IRE
0.00
Sync Level
0.000
GENERAL NOTE: Typical with 37.5 Ω load, nominal RSET. SMPTE 170 M levels are assumed. 100% saturation color bars (100/7.5/100/7.5)
are shown.
100138_023
Table 1-8.
Y (Luminance) Video Output Truth Table SETUPDIS = 0
Iout (mA)
DAC Data
Sync Interval
BLANK*(1)
White
26.68
801
0
1
Black
9.07
272
0
1
Blank
7.60
228
0
0
Sync
0
0
1
0
Description
GENERAL NOTE:
1. Typical with 37.5 Ω load, nominal RSET, and setup on. SMPTE 170 M levels are assumed. 100% saturation color bars (100/
7.5/100/7.5) are shown.
FOOTNOTE:
(1)
BLANK occurs by external BLANK* pin or internally generated BLANK.
100138C
02/17/03
Conexant
1-31
Circuit Description
Bt864A/Bt865A Data Sheet
800
Black
Blue
Red
Magenta
1.000
Green
26.68
Cyan
V
Yellow
mA
White
Figure 1-23. Y (Luminance) Video Output Waveform SETUPDIS = 1
White Level
736
634
570
470
406
304
8.0
0.300
Black/Blank Level
0.00
0.000
Sync Level
GENERAL NOTE: Typical with 37.5 Ω load and nominal RSET. ITU-RBT.470-3 levels are assumed. 100% saturation
(100/0/100/0) color bars are shown.
100138_024
Table 1-9.
Y (Luminance) Video Output Truth Table SETUPDIS = 1
Iout (mA)
DAC Data
Sync Interval
BLANK*(1)
White
28.68
800
0
1
Black
8.00
240
0
1
Blank
8.00
240
0
0
Sync
0
0
1
0
Description
GENERAL NOTE:
1. Typical with 37.5 Ω load and nominal RSET. ITU-RBT.470-3 levels are assumed. 100% saturation (100/0/100/0) color bars
are shown.
FOOTNOTE:
(1)
1-32
BLANK occurs by external BLANK* pin or internally generated BLANK.
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
Circuit Description
0.640
13.27
0.498
20 IRE
Black
17.07
Blue
0.783
Red
20.88
Magenta
1.058
Green
28.21
Cyan
V
White
mA
Yellow
Figure 1-24. C (Chrominance) Video Output Waveform SETUPDIS = 0
Blank
Level
20 IRE
Color Burst
(9 Cycles)
5.93
0.222
GENERAL NOTE:
Typical with 37.5 Ω load, nominal RSET, and chroma on. SMPTE 170 M levels are assumed. 100% saturation color bars
(100/7.5/100/7.5) are shown.
100138_025
Table 1-10. C (Chrominance) Video Output Truth Table SETUPDIS = 0
Iout (mA)
DAC Data
Sync Interval
BLANK*(1)
Peak Chroma (High)
28.21 [25.56]
856 [770]
x
1
Burst (High)
20.88 [20.88]
629 [629]
x
x
Blank
17.07 [17.07]
512 [512]
x
0
Burst (Low)
13.27 [13.27]
395 [395]
x
x
5.93 [8.53]
168 [254]
x
1
Description
Peak Chroma (Low)
GENERAL NOTE:
1. Typical with 37.5 Ω load, nominal RSET, and chroma on. SMPTE 170 M levels are assumed. 100% saturation color bars (100/
7.5/100/7.5) are shown.
2. Bracketed values indicate expected values when using the internal color bars (100/7.5/75/7.5).
FOOTNOTE:
(1)
BLANK occurs by external BLANK* pin or internally generated BLANK.
100138C
02/17/03
Conexant
1-33
Circuit Description
Bt864A/Bt865A Data Sheet
0.640
13.07
0.490
Black
17.07
Blue
0.791
Red
21.08
Magenta
1.083
Green
28.88
Cyan
V
White
mA
Yellow
Figure 1-25. C (Chrominance) Video Output Waveform SETUPDIS = 1
Blank
Level
Color Burst
(10 Cycles)
5.27
0.198
GENERAL NOTE: Typical with 37.5 Ω load, nominal RSET, and chroma on. ITU-RBT.470-3 levels are assumed. 100%
saturation (100/0/100/0) color bars are shown.
100138_026
Table 1-11. C (Chrominance) Video Output Truth Table SETUPDIS = 1
Iout (mA)
DAC Data
Sync Interval
BLANK*(1)
Peak Chroma (High)
28.88 [26.06]
877 [785]
x
1
Burst (High)
21.08 [21.08]
635 [635]
x
x
Blank
17.07 [17.07]
512 [512]
x
0
Burst (Low)
13.07 [13.07]
389 [389]
x
x
5.27 [7.97]
147 [239]
x
1
Description
Peak Chroma (Low)
GENERAL NOTE:
1. Typical with 37.5 Ω load, nominal RSET, and chroma on. ITU-RBT.470-3 levels are assumed. 100% saturation (100/0/100/0)
color bars are shown.
2. Bracketed values indicate expected values when using the internal color bars (100/0/75/0).
FOOTNOTE:
(1)
1-34
BLANK occurs by external BLANK* pin or internally generated BLANK.
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
Circuit Description
34 IRE
801
Black
Blue
1.000
Red
26.68
Magenta
1.221
Green
32.55
Cyan
V
Yellow
mA
White
Figure 1-26. CVBS (Composite) Video Output Waveform SETUPDIS = 0
White Level
740
644
583
100 IRE
11.41
9.07
7.60
0.423
0.340
0.285
3.80
3.20
0.00
0.143
0.120
0.000
489
429
Color Burst
(9 Cycles)
332
Black Level
Blank Level
20 IRE 7.5 IRE
20 IRE
40 IRE
Sync Level
GENERAL NOTE:
Typical with 37.5 Ω load, nominal RSET, clipping off, and chroma on. SMPTE 170 M levels are assumed. 100% saturation
color bars (100/7.5/100/7.5) are shown.
100138_027
Table 1-12. CVBS (Composite) Video Output Truth Table SETUPDIS = 0
Description
Iout (mA)
DAC Data
Sync Interval
BLANK*(1)
Peak Chroma (High)
32.55 [30.38]
988 [922]
0
1
White
26.68 [26.68]
801 [801]
0
1
Burst (High)
11.41 [11.41]
345 [345]
0
x
Black
9.07 [9.07]
272 [272]
0
1
Blank
7.60 [7.60]
228 [228]
0
0
Burst (Low)
3.80 [3.80]
111 [111]
0
x
Peak Chroma (Low)
3.20 [5.32]
85 [149]
0
1
0 [0]
0 [0]
1
0
Sync
GENERAL NOTE:
1. Typical with 37.5 Ω load, nominal RSET, clipping off, and chroma on. SMPTE 170 M levels are assumed. 100% saturation
color bars (100/7.5/100/7.5) are shown.
2. Bracketed values indicate expected values when using the internal color bars (100/7.5/75/7.5).
FOOTNOTE:
1. BLANK occurs by external BLANK* pin or internally generated BLANK.
100138C
02/17/03
Conexant
1-35
Circuit Description
Bt864A/Bt865A Data Sheet
800
Black
Blue
1.000
Red
26.68
Magenta
1.233
Green
32.88
Cyan
V
Yellow
mA
White
Figure 1-27. CVBS (Composite) Video Output Waveform SETUPDIS = 1
White Level
736
634
570
470
12.01
0.450
8.00
0.300
4.00
0.150
1.80
0.068
0.00
0.000
Color Burst
(10 Cycles)
406
304
Black/Blank
Level
Sync Level
GENERAL NOTE:
Typical with 37.5 Ω load, nominal RSET, and clipping off. ITU-RBT.470-3 levels are assumed. 100% amplitude,
100% saturation (100/0/100/0) color bars are shown.
100138_028
Table 1-13. CVBS (Composite) Video Output Truth Table SETUPDIS = 1
Iout (mA)
DAC Data
Sync Interval
BLANK*(1)
Peak Chroma (High)
32.88 [30.61]
998 [929]
0
1
White
26.68 [26.68]
800 [800]
0
1
Burst (High)
12.01 [12.01]
363 [363]
0
x
Black
8.00 [8.00]
240 [240]
0
1
Blank
8.00 [8.00]
240 [240]
0
0
Burst (Low)
4.00 [4.00]
117 [117]
0
x
Peak Chroma (Low)
1.80 [3.76]
41 [110]
0
1
0 [0]
0 [0]
1
0
Description
Sync
GENERAL NOTE:
1. Typical with 37.5 Ω load, nominal RSET, and clipping off. ITU-RBT.470-3 levels are assumed. 100% amplitude, 100%
saturation (100/0/100/0) color bars are shown.
2. Bracketed values indicate expected values when using the internal color bars (100/0/75/0).
FOOTNOTE:
(1)
1-36
BLANK occurs by external BLANK* pin or internally generated BLANK.
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
Circuit Description
Table 1-14. RGB Output Table (RGBOUT = 1)
SETUPDIS = 1
SETUPDIS = 0
BLANK*(1)
Description
Iout (mA)
DAC Data
Iout (mA)
DAC Data
White
18.68
560
18.68
560
1
Black
0
0
1.47
44
1
Blank
0
0
0
0
0
GENERAL NOTE: Iout typical with 37.5 Ω load, nominal RSET.
FOOTNOTE:
(1)
BLANK occurs by external BLANK* pin or internally generated BLANK
100138C
02/17/03
Conexant
1-37
Circuit Description
1-38
Bt864A/Bt865A Data Sheet
Conexant
100138C
02/17/03
2
Internal Registers
A read-back bit map is given in Table 2-1, and a register bit map is given in Table 2-2.
Bit descriptions and detailed programming information follow the bit map. When a
read does occur, only the data from Table 2-1 can be read. To read, write 0x8B after a
start condition if pin ALTADDR is low and 0x89 if pin ALTADDR is high. All
registers are write-only and are set to zero following a software reset. A software reset
is always performed at power-up; after power-up, a reset can be triggered by writing
the SRESET register bit. Figure 3-5 illustrates timing required for I2C
communications.
Table 2-1. Read-Back Bit Map
ESTATUS
7
6
0
ID[2:0]
1
ID[2:0]
5
4
3
2
1
0
VERSION[4:0]
CCSTAT[2]
CCSTAT[1]
FIELD[2:0]
GENERAL NOTE: The ID[2:0] bits indicate the part number: 4 is returned from the Bt864A; 5 is returned from the Bt865A. The
version number is indicated by bits VERSION[4:0]. For this revision, VERSION[4:0] = 0x11. The CCSTAT[2] bit is
high if closed-caption data has been written for the even field; it is low immediately after the clock run-in on line
284 or 335. The CCSTAT[1] bit is high if closed-caption data has been written for the odd field; it is low
immediately after the clock run-in on line 21 or 22. The FIELD[2:0] bits represent the field number, where 000
indicates the first field.
2.1
Essential Registers
The power-up state is defined to be black burst CCIR601 NTSC video. To enable
active video, the EACTIVE register bit must be set.
2.2
Important Registers
The default video format is interlaced 8-bit CCIR601 NTSC. Other video formats can
be enabled only by programming the four following registers: 0x53, 00x65, 0x66, and
0x67. Other registers may need to be programmed to get the desired timing of the
synchronization pins; these include HSYNCF[9:0] and HSYNCR[9:0].
2.3
Writing Addresses
Following a start condition, writing to slave address 0x8A initiates access to register
addresses. Alternative slave address 0x88 must be written if the ALTADDR pin is
high.
100138C
02/17/03
Conexant
2-1
Internal Registers
Bt864A/Bt865A Data Sheet
Table 2-2. Register Bit Map
Address(1)
D7
D6
EWSF1
D5
D4
Reserved(2)
D3
D2
D1
D0
A0
EWSF2
WSDAT[1:4]
A2
WSDAT[5:12]
A4
WSDAT[13:20]
A6
SRESET
A8
Reserved(2)
AA
Reserved(2)
AC
TXHS[7:0]
AE
TXHE[7:0]
B0
LUMADLY[1:0]
TXHE[10:8]
B2
Reserved(2)
TXRM
TXE
TXEF2[8]
TXBF2[8]
TXEF1[8]
TXBF1[8]
B4
TXBF1[7:0]
B6
TXEF1[7:0]
B8
TXBF2[7:0]
BA
TXEF2[7:0]
BC
ECCF2
ECCF1
ECCGATE
Reserved(2)
DACOFF
YC16
CBSWAP
PORCH
BE
CCF2B1[7:0]
C0
CCF2B2[7:0]
C2
CCF1B1[7:0]
C4
CCF1B2[7:0]
C6
HSYNCF[7:0]
C8
HSYNCR[7:0]
CA
SYNCDLY
FIELDI
SYNCDIS
ADJHSYNC
HSYNCF[9:8]
CC
SETMODE
SETUPDIS
VIDFORM[3:0]
CE
ESTATUS
RGBO
DCHROMA
D0
Reserved(2)
D2
Reserved(2)
•••
Reserved(2)
FE
Reserved(2)
Reserved(2)
TXHS[10:8]
ECBAR
SCRESET
HSYNCR[9:8]
EVBI
NONINTL
SQUARE
EACTIVE
ECLIP
PAL-N
FOOTNOTE:
(1)
(2)
2-2
All register addresses are hexadecimal.
Must be zero for normal operation. This is the default software reset state.
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
2.4
Internal Registers
Programming Detail
EWSF1
0 = Disable CGMS encoding in field 1.
1 = Enable CGMS encoding in field 1 (line 20).
EWSF2
0 = Disable CGMS encoding in field 2.
1 = Enable CGMS encoding in field 2 (line 283)
WSDAT [1:20]
CGMS data.
SRESET
When set to logical one, this will reset all registers, including itself, to logical zero.
TXHS[10:0]
Relative position of rising edge on the TTXREQ pin.
TXHE[10:0]
Relative position of falling edge on the TTXREQ pin.
LUMADLY[1:0]
This 2-bit value can be used to program the luminance delay on the CVBS/B output.
Bit 1
Bit 0
Function
0
0
No delay
0
1
1 pixel clock delay
1
0
2 pixel clock delay
1
1
3 pixel clock delay
TXRM
0 = REQUEST mode, TTXREQ pin outputs request.
1 = CLOCK mode, TTXREQ pin outputs teletext clock.
TXE
0 = Disable teletext.
1 = Enable teletext.
TXBF1[8:0]
First line of teletext, field one; TXBF1 + 1 = Std. PAL line number.
TXEF1[8:0]
Last line of teletext, field one; TXEF1= Std. PAL line number.
TXBF2[8:0]
First line of teletext, field two; TXBF2 + 313 = Std.
PAL line number.
TXEF2[8:0]
Last line of teletext, field two; TXEF2 + 312 = Std. PAL line number.
ECCF2
0 = Disable closed-caption encoding on field 2.
1 = Enable closed-caption encoding on field 2.
ECCF1
0 = Disable closed-caption encoding on field 1.
1 = Enable closed-caption encoding on field 1.
ECCGATE
0 = Normal closed-caption encoding.
1 = Enable closed-caption encoding constraints. After encoding, future encoding is disabled until a
complete pair of new data bytes is received. This prevents encoding of redundant or incomplete
data.
DACOFF
0 = Normal operation.
1 = Disable DAC output current and internal voltage reference. This will limit power consumption to just
the digital circuits.
NOTE:
YC16
100138C
02/17/03
The DACOFF bit is forced high after power-up until either 8 fields have been output or
register 0x67 (0xCE in 8-bit register address) has been written.
0 = 8-bit mode: YCrCb data is input on P[7:0] as 8-bit multiplexed video.
1 = 16-bit mode: YCrCb data is input on P[7:0] and Y[7:0], where multiplexed CrCb is input on P[7:0].
Conexant
2-3
Internal Registers
Bt864A/Bt865A Data Sheet
CBSWAP
0 = Normal pixel sequence.
1 = The Cb and Cr pixels can be swapped at the input of the pixel port. Refer to the pixel sequence
section for more information.
PORCH
0 = Front and back porch timing conforms to ITU-RBT.470-3. Front porch is 1.5 µs and back porch is
9.4 µs for M-systems or 10.5 µs for PAL-systems. The active video region is therefore smaller than
the 720 pixels specified in CCIR601.
1 = Redefine porch timing per CCIR601. This setting allows the full picture with 720 pixels to be
encoded by using a portion of both the front and back porch for active video.
CCF2B1[7:0]
This is the first byte of closed-caption information for the FIELD 2, line 284 for NTSC or line 335 for
PAL. Data is encoded LSB first.
CCF2B2[7:0]
This is the second byte of closed-caption information for the FIELD 2, line 284 for NTSC or line 335 for
PAL. Data is encoded LSB first.
CCF1B1[7:0]
This is the first byte of closed-caption information for the FIELD 1, line 21 for NTSC or line 22 for PAL.
Data is encoded LSB first.
CCF1B2[7:0]
This is the second byte of closed-caption information for the FIELD 1, line 21 for NTSC or line 22 for
PAL. Data is encoded LSB first.
HSYNCF[9:0]
HSYNCR[9:0]
When ADJHSYNC is enabled, these 10 bit registers can be used to program the placement of the falling
and rising edges of HSYNC* relative to the internal horizontal pixel clock. This variable horizontal timing
mode is available in master mode only. For more detail, see the Pixel Input Timing section.
SYNCDLY
0 = Normal sync timing.
1 = Delayed sync timing.
FIELDI
0 = A “1” on FIELD pin indicates a FIELD 2.
1 = A “1” on FIELD pin indicates a FIELD 1.
SYNCDIS
0 = Normal HSYNC* operation.
1 = Disable HSYNC* edges during VBI (master mode only).
ADJHSYNC
0 = Output hsync pulse on HSYNC*. The standard hsync pulse falls at the start of a new line and
remains low for 4.7 µs.
1 = Output a programmable hsync pulse on HSYNC*. By programming HSYNCR and HSYNCF, HSYNC*
can rise and fall at any desired time during each line.
SETMODE
This bit is ignored in master mode (automatic mode detection is not applicable in slave mode).
0 = By default, in slave mode, the video mode is automatically detected. This is further explained in the
SLAVE mode section.
1 = Override automatic mode-detection in slave mode. The mode will be set according to the
VIDFORM[3:0], NONINTL, and SQUARE register bits.
SETUPDIS
0 = Setup on. The 7.5 IRE setup is enabled for active video lines.
1 = Setup off. The 7.5 IRE setup is disabled.
VIDFORM[3:0]
Configures the device for various worldwide video formats
Bit
2-4
Format
Typical Market
0
NTSC normal
USA/Japan
0
0
PAL-M normal
Brazil
0
0
1
PAL-BDGHIN
W. Europe
1
0
1
PAL-Nc
Argentina
3
2
1
0
0
0
0
1
1
1
1
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
Internal Registers
NONINTL
0 = Interlaced operation.
1 = Noninterlaced operation.
SQUARE
0 = CCIR601 operation.
1 = Square pixel operation.
ESTATUS
0 = The I2C read-back information contains the version number.
1 = The I2C read-back information contains closed-captioning status and field number.
RGBO
0 = Normal operation.
1 = Enable RGB outputs.
The RGBOUT pin is logically ORed with the RGBO register bit.
DCHROMA
0 = Normal operation.
1 = Blank chroma.
ECBAR
0 = Normal operation.
1 = Enable color bars.
SCRESET
0 = Normal operation. The subcarrier phase is reset to zero at the beginning of each color field
sequence.
1 = Disable subcarrier reset event at beginning of field sequence.
EVBI
0 = Video is blanked during the vertical blanking interval.
1 = Enable active video during vertical blanking interval. Setup is added during VBI, if SETUPDIS = 0,
and scaling of YCrCb pixels is always based on 100% blank to white, i.e., normal PAL input scaling.
EACTIVE
0 = Black burst (only if ECBAR = 0).
1 = Enable normal video.
ECLIP
0 = Normal operation.
1 = Enable clipping; DAC values less than 63 are made 63. This limit corresponds to roughly one-fourth
of the sync height.
PAL-N
0 = PAL-BDGHI operation when VIDFORM[3:0] set appropriately.
1 = PAL-N operation when VIDFORM[3:0] set appropriately.
100138C
02/17/03
Conexant
2-5
Internal Registers
2-6
Bt864A/Bt865A Data Sheet
Conexant
100138C
02/17/03
3
PC Board Considerations
A simplified schematic is shown in Figure 3-2. The recommended component values
are listed in Table 3-1.
The layout should be optimized for lowest noise on the power and ground planes by
providing good decoupling. The trace length between groups of VAA and GND pins
should be as short as possible to minimize inductive ringing.
A well-designed power distribution network is critical to eliminating digital switching
noise. The ground plane must provide a low-impedance return path for the digital circuits.
A PC board with a minimum of four layers is recommended, with layers 1 (top) and 4
(bottom) for signals and layers 2 and 3 for ground and power, respectively.
3.1
Component Placement
Components should be placed as close as possible to the associated pin. Whenever
possible, components should be placed so traces can be connected point to point.
The optimum layout enables the Bt864A/Bt865A to be located as close as possible to the
power supply connector and the video output connector.
3.2
Power and Ground Planes
Separate digital and analog power planes are recommended. The digital power plane
should provide power to all digital logic on the PC board, and the analog power plane
should provide power to the VAA power pin, protection diodes, RF modulator, VREF,
VBIAS, and COMP decoupling. There should be at least a 1/8-inch gap between the
digital and analog power planes, connected by a single point through a ferrite bead, as
illustrated in Figure 3-2. The ground plane should be a single unified plane
overlapping both analog and digital power planes. The path back to the power supply
should be with the lowest impedance possible with only one possible return path. This
layout eliminates noise on the analog signals caused by cross-currents from digital
switching.
This bead should be located within 3 inches of the Bt864A/Bt865A. The bead
provides impedance to switching currents, which provides increased impedance at
high frequencies. A low-resistance (<0.5 Ω) bead should be used, such as Ferroxcube
5659065-3B, Fair-Rite 2723021447, or TDK BF45-4001.
100138C
02/17/03
Conexant
3-1
PC Board Considerations
Bt864A/Bt865A Data Sheet
Figure 3-1. Simplified Schematic
VDD
VAA
COMP
VBIAS
L1
Analog Power Plane
C6
VCC
C2
+
C3-C5
C8
C7
VREF
Bt864A/865A
C9
47 µf
C1
Ground
(Power Supply
Connector)
AGND
GND
RSET
FSADJUST
RLOAD
RLOAD
RLOAD
RLOAD
P
CVBS/G
LPF
RF MODULATOR
CVBS/B
Y/CVBS
C/R
P
LPF
P
LPF
To Video
Connector
VAA
Schottky Diodes
To Filter
To Filter
Schottky Diodes
LPF
RF MODULATOR
GND
22 pF
Audio
22 pF
75 Ω
1.8 µH
270 pF
TRAP
1.8 µH
300 pF
270 pF
300 pF
82 Ω
RF
Modulator
ZIN = 1 K(1)
RF
FOOTNOTE: (1) Some modulators may require AC coupling capacitors (10 µF).
100138_030
Table 3-1. Recommended Component Values
Location
Description
Vendor Part Number
C1–C8
0.1 µF Ceramic Capacitor
Erie RPE112Z5U104M50V
C9
47 µF Capacitor
Mallory CSR13F476KM
L1
Ferrite Bead - Surface Mount
Fair-Rite 2743021447
RSET
1% Metal Film Resistor (75 Ω)
Dale CMF-55C
TRAP
Ceramic Resonator
Murata TPSx.xMJ or MB2 (where x.x = sound carrier
frequency in MHz)
Schottky Diodes
BAT85 (BAT54F Dual) HP 5082-2305 (1N6263)
Siemens BAT 64-04 (Dual)
1% Metal Film Resistor (1)
Dale CMF-55C
RLOAD
GENERAL NOTE: The vendor numbers above are listed only as a guide. Substitution of devices with similar characteristics will not
affect the performance of the Bt864A/Bt865A.
FOOTNOTE:
(1)
3-2
Resistor value is typically 75 Ω. Conductance combined with the load equals that of a 37.5 Ω resistor.
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
PC Board Considerations
Figure 3-2. Example Power Plane Layout
CONN
Analog
13
1
864A/865A
Ferrite
Bead
100138_029
3.3
Decoupling
3.3.1
Device Decoupling
For optimum performance, all capacitors should be located as close as possible to the
device, and the shortest possible leads (consistent with reliable operation) should be
used to reduce the lead inductance. Chip capacitors are recommended for minimum
lead inductance. Radial lead ceramic capacitors may be substituted for chip capacitors
and are better than axial lead capacitors for self-resonance. Values are chosen to have
self-resonance above the pixel clock.
3.3.2
Power Supply Decoupling
The best power supply performance is obtained with a 0.1 µF ceramic capacitor
decoupling each group of VDD pins to GND, and the VAA pin to AGND. The
capacitors should be placed as close as possible to the device VAA, VDD, AGND, and
GND pins and connected with short, wide traces.
The 47 µF capacitor shown in Figure 3-1 is for low-frequency power supply ripple;
the 0.1 µF capacitors are for high-frequency power supply noise rejection.
When a linear regulator is used, the power-up sequence must be verified to prevent
latchup. A linear regulator is recommended to filter the analog power supply if the
power supply noise is greater than or equal to 200 mV. This is especially important
when a switching power supply is used, and the switching frequency is close to the
raster scan frequency. About 5% of the power supply hum and ripple noise less than
1 MHz will couple onto the analog outputs.
3.3.3
COMP Decoupling
The COMP pin must be decoupled to the VAA pin, typically with a 0.1 µF ceramic
capacitor. Low-frequency supply noise will require a larger value. The COMP capacitor
must be as close as possible to the COMP and the VAA pin. A surface-mount ceramic chip
capacitor is preferred for minimal lead inductance. Lead inductance degrades the noise
rejection of the circuit. Short, wide traces will also reduce lead inductance.
100138C
02/17/03
Conexant
3-3
PC Board Considerations
3.3.4
Bt864A/Bt865A Data Sheet
VREF Decoupling
A 0.1 µF ceramic capacitor should be used to decouple this pin to AGND.
3.3.5
VBIAS Decoupling
A 0.1 µF ceramic capacitor should be used to decouple this pin to AGND.
3.4
Signal Interconnect
3.4.1
Digital Signal Interconnect
The digital inputs to the Bt864A/Bt865A should be isolated as much as possible from
the analog outputs and other analog circuitry. Also, these input signals should not
overlay the analog power plane or analog output signals.
Most of the noise on the analog outputs will be caused by excessive edge rates (less
than 3 ns), overshoot, undershoot, and ringing on the digital inputs.
The digital edge rates should not be faster than necessary, as feed through noise is
proportional to the digital edge rates. Lower-speed applications will benefit from
using lower-speed logic (3–5 ns edge rates) to reduce data-related noise on the analog
outputs.
Transmission lines will mismatch if the lines do not match the source and destination
impedance. This will degrade signal fidelity if the line length reflection time is greater
than one-fourth the signal edge time. Line termination or line-length reduction is the
solution. For example, logic edge rates of 2 ns require line lengths of less than 4
inches without use of termination. Ringing may be reduced by damping the line with a
series resistor (30–300 Ω).
Radiation of digital signals can also be picked up by the analog circuitry. This is
prevented by reducing the digital edge rates (rise/fall time), minimizing ringing with
damping resistors, and minimizing coupling through PC board capacitance by routing
the digital signals at a 90 degree angle to any analog signals.
The clock driver and all other digital devices must be adequately decoupled to prevent
digital noise from coupling into the analog circuitry.
3-4
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
3.4.2
PC Board Considerations
Analog Signal Interconnect
The Bt864A/Bt865A should be located as close as possible to the output connectors to
minimize noise pickup and reflections caused by impedance mismatch.
The analog outputs are susceptible to crosstalk from digital lines; digital traces must
not be routed under or adjacent to the analog output traces.
To maximize the high-frequency power supply rejection, the video output signals
should overlay the ground plane.
For maximum performance, the analog video output impedance, cable impedance,
and load impedance should be the same. The load resistor connection between the
video outputs and AGND should be as close as possible to the Bt864A/Bt865A to
minimize reflections. Unused DAC outputs should be connected to AGND unless the
power-down feature is being utilized.
3.5
Applications Information
3.5.1
ESD and Latchup Considerations
Correct ESD-sensitive handling procedures are required to prevent device damage.
Device damage can produce symptoms of catastrophic failure or erratic device
behavior with leaky inputs.
All logic inputs should be held low until power to the device has settled to the
specified tolerance. DAC power decoupling networks with large time constants should
be avoided; they could delay VAA power to the device. Ferrite beads must be used
only for analog power VAA decoupling. Inductors cause a time constant delay that
induces latchup.
Latchup can be prevented by ensuring that all VAA and VDD pins are at the same
potential, all GND and AGND pins are at the same potential, and that the VAA and
VDD supply voltages are applied before the signal pin voltages. The correct power-up
sequence ensures that any signal pin voltage will never exceed the power supply
voltage.
3.5.2
Clock and Subcarrier Stability
The color subcarrier is derived directly from the CLK input, hence any jitter or
frequency deviation of CLK will be transferred directly to the color subcarrier. Jitter
within the valid CLK cycle interval will result in hue noise on the color subcarrier on
the order of 0.9–1.6 degrees per nanosecond. Random hue noise can result in
degradation in AM/PM noise ratio (typically around 40 dB for consumer media such
as Videodiscs and VCRs). Periodic or coherent hue noise can result in differential
phase error (which is limited to 10 degrees by FCC cable TV standards). Any
frequency deviation of the CLK from nominal will challenge the subcarrier tracking
capability of the destination receiver. This may range from a few parts-per-million
(ppm) for broadcast equipment to 50 ppm for industrial equipment to a few hundred
ppm for consumer equipment. Greater subcarrier tracking range generally results in
poorer subcarrier decoding dynamic range, so that receivers that tolerate jitter and
wide subcarrier frequency deviation will introduce more noise in the decoded image.
Crystal clock sources provide best stability and lowest jitter, with 50–100 ppm
100138C
02/17/03
Conexant
3-5
PC Board Considerations
Bt864A/Bt865A Data Sheet
accuracy required by most industrial or consumer receivors. Note that a 30 ppm
tolerance constraint applies for Teletext and MPEG2.
Some applications call for maintaining correct Subcarrier-Horizontal (SC-H) phasing
for correct color framing, which requires subcarrier coherence within specified
tolerances over a 4-field interval for 525-line systems or 8 fields for 625-line systems.
Any CLK interruption (even during vertical blanking interval) which results in
nonstandard pixel counts per line can result in SC-H excursions outside the NTSC
limit of ±40 degrees (reference EIA RS170A) or the PAL limit of ±20 degrees
(reference EBU D23-1984).
Any deviation of the number CLK cycles between HSYNC* falling edges when in
SLAVE mode may result in automatic mode switching unless the internal control
registers VIDFORM, NONINTL and SQUARE are set for the desired mode of
operation.
3.5.3
Mutual Inductance Concerns
The designer should prevent a situation where signals from other devices next to the
encoder cause the crystal to generate faulty clocks.
The Conexant encoder and any associated crystal that drives the CLK input should
physically be placed as far as possible from signal lines with excessive currents.
Excessive currents are defined to be greater than the Total Supply Current figure
listed in Table 4-3.
In some systems, there are signal lines for controlling motors, LEDs, and thermal
heads. When a large current flows through these traces problematic noise can result
from the phenomenon of mutual inductance (See Figure 3-3).
Figure 3-3. Example of Mutual Inductance
Large Current
M
CLK
GND
100138_031
3-6
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
3.5.4
PC Board Considerations
Reset Precautions
The user should make the length of the traces connected to the RESET* input pin as
short as possible. In addition, Conexant recommends that a 0.1 µF capacitor be
connected across the RESET* input pin and the digital ground pins (GND) for
decoupling purposes.
All of Bt864A/Bt865A’s programmable register bits can be reset through software
(i.e., setting register bit SRESET= 1). Furthermore, both the Bt864A/Bt865A’s
registers and timing can be reset by a low pulse of at least 0.05 µs (>1 complete period
of CLK) input directly to RESET*. If noise, having a pulse width close to 0.05 µs, is
inadvertently input to RESET*, it could cause the encoder to unintentionally reset the
subcarrier phase and/or the horizontal and vertical counters (see Figure 1-9). This
type of timing error could cause faulty system operation (see Figure 3-4).
Figure 3-4. Wiring for the Reset Input Pin
Short as Possible
RESET*
0.1 µF
GND
100138_032
3.5.5
Filtering RF Modulator Connection
The Bt864A/Bt865A internal upsampling filter alleviates external filtering
requirements by moving significant sampling alias components above 19 MHz and
reducing the sinx/x aperture loss up to the filter’s passband cutoff of 5.75 MHz. While
typical chrominance subcarrier decoders can handle the Bt864A/Bt865A output
signals without analog filtering, the higher frequency alias products pose some EMI
concerns and may create troublesome images when introduced to an RF modulator.
When the video is presented to an RF modulator, it should be free of energy in the
region of the aural subcarrier (4.5 MHz for NTSC, 5.5–6.5 MHz for PAL), hence
some additional frequency traps may be necessary when the video signal contains
fundamental or harmonic energy (as from unfiltered character generators) in that
region. For example, a pixel rate of 13.5 msps is three times the NTSC-M aural carrier
of 4.5 MHz, hence significant harmonic energy can fall on the FM aural carrier for
character cell sizes which are multiples of three. Where better frequency response
flatness is required, some peaking in the analog filter is appropriate to compensate for
residual digital filter losses with sufficient margin to tolerate 10% reactive
components.
A three-pole elliptic filter (1 inductor, 3 capacitors) with a 6.75 MHz passband can
provide at least 45 dB attenuation (including sinx/x loss) of frequency components
above 20 MHz and provide some flexibility for mild peaking or special traps. An
inductor value with a self-resonant frequency above 80 MHz is chosen so that its
intrinsic capacitance contributes less than 10% of the total effective circuit value. The
100138C
02/17/03
Conexant
3-7
PC Board Considerations
Bt864A/Bt865A Data Sheet
inductor itself may induce 1% (0.1 dB) loss, and worst case subcarrier attenuation
(including sinx/x loss) may be 7% with 10% tolerance reactive components. Any
additional ferrites introduced for EMI control after termination should have less than
5 Ω impedance below 5 MHz to minimize additional losses. The capacitor to ground
at the Bt864A/Bt865A output pin is compensated for the parasitic capacitance of the
chip plus any protection diodes and lumped circuit traces (about 22 pF+5 pF/diode).
Some filter peaking can be accomplished by splitting the source impedance across the
reactive PI filter network. However, this will also introduce some chrominanceluminance delay distortion in the range of 10–20 ns for a maximum of 0.5 dB boost at
the subcarrier frequency.
The filter network feeding an RF modulator may include the aforementioned trap,
which could take two forms depending on the depth of attenuation and type of
resonator device employed. The RF modulator typically has a high input impedance
(about 1 KΩ ± 30%) and loose tolerance. Consequently, the amplitude variation at the
modulator input will be greater, especially when the trap is properly terminated at the
modulator input for maximum effect. Some modulators video or aural fidelity will
degrade dramatically when overdriven, so the value of the effective termination
(nominally 37.5 Ω) may need to be adjusted downward to maintain sufficient linearity
(or depth of modulation margin) in the RF signal. Where required to maintain better
than 40 dB audio dynamic range in the presence of video energy in the region of the
aural carrier, a two section trap with more than 20 dB attenuation may be warranted.
Best gain flatness versus frequency and luma-chroma delay match can be obtained by
active buffering and use of the variable luma delay on CVBS/B channel. See
Figure 3-1.
3.5.6
Luminance Delay on CVBS/B
Postfiltering of the video signal can introduce a variable delay between the lower
frequency luminance components and the higher frequency chrominance subcarrier
components. The group delay distortion is often specified in system as chroma-luma
delay inequality or as Sinx/x pulse group delay. Group delay distortion is commonly
induced by postfilters which peak the chrominance level, by trap circuits intended to
reduce video energy in the aural subcarrier frequency range, and by Vestigial
Sideband (VSB) filtering in RF tuners. Since oversampling encoders greatly reduce
the need for peaking filters, delay compensation of the luminance signal largely
benefits the channel through the RF modulation and tuner path where group delay
distortion can amount to several hundred nanoseconds or several pixels of
misregistration.
While flat group delay correction as observed from a Sinx/x pulse spectrum can
require several LC stages with active buffers, a simplified approach where only lumachroma delay must be equalized is to shift the luminance signal through pipeline
delays to match any additional group delay induced on the chrominance components
by postfiltering. This alignment of the lower frequency luminance components with
the chrominance components does not strictly satisfy broadcast quality requirements
but provides perceptible improvements in display registration.
While VSB delays are prescribed in ITU-R BT.470-3 as about 170 ns, the luminance
delay compensation for postfilter aural traps depends on the attenuation required at
the aural carrier frequency. In the case of NTSC signals sampled at CCIR601
resolution, the coincidence of the aural carrier (4.5 MHz) at one third of the sample
rate means that any video component which transitions at intervals of every third pixel
3-8
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
PC Board Considerations
clock can generate significant energy at the aural carrier frequency. In the case of
hard-edged, unblended characters having a font cell size which is a multiple of three
pixels, harmonic energy at the aural carrier frequency may be only 15 dB below the
maximum video level, or roughly equal to the power of the sound subcarrier in the RF
spectrum.
Trap attenuation of about 20 dB can assure that the resultant interference with the FM
aural signal will degrade the noise level at the monaural decoded receiver about 1 dB
(–44 dB range) with less than 50 ns additional chroma delay [Multichannel stereo
(e.g., BTSC) or Second Audio Program (SAP) encoder may require greater
attenuation due to lower level subcarriers]. Therefore, luminance delay compensation
of about 225 ns on just the RF feed (e.g. CVBS/B) can correct for the chroma delay
artifacts of additional processing in the RF channel without compromising the
inherently low group delay distortion of the baseband channels (e.g. CVBS/Y/C).
3.6
I2C Programming
3.6.1
Data Transfer on the I2C Bus
An I2C reference manual has been developed and may be obtained upon request. This
provides farther information on I2C bus protocol. Figure 3-5 shows the relationship
between SDA and SCL to be used when programming the I2C bus. If the bus is not
being used, both SDA and SCL lines must be left high.
Figure 3-5. I2C Diagram
Subsequent Bytes and Acknowledge
Interpreted as Data Values for
Autoincremented Subaddress Locations
SCL
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
(1)
Main Address
(1)
Subaddress
(1)
Data
Stop Condition
Start Condition
MSB
SDA
2
LSB
1
Footnote:
(1) Acknowledge generated by Bt864A/865A.
100138_033
Every byte put onto the SDA line should be 8 bits long (MSB first), followed by an
acknowledge bit, which is generated by the receiving device.
Each data transfer is initiated with a start condition and ended with a stop condition.
The first byte after a start condition is always the address byte. If this is the device’s
own address, the device will generate an acknowledge by pulling the SDA line low
100138C
02/17/03
Conexant
3-9
PC Board Considerations
Bt864A/Bt865A Data Sheet
during the ninth clock pulse, then accept the data in subsequent bytes
(autoincrementing the register address) until another stop condition is detected.
Bit 8 of the address byte is the read/write bit (high = read from addressed device, low
= write to the addressed device) so, for the Bt864A/Bt865A, the address is only
considered valid if the R/W bit is low.
Data bytes are always acknowledged during the ninth clock pulse by the addressed
device. Note that during the acknowledge period the transmitting device must leave
the SDA line high.
Premature termination of the data transfer is allowed by generating a stop condition at
any time. When this happens, the Bt864A/Bt865A will remain in the state defined by
the last complete data byte transmitted. Any master acknowledge subsequent to
reading the chip ID is ignored.
3-10
Conexant
100138C
02/17/03
4
Parametric Information
4.1
DC Electrical Parameters
Table 4-1. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
5V
4.75
5.00
5.25
V
3.3V
3.0
3.3
3.6
V
Ambient Operating Temperature
TA
0
70
°C
DAC Output Load
RL
37.5
Ω
RSET
75
Ω
Power Supply (VAA and VDD)
Nominal RSET
Table 4-2. Absolute Maximum Ratings
Parameter
Symbol
Min
Typ
VAA and VDD (measured to GND)
Voltage on Any Signal Pin (1)
GND –0.5
Max
Units
7.0
V
VAA or
VDD + 0.5
V
+150
°C
Analog Output Short Circuit Duration to
Any Power Supply or Common
ISC
Storage Temperature
TS
Junction Temperature
TJ
+125
°C
TVSOL
220
°C
Vapor Phase Soldering (1 Minute)
Indefinite
–65
GENERAL NOTE: Stresses above those listed in this table (“Absolute Maximum Ratings”) may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at these or any other conditions above
those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
FOOTNOTE:
(1)
This device employs high-impedance CMOS structures on all signal pins. It should be handled as an ESD-sensitive device.
Voltage on any signal pin that exceeds the power supply or ground voltage by more than 0.5 V can cause destructive latchup.
100138C
02/17/03
Conexant
4-1
Parametric Information
Bt864A/Bt865A Data Sheet
Table 4-3. DC Characteristics (VDD = 5 V)
Parameter
Symbol
Video D/A Resolution
Min
Typ
Max
Units
10
10
10
Bits
Output Current-DAC Code 1023 (Iout FS)
34.13
mA
Output Voltage-DAC Code 1023
1.28
V
Video Level Error (Nominal Resistors)
5
Output Capacitance
22
%
pF
Digital Inputs (Except those specified below)
Input High Voltage
VIH
2.0
VDD + 0.5
V
Input Low Voltage
VIL
GND –0.5
0.8
V
Input High Current (Vin = 2.4 V)
IIH
1
µA
Input Low Current (Vin = 0.4 V)
IIL
–1
µA
Input Capacitance (f = 1 MHz, Vin = 2.4 V)
CIN
7
pF
SCL, SDA
Input High Voltage
VIH
0.7 x VDD
VDD + 0.5
V
Input Low Voltage
VIL
GND –0.5
0.3 x VDD
V
Input High Voltage
VIH
2.4
VDD + 0.5
V
Input Low Voltage
VIL
GND –0.5
0.8
V
Output High Voltage (IOH = –400 µA)
VOH
2.4
Output Low Voltage (IOL = 3.2 mA)
VOL
0.4
V
Three-State Current
IOZ
50
µA
Output Capacitance
CDOUT
CLK Input
Digital Outputs
V
10
pF
GENERAL NOTE: “Recommended Operating Conditions,” NTSC CCIR 601 operation, and CLK frequency = 27 MHz. As the above
parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required.
Typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 5 V or 3.3 V.
4-2
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
4.2
Parametric Information
AC Electrical Parameters
Table 4-4. AC Characteristics (VDD = 5 V, VAA = 5 V) (1 of 2)
EIA/TIA
Parameter
250C Ref
CCIR
567
Symbol
Min
Typ
Max
Units
Hue Accuracy(3)
X(1)
X(2)
1
2.5
±°
Color Amplitude Accuracy(3)
X(1)
X(2)
1
2.3
±%
Chroma AM/PM Noise(4)
1 MHz
Red Field
–64
6.2.2.1
Differential Gain(3)
1
C3.4.1.3
dB rms
2
1.5
6.2.2.2
0.5
% p–p
2.2
Differential Phase(3)
C3.4.1.3
SNR (unweighted 100 IRE Y Ramp Tilt
% p–p
° p–p
0.45
° p–p
Correct)(3)
RMS (5 MHz Bandwidth)
6.3.1
–62
dB rms
Peak Periodic
6.3.2
–60
dB p–p
6.1.1
–2.3
–3
± IRE
C3.5.4.1
–0.5
–0.8
dB
6.1.2.2
C3.5.3.1
–2
–2.5
± IRE
6.1.2.2
C3.5.3.1
–2.5
6.1.2
C3.5.3.2
0
10
ns
Short Time Distortion 100IRE/PIXEL(4)
6.1.6
C3.5.1.4
2.3
3
%
Nonlinearity(3)
6.2.1
0.5
6.2.3
0.2
100 IRE Multiburst (4.0 MHz
Packet)(4)
Gain/frequency (4.8 MHz Packet)
Chroma/Luma Gain Ineq(4)
5.0 V
3.3 V
Chroma/Luma Delay
Luminance
Ineq(4)
Chroma/Luma Intermod(3)
C3.4.1.4
Chroma Nonlinear Gain(3)
Chroma Nonlinear
Phase(3)
0.8
± IRE
± IRE
2
± IRE
6.2.4.2
0.2
2
±°
1
7
ns
2
3
ns
(5)
5.0 V
3.3 V
Control Output Hold
22
0.2
Time(5)
Control Output Delay Time
%
6.2.4.1
Pixel/Control Setup Time(5)
Pixel/Control Hold
± IRE
Time(5)
3
17
ns
3
35
ns
4
CLK Frequency
4
24.54
ns
27
29.5
MHz
CLK Pulse Width Low Time
8
ns
CLK Pulse Width High Time
8
ns
100138C
02/17/03
Conexant
4-3
Parametric Information
Bt864A/Bt865A Data Sheet
Table 4-4. AC Characteristics (VDD = 5 V, VAA = 5 V) (2 of 2)
Parameter
EIA/TIA
250C Ref
CCIR
567
Symbol
Min
Typ
Max
Units
Pipeline Delay
Input Pixels to Composite Video
52
CLK periods
Input Pixels to RGB Output
52
CLK periods
180
mA
5.0 V
50
mA
3.3 V
30
mA
5.0 V
230
mA
3.3 V
210
mA
VAA Supply Current (SLEEP = 1)(6)
1
mA
VDD Supply Current (SLEEP = 1)(6)
1
mA
VAA Supply Current (DAC off =1)
1
mA
VDD Supply Current (DAC off =1)
50
mA
VAA Supply Current
VDD Supply Current
Total Supply Current
Power-Down Mode Currents
GENERAL NOTE: “Recommended Operating Conditions,” NTSC CCIR 601 operation, and CLK frequency = 27 MHz. Analog output
load = 75 pF. HSYNC*, VSYNC*, BLANK*, and FIELD output loads = 75 pF. As the above parameters are
guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values
are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 5 V. Video input and output
timing is shown in Figure 4-1.
FOOTNOTE:
(1)
(2)
(3)
(4)
(5)
(6)
4-4
75/7.5/75/7.5 Color bars normalized to burst.
100/0/100/0 Colorbars normalized to burst.
Guaranteed by characterization.
Without post filter. Guaranteed by design.
Control pins are defined as: P[7:0], Y[7:0],BLANK*, HSYNC*, VSYNC*, FIELD, TTXREQ, TTXDAT.
All digital inputs at GND or VDD.
Conexant
100138C
02/17/03
Bt864A/Bt865A Data Sheet
Parametric Information
Figure 4-1. YCrCb Video Input and Output Timing
CLK
P[7:0], Y[7:0]
16-Bit Mode, BLANK*,
HSYNC*, VSYNC*
1
2
P[7:0] 8-Bit Mode,
TTXDAT
1
2
2.4
.8
TTXREQ
4
3
2.4
.8
HSYNC*, VSYNC*
FIELD (Output)
4
3
CVBS/B, CVBS/G,
Y/CVBS, C/R
Pipeline
100138_034
100138C
02/17/03
Conexant
4-5
Parametric Information
Bt864A/Bt865A Data Sheet
Figure 4-2. 52-Pin Metric Quad Flatpack (MQFP)
D
D1
D2
E
E1
E2
e
b
See Detail A
TOP VIEW
BOTTOM VIEW
All Dimensions in
Millimeters
Dim.
SIDE VIEW
Min.
Nom.
Max.
A
----
----
2.45
A1
0.102
----
----
A2
1.95
2.00
2.05
D
17.05
17.20
17.35
D1
13.95
14.00
14.05
D2
A
A2
12.00 REF.
E
17.05
17.20
17.35
E1
13.95
14.00
14.05
E2
L
A1
DETAIL A
L
1.60 REF.
12.00 REF.
0.70
0.80
e
1.00 BSC.
b
0.35 REF.
0.90
100138_035
4-6
Conexant
100138C
02/17/03
www.conexant.com
General Information:
U.S. and Canada: (800) 854-8099
International: (949) 483-6996
Headquarters – Newport Beach
4311 Jamboree Rd.
Newport Beach, CA. 92660-3007