53'53'DQG53' /RZ9ROWDJH9.IOH[99ELV 0RGHP'DWD3XPSVIRU'HVNWRS$SSOLFDWLRQV Introduction The CONEXANT RP56D, RP336D, and RP144D Modem Data Pump (MDP) families support data/fax modem, voice coding/decoding, optional full-duplex speakerphone, and optional AudioSpan (Table 1). Low voltage and small size support desktop applications. Downloadable architecture allows upgrading of MDP code from the host/DTE. In V.90/K56flex mode (RP56), the MDP can receive data at speeds up to 56 kbps from a digitally connected V.90or K56flex-compatible central site modem. These MDPs take advantage of the PSTN which is primarily digital except for the client modem to central office local loop and are ideal for applications such as remote access to an Internet service provider (ISP), on-line service, or corporate site. The MDP can send upstream data at speeds up to V.34 rates. In V.34 data mode (RP56 and RC336), the MDP can connect at the highest data rate the channel can support from 33.6 kbps to 2400 bps with auto-fallback to V.32 bis. In V.32 bis mode, the MDP can connect at the highest data rate the channel can support from 14.4 kbps to 4800 bps with optional auto-fallback to lower rate modulations. Internal HDLC support eliminates the need for an external serial input/output (SIO) device in the DTE for products incorporating error correction and T.30 protocols. Voice mode includes an Adaptive Differential Pulse Code Modulation (ADPCM) voice coder and decoder (codec). The codec compresses and decompresses voice signals for efficient digital storage of voice messages. The codec operates at 28.8k, 21.6k, or 14.4k bps (4-bit, 3-bit, or 2-bit quantization, respectively) with a 7.2 kHz or 8.0 kHz sample rate. A voice pass-through mode allows the host to transmit and receive uncompressed voice samples in 16-bit linear form at 7.2 kHz, 8.0 kHz, or 11.025 kHz sample rate, or in 8-bit A-Law/µ-Law PCM form at 8.0 kHz sample rate. SP models support position-independent full-duplex speakerphone (FDSP) operation using a dual internal integrated analog circuit to interface with the telephone line and the audio input/out (i.e., a headset, handset, or a microphone with external speaker). SP models also support AudioSpan (analog simultaneous audio/voice and data) operation at a data rate of 4.8 kbps. The MDP operates over the public switched telephone network (PSTN) through the appropriate line termination. 'DWD 6KHHW Features • Downloadable MDP code from the host/DTE • 2-wire full-duplex − V.90 and K56flex (RP56 models) − V.34 (33.6 kbps) (RP56 and RP336 models) − V.32 bis, V.32, V.22 bis, V.22, V.23, and V.21 − Bell 212 and 103 • 2-wire half-duplex − V.34 fax, V.17, V.33, V.29, V.27 ter, and V.21 ch 2 − Bell 208 − Short train option in V.17 and V.27 ter • Serial synchronous and asynchronous data • Parallel synchronous and asynchronous data • Parallel synchronous SDLC/HDLC support • In-band secondary channel (V.34 and V.32 bis) • Automatic mode selection (AMS) • Automatic rate adaption (ARA) • Digital near-end and far-end echo cancellation • Bulk delay for satellite transmission • ADPCM voice mode (7.2 kHz or 8.0 kHz) • Voice pass-through mode (7.2 kHz, 8.0 kHz, or 11.025 kHz) • Full-duplex speakerphone (SP models) − Acoustic and line echo cancellation − Programmable microphone AGC − Microphone volume selection and muting − Speaker volume control and muting; room monitor • AudioSpan (SP models) − ITU-T V.61 modulation (4.8 kbps data plus audio) − Handset, headset, or half-duplex speakerphone • TTL and CMOS compatible DTE interface − ITU-T V.24 (EIA/TIA-232-E) (data/control) − Microprocessor bus (data/configuration/control) • Dynamic range: -9 dBm to -43 dBm • Adjustable speaker output to monitor received signal • DMA support interrupt lines • Transmit and receive (16+128)-byte FIFO data buffers • NRZI encoding/decoding • 511 pattern generation/detection • V.8 and V.8 bis signaling • V.13 signaling • Diagnostic capability − V.54 inter-DCE signaling − V.54 local analog and remote digital loopback • +3.3V operation with +5V tolerant inputs − +5V analog operation • Power consumption: − Normal Mode = 280 mW; Sleep Mode = 53 mW • Low profile, small footprint package − 100-pin PQFP 2UGHU 1R 0' 5HY 'HFHPEHU 53'53'DQG53' /RZ9ROWDJH9.IOH[99ELV0RGHP'DWD3XPSV 7DEOH 0RGHP 0RGHOV DQG )XQFWLRQV 0RGHP3DUW 1XPEHU 0RGHO 1XPEHU 3DUW 1R 3DFNDJH DQG 3DFNDJH 2SWLRQV 3DFNDJH &ORFN&U\VWDO $QDORJ ,QSXW ,QWHUIDFH 9ROWDJH 6XSSRUWHG )XQFWLRQV 9.IOH[ 9 'DWD 9 ELV 'DWD )'63 'DWD 9 )D[ $XGLR6SDQ 5HPRWH 9RLFH 9RLFH 6HULDO ,QWHUIDFH 53'63 5 3LQ 34)3 &ORFN 9 < < < < ± 53' 5 3LQ 34)3 &ORFN 9 < < < ± ± 53'63 5 3LQ 34)3 &ORFN 9 ± < < < ± 53' 5 3LQ 34)3 &ORFN 9 ± < < ± ± 53'63 5 3LQ 34)3 &ORFN 9 ± ± < < ± 53' 5 3LQ 34)3 &ORFN 9 ± ± < ± ± 1RWHV 0RGHOSDUW QXPEHU RSWLRQV ' 'RZQORDGDEOH 63 6SHDNHUSKRQH 6XSSRUWHG IXQFWLRQV < )'63 6XSSRUWHG ± 1RW VXSSRUWHG )XOOGXSOH[ VSHDNHUSKRQH 5HPRWH 9RLFH 5HPRWH YRLFH UHFRUG DQG SOD\EDFN $XGLR6SDQ $QDORJ VLPXOWDQHRXV YRLFH DQG GDWD Information provided by CONEXANT SYSTEMS, INC. (CONEXANT) is believed to be accurate and reliable. However, no responsibility is assumed by CONEXANT for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of CONEXANT other than for circuitry embodied in CONEXANT products. CONEXANT reserves the right to change circuitry at any time without notice. This document is subject to change without notice. K56flex is a trademark of CONEXANT SYSTEMS, INC. and Lucent Technologies. CONEXANT and “What's Next in Communications Technologies” are trademarks of CONEXANT SYSTEMS, INC. ©1998, CONEXANT SYSTEMS, INC. Printed in U.S.A. All Rights Reserved 0' /RZ9ROWDJH9.IOH[99ELV0RGHP'DWD3XPSV 53'53'DQG53' Technical Description The MDP functional interface is illustrated in Figure 1. Configurations and Rates The selectable MDP configurations, signaling rates, and data rates are listed in Table 2. CLKIN CLOCK CIRCUIT ~RDCLK TDCLK XTCLK TXD V.24 SERIAL DTE INTERFACE RXD ~RLYA ~RTS ~RLYB ~CTS RINGD ~DTR RIN MODEM DATA PUMP (MDP) R6764:100-PIN PQFP] ~DSR ~RLSD ~RI RXA TXA TXA1 TXA2 MICM SPK TELEPHONE LINE/ TELIN TELEPHONE/ TELEPHONE AUDIO INTERFACE TELOUT LINE INTERFACE SPKMD ~READ ~WRITE DATA BUS (8) D0-D7 ADDRESS BUS (5) A0-A4 HOST PROCESSOR DECODER TELEPHONE LINE MIC MICV/NC* SPKR TELIN/NC* MIC/ SPEAKER TELOUT/NC* RS0-RS4 VGG (+5V ) ~CS VCC (+3.3V) IRQ ~RESET VAA (+5V) AGND POWER SUPPLY DGND * PINS ARE INTERNAL NO CONNECT (NC) ON NON-SP MODELS. MD218F1 FID )LJXUH 0'3 )XQFWLRQDO ,QWHUIDFH 0' 53'53'DQG53' /RZ9ROWDJH9.IOH[99ELV0RGHP'DWD3XPSV 7DEOH &RQILJXUDWLRQV 6LJQDOLQJ 5DWHV DQG 'DWD 5DWHV &RQILJXUDWLRQ 0RGXODWLRQ &DUULHU )UHTXHQF\ +] 'DWD 5DWH ESV V.90/K56flex PCM* PCM – V.34 33600 TCM** V.34 31200 TCM** V.34 28800 TCM** V.34 26400 TCM** V.34 24000 TCM** V.34 21600 TCM** V.34 19200 TCM** V.34 16800 TCM** V.34 14400 TCM** V.34 12000 TCM** V.34 9600 TCM** V.34 7200 TCM** V.34 4800 TCM** V.34 2400 TCM** V.32 bis 14400 TCM V.32 bis 12000 TCM V.32 bis 9600 TCM V.32 bis 7200 TCM V.32 bis 4800 V.32 9600 TCM V.32 9600 V.32 4800 V.22 bis 2400 V.22 bis 1200 V.22 1200 V.22 600 V.23 1200/75 V.21 Bell 208 4800 Bell 212A Bell 103 V.23 1200/75 V.21 TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM QAM TCM QAM QAM QAM DPSK DPSK DPSK FSK FSK DPSK DPSK FSK FSK FSK TCM Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 1800 1800 1800 1800 1800 1800 1800 1800 1200/2400 1200/2400 1200/2400 1200/2400 1700/420 1080/1750 1800 1200/2400 1170/2125 1700/420 1080/1750 1800 56000R/V.34ratesT4 33600 31200 28800 26400 24000 21600 19200 16800 14400 12000 9600 7200 4800 2400 14400 12000 9600 7200 4800 9600 9600 4800 2400 1200 1200 600 1200/75 0–300 4800 1200 0–300 1200/75 0–300 14400 V.17 14400 TCM/V.333 V.17 12000 TCM/V.333 6\PERO 5DWH %LWV6\PERO %LWV6\PERO 6\PEROV6HF 'DWD 7&0 &RQVWHOODWLRQ 3RLQWV 8000 Dynamic – – Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 2400 2400 2400 2400 2400 2400 2400 2400 600 600 600 600 1200 300 1600 600 300 1200 300 2400 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 6 5 4 3 2 4 4 2 4 2 2 1 1 1 3 2 1 1 1 6 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 128 64 32 16 4 32 16 4 16 4 4 4 – – 8 4 – – – 128 TCM 1800 12000 2400 5 1 64 V.17 9600 TCM3 V.17 7200 TCM3 TCM 1800 9600 2400 4 1 32 TCM 1800 7200 2400 3 1 16 V.29 96003 V.29 72003 QAM 1700 9600 2400 4 0 16 QAM 1700 7200 2400 3 0 8 V.29 48003 V.27 48003 QAM 1700 4800 2400 2 0 4 DPSK 1800 4800 1600 3 0 8 V.27 24003 DPSK 1800 2400 1200 2 0 4 FSK 1750 300 300 1 0 – – – – – – – V.21 Channel 23 Tone Transmit – Notes: 1. Modulation legend: TCM: Trellis-Coded Modulation FSK: Frequency Shift Keying 2. Adaptive; established during handshake: 6\PERO 5DWH %DXG QAM: Quadrature Amplitude Modulation DPSK: Differential Phase Shift Keying &DUULHU )UHTXHQF\ +] 9 /RZ &DUULHU 9 +LJK &DUULHU 3. Models with fax support only. 4. Maximum data rate. * RP56 models only. ** RP56 and RP336 models only. 0' /RZ9ROWDJH9.IOH[99ELV0RGHP'DWD3XPSV 53'53'DQG53' 7DEOH 576&76 5HVSRQVH 7LPHV Automatic Mode Selection When automatic mode selection (AMS) is enabled, the MDP configures itself to the highest compatible data rate supported by the remote modem (AUTO bit). Automode operation is supported in V.90, K56flex, V.34, V.32 bis, V.32 V.22 bis, V.22, V.21, V.23, Bell 212A, and Bell 103 modes. Automatic Rate Adaption (ARA) In V.90, K56flex, V.34, and V.32 bis modes, automatic rate adaption (ARA) can be enabled to select the highest data rate possible based on the measured eye quality monitor (EQM) (EARC bit). This selection occurs during handshake/retrain and rate renegotiation. Tone Generation The MDP can generate single or dual voice-band tones from 0 Hz to 3600 Hz with a resolution of 0.15 Hz and an accuracy of ± 0.01%. Tones over 3000 Hz are attenuated. DTMF tone generation allows the MDP to operate as a programmable DTMF dialer. Data Encoding The data encoding conforms to ITU-T recommendations V.90, V.34, V.32 bis, V.32, V.17, V.33, V.29, V.27 ter, V.22 bis, V.22, V.23, or V.21, and is compatible with Bell 208, 212A, or 103, depending on the model and selected configuration. RTS - CTS Response Time The response times of CTS relative to a corresponding transition of RTS are listed in Table 3. Transmit Level The transmitter output level is selectable from 0 dBm to -15 dBm (VAA = +5V) in 1 dB steps and is accurate to ±0.5 dB when used with an external hybrid. The output level can also be fine tuned by changing a gain constant in MDP DSP RAM. The maximum V.34/V.32 bis/V.32 transmit level for acceptable receive performance should not exceed -9 dBm. Note: In V.34 mode, the transmit level may be automatically changed during the handshake. This automatic adjustment of the transmit level may be disabled via a parameter in DSP RAM. Transmitter Timing RTS-CTS Response1 Constant Carrier Controlled Carrier Turn-Off Sequence3 ± 2 ms N/A N/A V.33/V.17 Long N/A 1393 ms2 15 ms4 V.33/V.17 Short N/A 142 ms2 15 ms4 V.29 N/A 253 ms2 12 ms V.27 4800 Long N/A 708 ms2 7 ms4 V.27 4800 Short N/A 50 ms2 7 ms4 V.27 2400 Long N/A 943 ms2 10 ms4 V.27 2400 Short N/A 67 ms2 10 ms4 ± 2 ms 270 ms N/A Configuration V.90, K56flex, V.34, V.32 bis, V.32 V.22 bis, V.22, Bell 212A V.21 500 ms 500 ms N/A V.23, Bell 103 210 ms 210 ms N/A Notes: 1. Times listed are CTS turn-on. The CTS OFF-to-ON response time is host programmable in DSP RAM. (Fullduplex modes only.) 2. Add echo protector tone duration plus 20 ms when echo protector tone is used during turn-on. 3. Turn-off sequence consists of transmission of remaining data and scrambled ones for controlled carrier operation. CTS turn-off is less than 2 ms for all configurations. 4. Plus 20 ms of no transmitted energy. 5. N/A = not applicable. Receive Level The MDP satisfies performance requirements for received line signal levels from –9 dBm to –43 dBm measured at the Receiver Analog (RXA) (TIP and RING) input (-15 dBm at RIN). Note: A 6 dB pad is required between TIP and RING and the RIN input. Receiver Timing Transmitter timing is selectable between internal (±0.01%), external, or slave. The timing recovery circuit can track a frequency error in the associated transmit timing source of ±0.035% (V.22 bis) or ±0.01% (other configurations). Scrambler/Descrambler Carrier Recovery A self-synchronizing scrambler/descrambler is used in accordance with the selected configuration. The carrier recovery circuit can track a ±7 Hz frequency offset in the received carrier. Answer Tone Clamping When the NV25 bit is a zero, the MDP generates a 2100 Hz answer tone at the beginning of the answer handshake for 5.0 seconds (V.8) or 3.6 seconds (V.32 bis, V.32, V.22 bis, V.22, V.23, and V.21). The answer tone has 180° phase reversals every 0.45 second to disable network echo cancellers (V.8, V.32 bis, V.32). Received Data (RXD) is clamped to a constant mark whenever the Received Line Signal Detector (~RLSD) is off. ~RLSD can be clamped off (RLSDE bit). 0' 53'53'DQG53' /RZ9ROWDJH9.IOH[99ELV0RGHP'DWD3XPSV Echo Canceller AudioSpan Mode (SP Models) V.90 and K56flex echo cancellation is also provided. AudioSpan provides full-duplex analog simultaneous audio/voice and data over a single telephone line at a data rate with audio of 4800 bps using V.61 modulation. AudioSpan can send any type of audio waveform, including music. Data can be sent with or without error correction. The audio/voice interface can be in the form of a headset, handset, or a microphone and speaker (halfduplex speakerphone). Handset echo cancellation is provided. ADPCM Voice Mode Data Formats The Adaptive Differential Pulse Code Modulation (ADPCM) voice coder and decoder (codec) compresses and decompresses voice signals for efficient digital storage of voice messages. The codec operates at 28.8k, 21.6k, or 14.4k bps (4-bit, 3-bit, or 2-bit quantization, respectively) with a 7.2 kHz or 8.0 kHz sample rate. Serial Synchronous Data Transmit Voice. 16-bit compressed transmit voice can be sent to the MDP ADPCM codec for decompression then to the digital-to-analog converter (DAC) by the host. Serial Asynchronous Data A data echo canceller with near-end and far-end echo cancellation is included for 2-wire full-duplex V.34/V.32 bis/V.32 operation. The combined echo span of near and far cancellers can be up to 40 ms. The proportion allotted to each end is automatically determined by the MDP. The delay between near-end and far-end echoes can be up to 1.2 seconds. Data rate: Selectable clock: Internal, external, or slave. Data rate: Receive Voice. 16-bit received voice samples from the MDP analog-to-digital converter (ADC) can be sent to the ADPCM codec for compression, and then be read by the host. Voice Pass-Through Mode Voice pass-through mode allows the host to transmit and receive uncompressed voice samples in 16-bit linear form at 7.2 kHz, 8.0 kHz, or 11.025 kHz sample rate, or in 8-bit A-Law/µ-Law PCM form at 8.0 kHz sample rate. Transmit Voice. Transmit voice samples can be sent to the MDP DAC from the host. Receive Voice. Received voice samples from the MDP ADC can be read by the host. Speakerphone Voice/Audio Paths (SP Models) The MDP incorporates a dual integrated analog interface. The voice/audio transmit and receive signals can be routed through several paths. The voice/audio paths are available in the speakerphone mode configuration and are selected through DSP RAM. The voice/audio input can be taken from one of four different sources: telephone line input (RIN), handset (TELIN), microphone (MICM or MICV). 300-56000 bps (RP56), 300-33600 bps (RP56 and RP336), or 300-14400 bps, ±0.01%. 300-56000 bps (RP56), 300-33600 bps (RP56 and RP336), or 300-14400 bps, +1% (or +2.3%), -2.5%; 0-300 bps (V.21 and Bell 103); 1200/75 bps (V.23). Bits per character: 7, 8, 9, 10, or 11. Parallel Synchronous Data Normal sync: 8-bit data for transmit and receive Data rate: 300-56000 bps (RP56), 300-33600 bps (RP56 and RP336), or 300-14400 bps, ±0.01%. SDLC/HDLC support: Transmitter: Flag generation, 0 bit stuffing, CRC-16 or CRC-32 generation. Receiver: Flag detection, 0 bit deletion, CRC-16 or CRC-32 checking. Parallel Asynchronous Data Data rate: 300-56000 bps (RP56), 300-33600 bps (RP56 and RP336), or 300-14400 bps, +1% (or 2.3%), -2.5%; 1200, 300, or 75 bps (FSK). Data bits per character: 5, 6, 7, or 8. The speaker output (SPK) can originate from one of five different sources: RIN, TELIN, MICM or MICV or from the MDP’s internal voice playback mode. Parity generation/checking: Odd, even, or 9th data bit. The voice/audio output may be routed to the telephone line output (TXA1 and TXA2) or handset (TELOUT). An asynchronous-to-synchronous converter is provided in the transmitter and a synchronous-to-asynchronous converter is provided in the receiver. The converters operate in both serial and parallel modes. The asynchronous character format is 1 start bit, 5 to 8 data bits, an optional parity bit, and 1 or 2 stop bits. Valid character size, including all bits, is 7, 8, 9, 10, or 11 bits per character. Two ranges of signaling rates are provided: • Basic range: +1% to –2.5% • Extended overspeed range: +2.3% to –2.5% The voice paths can be switched to allow an audio input to be routed to the telephone line output through a variable gain for applications such as music-on-hold. The “room monitor” mode allows the MDP to receive audio from its surroundings and concurrently transmit the audio to a remote site. Async/Sync and Sync/Async Conversion 0' /RZ9ROWDJH9.IOH[99ELV0RGHP'DWD3XPSV When the transmitter's converter is operating at the basic signaling rate, no more than one stop bit will be deleted per 8 consecutive characters. When operating at the extended rate, no more than one stop bit will be deleted per 4 consecutive characters. Break handling is performed as described in V.14. Asynchronous characters are accepted on the TXD serial input and are issued on the RXD serial output. V.54 Inter-DCE Signaling The MDP supports V.54 inter-DCE signaling procedures in synchronous and asynchronous configurations. Transmission and detection of the preparatory, acknowledgment, and termination phases as defined in V.54 are provided. Three control bits in the transmitter allow the host to send the appropriate bit patterns (V54T, V54A, and V54P bits). Three control bits in the receiver are used to enable one of three bit pattern detectors (V54TE, V54AE, and V54PE bits). A status bit indicates when the selected pattern detector has found the corresponding bit pattern (V54DT bit). V.13 Remote RTS Signaling The MDP supports V.13 remote RTS signaling. Transmission and detection of signaling bit patterns in response to a change of state in the RTS bit or the ~RTS input signal are provided. The RRTSE bit enables V.13 signaling. The RTSDE bit enables detection of V.13 patterns. The RTSDT status bit indicates the state of the remote RTS signal. This feature may be used to clamp/unclamp the local ~RLSD and RXD signals in response to a change in the remote RTS signal in order to simulate controlled carrier operation in a constant carrier environment. The MDP automatically clamps and unclamps ~RLSD. Dialing and Answering The host can dial and answer using supported DTMF/pulse dialing and tone detection functions. The major parameters are host programmable. Supervisory Tone Detection Three parallel tone detectors (A, B, and C) are provided for supervisory tone detection. The signal path to these detectors is separate from the main received signal path. Each tone detector consists of two cascaded second order IIR biquad filters. The coefficients are host programmable. Each fourth order filter is followed by a level detector which has host programmable turn-on and turn-off thresholds allowing hysteresis. Tone detector C is preceded by a prefilter and squarer. This circuit is useful for detecting a tone with frequency equal to the difference between two tones that may be simultaneously present on the line. The squarer may be disabled by the SQDIS bit causing tone detector C to be an eighth order filter. The tone detectors are disabled in data mode. The tone detection sample rate is 9600 Hz in V.8 and V.34 modes and is 7200 Hz in non-V.34 modes. The default call progress filter coefficients are based on a 7200 Hz sampling rate and apply to non-V.34 modes only. 0' 53'53'DQG53' The maximum detection bandwidth is equal to one-half the sample rate. The default bandwidths and thresholds of the tone detectors are: Tone Detector Bandwidth Turn-On Threshold Turn-Off Threshold A 245 – 650 Hz –25 dBm –31 dBm B 360 – 440 Hz –25 dBm –31 dBm C Prefilter 0 – 500 Hz N/A N/A C 50 – 110 Hz * * * Tone Detector C will detect a difference tone within its bandwidth when the two tones present are in the range –1 dBm to –26 dBm. 511 Pattern Generation/Detection In synchronous mode, a 511 pattern can be generated and detected (control bit S511). Use of this bit pattern during self-test eliminates the need for external test equipment. In-Band Secondary Channel A full-duplex in-band secondary channel is provided in V.34 (all speeds) and V.32 bis/V.32 (7200 bps and above) modes. Control bit SECEN enables and disables the secondary channel operation. The secondary channel operates in parallel data mode with independent transmit and receive interrupts and data buffers. The main channel may operate in parallel or serial mode. In V.34 modes, the secondary channel rate is 200 bps. In V.32 bis/V.32 modes, the secondary channel rate is 150 bps. This rate is also host programmable in V.32 bis/V.32 modes. Transmit and Receive FIFO Data Buffers Two (16+128)-byte first-in first-out (FIFO) data buffers allow the DTE/host to rapidly output up to 144 bytes of transmit data and input up to 144 bytes of accumulated received data. The receiver FIFO is always enabled. The transmitter FIFO is enabled by the FIFOEN control bit. TXHF and RXHF bits operate off the lower 16 bits and indicate the corresponding FIFO buffer half full (8 or more bytes loaded) status. TXFNF and RXFNE bits indicate the TXFIFO buffer not full and RXFIFO buffer not empty status, respectively. An interrupt mask register allows an interrupt request to be generated whenever the TXFNF, RXFNE, RXHF, or TXHF status bit changes state. The 128-byte FIFO extensions are enabled by default and can be disabled by clearing a bit in RAM. DMA Support Interrupt Request Lines DMA support is available in synchronous, asynchronous, and HDLC parallel data modes. Control bit DMAE enables and disables DMA support. When DMA support is enabled, the MDP ~RI and ~DSR lines are assigned to Transmitter Request (TXRQ) and Receiver Request (RXRQ) hardware output interrupt request lines, respectively. The TXRQ and RXRQ signals follow the assertion of the TDBE and RDBF interrupt bits thus allowing the DTE/host to respond immediately to the 53'53'DQG53' /RZ9ROWDJH9.IOH[99ELV0RGHP'DWD3XPSV interrupt request without masking out status bits to determine the interrupt source. NRZI Encoding/Decoding NRZI data encoding/decoding may be selected in synchronous and HDLC modes instead of the default NRZ (control bit NRZIEN). In NRZ encoding, a 1 is represented by a high level and a 0 is represented by a low level. In NRZI encoding, a 1 is represented by no change in level and a 0 is represented by a change in level. ITU-T CRC-32 Support ITU-T CRC-32 generation/checking may be selected instead of the default ITU-T CRC-16 in HDLC mode using DSP RAM access. Caller ID Demodulation Caller ID information can be demodulated in V.23 1200 receive configuration and presented to the host/DTE in serial (RXD) and parallel (RBUFFER) form. Telephone Line Interface Line Transformer Interface. V.90/K56flex/V.34/V.32 bis/V.32 places high requirements upon the Data Access Arrangement (DAA) to the telephone line. Any non-linear distortion generated by the DAA in the transmit direction cannot be canceled by the MDP's echo canceller and interferes with data reception. The designer must, therefore, ensure that the total harmonic distortion seen at the RXA input to the MDP be at least 65 dB below the minimum level of received signal. Due to the wider bandwidth requirements in V.90, K56flex, and V.34, the DAA must maintain linearity from 10 Hz to 4000 Hz. Hardware Interface Signals A functional interconnect diagram showing the typical MDP connection in a system is illustrated in Figure 2. Any point that is active low is represented by a small circle at the signal point. Edge triggered inputs are denoted by a small triangle (e.g., TDCLK). An active low signal is indicated by a tilde preceding the signal name (e.g., ~RESET). A clock intended to activate logic on its rising edge (lowto-high transition) is called active low (e.g., ~RDCLK), while a clock intended to activate logic on its falling edge (high-to-low transition) is called active high (e.g., TDCLK). When a clock input is associated with a small circle, the input activates on a falling edge. If no circle is shown, the input activates on a rising edge. The 100-pin PQFP MDP hardware interface signals are shown Figure 2. The 100-pin PQFP MDP signal pin assignments are shown Figure 3 and are listed in Table 4. The MDP hardware interface signals are described in Table 5. The digital interface characteristics are defined in Table 6. The analog interface characteristics are defined Table 7. The power requirements are defined in Table 8. The absolute maximum ratings are defined in Table 9. Relay Control. Direct control of the off-hook and talk/data relays is provided. Internal relay drivers allow direct connection to the off-hook (RLYA) and talk/data (RLYB) relays. The talk/data relay output can optionally be used for pulse dial. Speaker Interface An analog speaker output (SPK) is provided with on/off and volume control logic incorporated in the MDP. An external amplifier is recommended if driving non-amplified speakers. A digital speaker output (SPKMD) is provided which reflects the received analog input signal digitized to TTL high or low level by an internal comparator to create a PC Card (PCMCIA)-compatible signal. Additional Information Additional information is provided in the RP56D, RP336D, and RP144D Modem Designer's Guide (Order No. 1155). 0' /RZ9ROWDJH9.IOH[99ELV0RGHP'DWD3XPSV 75 76 88 89 90 91 92 93 94 95 96 97 2 3 4 5 6 7 MCU EXTERNAL BUS 80 9 36 17 MCU: IRQ MCU: ~WKRESOUT MCU: ~RESET 86 SERIAL DTE INTERFACE 28.224 MHz CLOCK CLKIN YCLK XCLK 87 NC NC D0 D1 D2 D3 D4 D5 D6 D7 RS0 RS1 RS2 RS3 RS4 ~CS ~WRITE ~READ ~RLYA RINGD RIN TXA1 TXA2 TELIN/NC* TELOUT/NC* MICV/NC* MICM SPK SPKMD IRQ ~WKRES ~RES2 ~RES1 VREF 47 79 35 30 31 26 27 34 37 29 38 TELEPHONE LINE/ TELEPHONE/ AUDIO INTERFACE 32 10 VC 82 8 12 64 13 67 11 78 53'53'DQG53' 0.1 CER 33 FB DAA FOR EXTERNAL VC USE FERRITE BEADS (70 OHM @ 100 MHZ TYPE WITH A MAX DC RESISTANCE OF 0.5 OHM AND A RATED CURRENT OF 200 mA). FB GPO0 ~RDCLK TDCLK XTCLK TXD RXD ~RLSD ~RI 10 0.1 CER 10 98 PLLVDD +3.3V (VDD) 10 PLLGND RESERVED RESERVED RESERVED 58 RESERVED RESERVED RESERVED 71 RESERVED VGG RESERVED RESERVED RESERVED 40 RESERVED AVDD 63 RESERVED VDD 68 RESERVED VDD 85 RESERVED VDD NC +5V +3.3V 0.1 10 16 65 81 99 49 PROVIDE DIRECT CONNECTION OR FERRITE BEAD BETWEEN GND AND AGND, WHICHEVER ACHIEVES LOWEST NOISE FLOOR. 10µH 28 0.022 GND GND GND GND GND MCLKIN MTXSIN MRXOUT MSTROBE MSCLK MCNTRLSIN FB +5V 0.1 SLEEPO IASLEEP AVAA 10 25 39 48 AGND AGND AGND SR1IO IA1CLK SA1CLK SR4IN SR4OUT CLKOUT SR3OUT SR3IN SA2CLK SR2CLK SR2IO VCNTRLSIN/NC* VSCLK/NC* VSTROBE/NC* VRXOUT/NC* VTXSIN/NC* VCLKIN/NC* 100 14 15 1 57 61 66 70 72 73 74 77 83 84 NC NC NC NC NC NC NC NC NC NC NC NC NC 69 56 42 43 45 46 44 41 62 24 23 20 18 22 19 21 59 10 60 55 52 50 51 53 54 NOTES: 1. TOLERANCES AND RATINGS (UNLESS OTHERWISE SPECIFIED): RESISTOR VALUES IN OHMS; 5%, 1/8W CAPACITOR VALUES IN MICROFARADS; 10%, 20V 2. DENOTES ANALOG GROUND. 3. DENOTES DIGITAL GROUND. * PINS ARE INTERNAL NO CONNECT (NC) ON NON-SP MODELS. MD218F4-HIS-100PQFP )LJXUH 0'3 +DUGZDUH ,QWHUIDFH 6LJQDOV3LQ 34)3 0' PLLGND GND PLLVDD RS1 RS0 D7 D6 D5 D4 D3 D2 D1 D0 NC CLKIN VDD RESERVED RESERVED GP00 GND 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 /RZ9ROWDJH9.IOH[99ELV0RGHP'DWD3XPSV 100 99 53'53'DQG53' RESERVED RS2 1 80 IRQ 2 RINGD RS3 3 79 78 RS4 ~CS 4 77 RESERVED 5 6 76 XCLK 75 YCLK 7 74 RESERVED ~RDCLK 8 73 ~WKRES SR2CLK ~RLSD 9 72 RESERVED RESERVED 10 71 VGG 11 RESERVED ~WRITE ~READ ~RI 15 16 66 RESERVED 65 GND ~RES1 17 64 XTCLK SR4OUT 18 63 SR3OUT SR4IN 19 62 VDD SR1IO 20 61 RESERVED SR3IN 21 SR2IO CLKOUT 22 60 59 SA1CLK IA1CLK AGND 23 58 RESERVED 24 25 57 RESERVED 56 IASLEEP TELIN/NC* 26 55 VCNTRLSIN/NC* TELOUT/NC* AVAA SPKR TXA1 27 54 VCLKIN/NC* 28 53 29 52 VTXSIN/NC* VSCLK/NC* 30 51 VRXOUT/NC* SA2CLK 50 46 MSTROBE ~RLYA SLEEPO GND VSTROBE/NC* 45 MRXOUT AGND 44 41 MCNTRLSIN MCLKIN 43 40 AVDD MTXSIN MSCLK 39 MICM SPKMD AGND 32 RIN ~RES2 31 TXA2 VREF VC MICV/NC* 49 RXD RESERVED GND 47 48 67 42 14 37 38 VDD RESERVED 36 68 35 13 34 12 33 TDCLK TXD 70 69 MD212F5 PO-R6764-100P * NC on non-SP models. )LJXUH 0'3 3LQ 6LJQDOV 3LQ 34)3 0' /RZ9ROWDJH9.IOH[99ELV0RGHP'DWD3XPSV 53'53'DQG53' 7DEOH 0'3 3LQ 6LJQDOV 3LQ 34)3 Pin Signal Label I/O Type 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 RESERVED RS2 RS3 RS4 ~CS ~WRITE ~READ ~RDCLK ~WKRES SR2CLK ~RLSD TDCLK TXD RESERVED RESERVED GND ~RES1 18 19 20 21 22 SR4OUT SR3OUT SR4IN SR3IN CLKOUT DI DI DI DI DI 23 24 25 26 27 28 29 30 31 32 33 SA1CLK IA1CLK AGND TELIN/NC* TELOUT/NC* AVAA SPK TXA1 TXA2 VREF VC DI DI GND I(DA) O(DD) PWR O(DF) O(DD) O(DD) REF REF 34 35 36 MICV/NC* RIN ~RES2 I(DA) I(DA) 37 38 39 40 41 42 43 44 45 46 47 48 MICM SPKMD AGND AVDD MCNTRLSIN MCLKIN MTXSIN MSCLK MRXOUT MSTROBE ~RLYA AGND 49 50 GND VSTROBE/NC* Interface3 I(DA) OA GND PWR DI DI DI DI DI DI OD GND NC Host Parallel Interface Host Parallel Interface Host Parallel Interface Host Parallel Interface Host Parallel Interface Host Parallel Interface DTE Serial Interface MCU: READY/~WKRESOUT To VSCLK (52) DTE Serial Interface DTE Serial Interface DTE Serial Interface NC NC DGND PIF: ~RESET SIF: Reset circuit To MTXSIN (43) To VTXSIN (53) To MRXOUT (45) To VRXOUT (51) To MCLKIN (42) & VCLKIN (54) To MSTROBE (46) To MSCLK (44) Analog Ground Line/Audio Interface Line/Audio Interface +5VA Line/Audio Interface Line/Audio Interface Line/Audio Interface VC through capacitors DAA through FB; GND through capacitors and FB Line/Audio Interface Line/Audio Interface PIF: ~RESET SIF: Reset circuit Line/Audio Interface Line/Audio Interface Analog Ground +3.3V To SR1IO (62) To CLKOUT (22) To SR4OUT (18) To IA1CLK (24) To SR4IN (20) To SA1CLK (23) NC AGND GND DI DGND To SA2CLK (59) IA IA IA IA IA IA OA IA DI OA OA IA GND Notes: 1. I/O types: IA, IB = Digital input; OA, OB = Digital output. I(DA) = Analog input; O(DD), O(DF) = Analog output. DI = Device interconnect. 2. NC = No external connection allowed (may have internal connection). 0' Pin Signal Label I/O Type 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 VRXOUT/NC* VSCLK/NC* VTXSIN/NC* VCLKIN/NC* VCNTRLSIN/NC* IASLEEP RESERVED RESERVED SA2CLK SR2IO RESERVED SR1IO VDD XTCLK GND RESERVED RXD DI DI DI DI DI DI 68 69 70 71 72 VDD SLEEPO RESERVED VGG RESERVED 73 74 75 76 77 78 79 80 81 82 83 RESERVED RESERVED YCLK XCLK RESERVED ~RI RINGD IRQ GND GP00 RESERVED 84 85 86 RESERVED VDD CLKIN PWR I 87 88 89 90 91 92 93 94 95 96 97 98 NC D0 D1 D2 D3 D4 D5 D6 D7 RS0 RS1 PLLVDD IA/OB IA/OB IA/OB IA/OB IA/OB IA/OB IA/OB IA/OB IA IA PLL 99 100 GND PLLGND GND PLL DI DI DI PWR IA GND OA PWR DI REF OA OA OA IA IA GND DI Interface To SR3IN (21) To SR2CLK (10) To SR3OUT (19) To CLKOUT (22) To SR2IO (60) To SLEEPO (69) NC NC To VSTROBE (50) To VCNTRLSIN (55) NC To MCNTRLSIN (41) +3.3V DTE Serial Interface DGND NC DTE Serial Interface +3.3V To IASLEEP (56) NC +5V NC NC NC NC NC NC DTE Serial Interface Line/Audio Interface Host Parallel Interface DGND To ~RDCLK (8) NC NC +3.3V Clock Circuit NC Host Parallel Interface Host Parallel Interface Host Parallel Interface Host Parallel Interface Host Parallel Interface Host Parallel Interface Host Parallel Interface Host Parallel Interface Host Parallel Interface Host Parallel Interface To +3.3 (VDD) through 10 Ω and to DGND through 10 µF. DGND DGND 3. Interface Legend: MDP = Modem Data Pump DTE = Data Terminal Equipment PIF = Parallel host interface SIF = Serial DTE interface. * NC on non-SP models. 53'53'DQG53' /RZ9ROWDJH9.IOH[99ELV0RGHP'DWD3XPSV 7DEOH 0'3 6LJQDO 'HILQLWLRQV Label I/O Type Signal/Definition OVERHEAD SIGNALS CLKIN I Clock In. Connect to an external 28.224 MHz clock circuit. ~RES1, ~RES2 IA Reset. ~RESET low holds the MDP in the reset state. ~RESET going high releases the MDP from the reset state and initiates normal operation using power turn-on (default) values. ~RESET must be held low for at least 3 µs. The MDP is ready to use 400 ms after the low-to-high transition of ~RESET. ~RES1 and ~RES2 are typically connected to the MCU ~RESET input and to the host bus ~RESET (or RESET through an inverter) line (parallel host) or reset circuit (serial DTE interface) which resets both the MCU and MDP upon power turn-on. ~RES1 and ~RES2 have active internal pull-up resistors. ~WKRES IA Wake-up Reset. ~WKRES is connected internally to ~RESET but will not drive the MDP ~RESET pins. Asserting ~WKRES performs the same reset function as the MDP ~RESET and typically used by the MCU to wake up the MDP from SLEEP Mode when the MDP ~RESET lines cannot be asserted (because they are also connected to the MCU ~RESET input). For a serial DTE or parallel host MCU configuration, connect ~WKRES to the MCU ~WKRESOUT output. ~WKRES has an active internal pull-up resistor. VDD PWR +3.3V Digital Circuit Power Supply. Connect to +3.3V through digital circuit power supply filter. AVDD PWR +3.3V Analog Circuit Digital Power Supply. Connect to +3.3V through digital circuit power supply filter. AVAA PWR Analog Circuit Analog Power Supply. Connect to +5V through analog circuit power supply filter. VGG REF Input Reference Voltage. Reference voltage for +5V tolerant input pins. Connect to +5V. GND GND Digital Ground. Connect to digital ground. AGND GND Analog Ground. Connect to analog ground. XCLK OA X Clock. Output clock at 56.448 MHz (PLL disabled) or 63.5045 (PLL enabled), which runs during MDP Normal Mode and is turned off during Sleep Mode. YCLK OA Y Clock. Output clock at 28.224 MHz, which runs during MDP Normal Mode and is turned off during Sleep Mode. SYCLK OA System Clock. Output clock at 28.224 MHz, which runs during MDP Normal Mode and during Sleep Mode. PLLVDD PLL PLLVDD Connection. Connect to +3.3V (VDD) through 10 Ω and to DGND through 10 (+) µF. PLLGND PLL PLLGND Connection. Connect to DGND. PARALLEL HOST INTERFACE Address, data, control, and interrupt hardware interface signals allow MDP connection to an 8086-compatible microprocessor bus. With the addition of external logic, the interface can be made compatible with a wide variety of other microprocessors such as the 6502, 8086 or 68000. The microprocessor interface allows a microprocessor to change MDP configuration, read or write channel and diagnostic data, and supervise MDP operation by writing control bits and reading status bits. D0–D7 IA/OB Data Lines. Eight bidirectional data lines (D0–D7) provide parallel transfer of data between the host and the MDP. The most significant bit is D7. Data direction is controlled by the Read Enable and Write Enable signals. RS0–RS4 IA Register Select Lines. The five active high register select lines (RS0–RS4) address interface memory registers within the MDP interface memory. These lines are typically connected to the five least significant lines (A0–A4) of the address bus. The MDP decodes RS0 through RS4 to address one of 32 internal interface memory registers (00–1F). The most significant address bit is RS4, while the least significant address bit is RS0. The selected register can be read from or written into via the 8-bit parallel data bus (D0–D7). The most significant data bit is D7, while the least significant data bit is D0. ~CS IA Chip Select. ~CS selects the MDP for microprocessor bus operation. ~CS is typically generated by decoding host address bus lines. ~READ IA Read Enable. During a read cycle (~READ asserted), data from the selected interface memory register is gated onto the data bus by means of three-state drivers in the MDP. These drivers force the data lines high for a one bit, or low for a zero bit. When not being read, the three-state drivers assume their high-impedance (off) state. ~WRITE IA Write Enable. During a write cycle (~WRITE asserted), data from the data bus is copied into the selected MDP interface memory register, with high and low bus levels representing one and zero bit states, respectively. IRQ OA Interrupt Request. The MDP IRQ output may be connected to the host processor interrupt request input in order to interrupt host program execution for immediate MDP service. The IRQ output can be enabled in the MDP interface memory to indicate immediate change of conditions. The use of IRQ is optional depending upon MDP application. The IRQ output is driven by a TTL-compatible CMOS driver. 0' /RZ9ROWDJH9.IOH[99ELV0RGHP'DWD3XPSV 53'53'DQG53' 7DEOH 0'3 6LJQDO 'HILQLWLRQV &RQW G Label I/O Type Signal Name/Description DTE SERIAL INTERFACE Timing, data, control, and status signals provide a V.24-compatible serial interface. These signals are TTL compatible in order to drive the short wire lengths and circuits normally found within a printed circuit board, stand-alone modem enclosures, or equipment cabinets. For driving longer cables, these signals can be easily converted to EIA/RS-232-D voltage levels. TXD IA Transmitted Data. The MDP obtains serial data to be transmitted from the local DTE on the Transmitted Data (TXD) input. RXD OA Received Data. The MDP presents received serial data to the local DTE on the Received Data (RXD) output. ~RTS IA Request to Send. Activating ~RTS causes the MDP to transmit data on TXD when ~CTS becomes active. The ~RTS pin is logically ORed with the RTS bit. ~CTS OA Clear To Send. ~CTS active indicates to the local DTE that the MDP will transmit any data present on TXD. CTS response times from an active condition of RTS are shown in Table 3. ~RLSD OA Received Line Signal Detector. ~RLSD active indicates to the local DTE that energy above the receive level threshold is present on the receiver input, and that the energy is not a training sequence. One of four ~RLSD receive level threshold options can be selected (RTH bits). A minimum hysteresis action of 2 dB exists between the actual off-to-on and on-to-off transition levels. The threshold level and hysteresis action are measured with a modulated signal applied to the Receiver Analog (RXA) input. Note that performance may be degraded when the received signal level is less than -43 dBm. The ~RLSD on and off thresholds are host programmable in DSP RAM. ~DTR IA Data Terminal Ready. In V.8, V.90, K56flex, V.34, V.32 bis, V.32, V.22 bis, V.22, or Bell 212A configuration, activating ~DTR initiates the handshake sequence. The DATA bit must be set to complete the handshake. In V.21, V.23, or Bell 103 configuration, activating ~DTR causes the MDP to enter the data state provided that the DATA bit is a 1. If in answer mode, the MDP immediately sends answer tone. In these modes, if controlled carrier is enabled, carrier is controlled by RTS. During the data mode, deactivating ~DTR causes the transmitter and receiver to turn off and return to the idle state. The ~DTR input and the DTR control bit are logically ORed. Data Set Ready. ~DSR ON indicates that the MDP is in the data transfer state. ~DSR OFF indicates that the DTE is to disregard all signals appearing on the interchange circuits except Ring Indicator (~RI). ~DSR is OFF when the MDP is in a test mode (i.e., local analog or remote digital loopback). ~DSR OA ~RI OA Ring Indicator. ~RI output follows the ringing signal present on the line with a low level (0 V) during the ON time, and a high level during the OFF time coincident with the ringing signal. The RI status bit reflects the state of the ~RI output. TDCLK OA Transmit Data Clock. The MDP outputs a synchronous Transmit Data Clock (TDCLK) for USRT timing. The TDCLK frequency is the data rate (±0.01%) with a duty cycle of 50±1%. The TDCLK source can be internal, external (input on XTCLK), or slave (to ~RDCLK) as selected by TXCLK bits in interface memory. XTCLK IA External Transmit Clock. In synchronous communication, an external transmit data clock can be connected to the MDP XTCLK input. The clock supplied at XTCLK must exhibit the same characteristics as TDCLK. The XTCLK input is then reflected at the TDCLK output. ~RDCLK OA Receive Data Clock. The MDP outputs a synchronous Receive Data Clock (~RDCLK) for USRT timing. The ~RDCLK frequency is the data rate (±0.01%) with a duty cycle of 50±1%. The ~RDCLK low-to-high transitions coincide with the center of the received data bits. The DSR status bit reflects the state of the ~DSR output. 0' 53'53'DQG53' /RZ9ROWDJH9.IOH[99ELV0RGHP'DWD3XPSV 7DEOH 0'3 6LJQDO 'HILQLWLRQV &RQW G Label I/O Type Signal Name/Description TELEPHONE LINE/TELEPHONE/AUDIO INTERFACE SIGNALS AND REFERENCE VOLTAGE TXA1, TXA2 O(DF) Transmit Analog 1 and 2 Output. The TXA1 and TXA2 outputs are differential outputs 180 degrees out of phase with each other. Each output can drive a 300 Ω load. Typically, TXA1 and TXA2 are connected to the telephone line interface or an optional external hybrid circuit. RIN I(DA) Receive Analog Input. RIN is a single-ended input with 70K Ω input impedance. Typically, RIN is connected to telephone line interface or an optional external hybrid circuit. NOTE: If not used, do not tie directly to ground; this input has a bias voltage of +2.5V (VAA = +5V). RINGD IA Ring Detect. The RINGD input is monitored for pulses in the range of 15 Hz to 68 Hz. The frequency detection range may be changed by the host in DSP RAM. The circuit driving RINGD should be a 4N35 optoisolator or equivalent. The circuit driving RINGD should not respond to momentary bursts of ringing less than 125 ms in duration, or less than 40 VRMS (15 Hz to 68 Hz) across TIP and RING. Detected ring signals are reflected on the ~RI output signal as well as the RI bit. ~RLYA (~OHRC, ~CALLID) OD Relay A Control. The ~RLYA open drain output can directly drive a reed relay coil with a minimum resistance of 360 ohms (9.2 mA max. @ +3.3V). A clamp diode, such as a 1N4148, should be installed across the relay coil. An external transistor can be used to drive heavier loads (e.g., electro-mechanical relays). ~RLYA is controlled by host setting/resetting of the RA bit. In a typical application, ~RLYA is connected to the normally open Off-Hook relay (~OHRC). In this case, ~RLYA active closes the relay to connect the MDP to the telephone line. Alternatively, in a typical application, ~RLYA is connected to the normally open Caller ID relay (~CALLID). When the MDP detects a Calling Number Delivery (CND) message, the ~RLYA output is asserted to close the Caller ID relay in order to AC couple the CND information to the MDP RIN input (without closing the off-hook relay and allowing loop current flow which would indicate an off-hook condition). ~RLYB (~TALK) OD Relay B Control. The ~RLYB open drain output can directly drive a reed relay coil with a minimum resistance of 360 ohms (9.2 mA max. @ 3.3V). A clamp diode, such as a 1N4148, should be installed across the relay coil. An external transistor can be used to drive heavier loads (e.g., electro-mechanical relays). ~RLYB is controlled by host setting/resetting of the RB bit. In a typical application, ~RLYB is connected to the normally closed Talk/Data relay (~TALK). In this case, ~RLYB active opens the relay to disconnect the handset from the telephone line. MICM I(DA) Modem Microphone Input. MICM is a single-ended microphone input. The input impedance is > 70k Ω. NOTE: If not used, do not tie directly to ground; this input has a bias voltage of +2.5V (VAA = +5V). SPK O(DF) Speaker Analog Output. The SPK analog output can originate from one of five different sources: RIN, TELIN, MICM or MICV or from the MDP’s internal voice playback mode. The SPK on/off and three levels of attenuation are controlled by bits in DSP RAM. When the speaker is turned off, the SPK output is clamped to the voltage at the VC pin. The SPK output can drive an impedance as low as 300 ohms. In a typical application, the SPK output is an input to an external LM386 audio power amplifier. SPKMD OA Modem Speaker Digital Output. The SPKMD digital output reflects the received analog input signal digitized to TTL high or low level by an internal comparator to create a PC Card (PCMCIA)-compatible signal. VREF REF High Voltage Reference. Connect to VC through 10 µF (polarized, + terminal to VREF) and 0.1 µF (ceramic) in parallel. VC REF Low Voltage Reference. Connect to a ferrite bead and connect the other end of the ferrite bead to DGND through 10 µF (polarized, + terminal to VC) and 0.1 µF (ceramic) in parallel. MICV/NC* I(DA) Voice Microphone Input. MICV is a single-ended microphone input. Typically, MICV is connected to a microphone output for recording voice e.g., in a speakerphone application. TELIN/NC* I(DA) NOTE: If not used, do not tie directly to ground; this input has a bias voltage of +2.5V (VAA = +5V). Telephone Analog Input. TELIN is a single-ended input with 70K Ω input impedance. Typically, TELIN is connected to a telephone handset microphone circuit. NOTE: If not used, do not tie directly to ground; this input has a bias voltage of +2.5V (VAA = +5V). TELOUT/NC* O(DF) Telephone Analog Output. TELOUT is a single-ended output that can drive a 300 Ω load. Typically, TELOUT is connected to a telephone handset speaker circuit. MICBIAS REF Microphone Bias. Microphone bias reference voltage. 0' /RZ9ROWDJH9.IOH[99ELV0RGHP'DWD3XPSV 53'53'DQG53' 7DEOH 0'3 6LJQDO 'HILQLWLRQV &RQW G Label I/O Type Signal Name/Description MISCELLANEOUS RESERVED Reserved Function. May be connected to internal circuit. Leave open. MDP INTERCONNECT GP00 DI To ~RDCLK. SLEEPO DI To IASLEEP. IASLEEP DI To SLEEPO. MSCLK DI To IA1CLK. CLKOUT DI To MCLKIN & VCLKIN. SR1IO DI To MCNTRLSIN. SR3IN DI To VRXOUT. IA1CLK DI To MSCLK. SA1CLK DI To MSTROBE. SR4OUT DI To MTXSIN. MCLKIN DI To CLKOUT. VCLKIN/NC* DI To CLKOUT. MSTROBE DI To SA1CLK. VSTROBE/NC* DI To SA2CLK. MCNTRLSIN DI To SR1IO. VSCLK/NC* DI To SR2CLK. VCNTRLSIN/NC* DI To SR2IO. MRXOUT DI To SR4IN. VTXSIN/NC* DI To SR3OUT. VRXOUT/NC* DI To SR3IN. MTXSIN DI To SR4OUT. SR2IO DI To VCNTRLSIN. SR4IN DI To MRXOUT. SR2CLK DI To VSCLK. SA2CLK DI To VSTROBE. SR3OUT DI To VTXSIN. * NC on non-SP models. External interconnects as described can made for the NC pins on non-SP models in case SP models are ever substituted in the application design and SP support is required. 0' 53'53'DQG53' /RZ9ROWDJH9.IOH[99ELV0RGHP'DWD3XPSV 7DEOH 'LJLWDO (OHFWULFDO &KDUDFWHULVWLFV Parameter Input High Voltage Symbol Min. Typ. Max. VIH Type IA Units Vdc 2.0 – VCC – 40 µA 0.8 VDC Input High Current IIH – Input Low Voltage VIL 0.3 Input Low Current IIL – – 40 µA Input Leakage Current IIN – – ±100 µADC – – VDC – VCC Output High Voltage VOH Type OA 2.4 VIN = 0 to +3.3V, VCC = 3.6V ILOAD = – 100 µA Type OD Output Low Voltage Test Conditions1 ILOAD = 0 mA VOL VDC Type OA – – 0.4 ILOAD = 1.6 mA Type OD – – 0.75 ILOAD = 15 mA Three-State (Off) Current ITSI ±10 µADC VIN = 0.4 to VCC-1 7DEOH $QDORJ (OHFWULFDO &KDUDFWHULVWLFV Signal Name Characteristic Value I (DA) Input Impedance AC Input Voltage Range Reference Voltage > 70K Ω 1.1 VP-P +2.5 VDC (VAA = +5V) TXA1, TXA2, TELOUT O (DD) Minimum Load Maximum Capacitive Load Output Impedance AC Output Voltage Range Reference Voltage DC Offset Voltage 300 Ω 0 µF 10 Ω 2.2 VP-P (VAA = +5V) (with reference to ground and a 600 Ω load) +2.5 VDC (VAA = +5V) ± 200 mV Minimum Load 300 Ω Maximum Capacitive Load Output Impedance AC Output Voltage Range Reference Voltage DC Offset Voltage 0.01 µF 10 Ω 2.2 VP-P (VAA = +5V) +2.5 VDC (VAA = +5V) ± 20 mV SPK Type RIN, TELIN, MICM, MICV O (DF) 0' /RZ9ROWDJH9.IOH[99ELV0RGHP'DWD3XPSV 53'53'DQG53' 7DEOH &XUUHQW DQG 3RZHU 5HTXLUHPHQWV Notes Typical Current (mA) Maximum Current (mA) Typical Power (mW) Maximum Power (mW) Normal Mode 85 90 280 325 f = 28.224 MHz Sleep Mode 53 — 175 — f = 28.224 MHz Mode Notes: 1. 2. 3. 4. Operating voltage: VDD = +3.3V ± 0.3V. Test conditions: VDD = +3.3V for typical values; VDD = +3.6V for maximum values. Input Ripple ≤ 0.1 Vpeak-peak. f = Internal frequency. 7DEOH $EVROXWH 0D[LPXP 5DWLQJV Symbol Limits Units Supply Voltage Parameter VDD -0.5 to +4.0 V Input Voltage VIN Except XTLI XTLI Operating Temperature Range V TA -0.5 to (VGG +0.5)* -0.5 to 3.9V -0 to +70 °C TSTG -55 to +125 °C Analog Inputs VIN -0.3 to (VAA + 0.5) V Voltage Applied to Outputs in High Impedance (Off) State VHZ -0.5 to (VGG +0.5)* V DC Input Clamp Current IIK ±20 mA DC Output Clamp Current IOK ±20 mA Static Discharge Voltage (25°C) VESD ±2500 V Latch-up Current (25°C) ITRIG ±400 mA Storage Temperature Range * VGG = +5.0V ± 5%. 0' 53'53'DQG53' :RUOGZLGH +HDGTXDUWHUV 86 1RUWK &HQWUDO )RU PRUH LQIRUPDWLRQ 86 6RXWK &HQWUDO -DPERUHH 5RDG 32 %R[ & 1HZSRUW %HDFK &$ 3KRQH )D[ &DOO ,QWHUQDWLRQDO LQIRUPDWLRQ &DOO 85/ $GGUHVV KWWSZZZFRQH[DQWFRP (0DLO $GGUHVV OLWHUDWXUH#FRQH[DQWFRP 5(*,21$/ 6$/(6 2)),&(6 86 1RUWKZHVW3DFLILF 1RUWKZHVW 3UXQHULGJH $YHQXH 6XLWH 6DQWD &ODUD &$ 3KRQH )D[ 86 /RV $QJHOHV %XVLQHVV &HQWHU &LUFOH 6XLWH 7KRXVDQG 2DNV &$ 3KRQH )D[ 86 6RXWKZHVW 9RQ .DUPDQ $YH 6XLWH 1HZSRUW %HDFK &$ 3KRQH )D[ 7ZR 3LHUFH 3ODFH &KDQFHOORU\ 3DUN 6XLWH ,WDVFD ,/ 3KRQH )D[ 3UHVWRQ 5RDG 6XLWH 'DOODV 7; 3KRQH )D[ 86 1RUWKHDVW /LWWOHWRQ 5RDG 6XLWH $ :HVWIRUG 0$ 3KRQH )D[ 86 6RXWKHDVW 3DUNZD\ /DQH 6XLWH 1RUFURVV *$ 3KRQH )D[ 86 )ORULGD6RXWK $PHULFD 2QH 3UHVWLJH 3ODFH 0F&RUPLFN 'ULYH 6XLWH &OHDUZDWHU )/ 3KRQH )D[ 86 0LG$WODQWLF 3ULQFHWRQ 3LNH &RUSRUDWH &HQWHU /HQR[ 'ULYH 6XLWH /DZUHQFHYLOOH 1- 3KRQH )D[ /RZ9ROWDJH9.IOH[99ELV0RGHP'DWD3XPSV (XURSHDQ +HDGTXDUWHUV /HV 7DLVVRXQLHUHV % 5RXWH GHV 'ROLQHV %3 6RSKLD $QWLSROLV &HGH[ )UDQFH 3KRQH )D[ (XURSH 6RXWK 7RXU *$1 &HGH[ 3DULV /D 'pIHQVH )UDQFH 3KRQH )D[ $3$& +HDGTXDUWHUV 3DXO*HUKDUGW$OOHH D 0QFKHQ *HUPDQ\ 3KRQH )D[ .LP 6HQJ 3URPHQDGH (DVW 7RZHU *UHDW :RUOG &LW\ 6LQJDSRUH 3KRQH )D[ (XURSH 0HGLWHUUDQHDQ $XVWUDOLD (XURSH 1RUWK &KLQD (XURSH &HQWUDO 9LD * 'L 9LWWRULR 0D]]R 'L 5KR 0, ,WDO\ 3KRQH )D[ %HUNVKLUH &RXUW :HVWHUQ 5RDG %UDFNQHOO %HUNVKLUH 5* 5( (QJODQG 3KRQH )D[ (XURSH 1RUWK 6DWHOOLWH *DOJDOH\ +DSODGD 6WUHHW 32 %R[ +HU]OLD ,VUDHO 3KRQH )D[ 6XLWH 5DZVRQ 6WUHHW (SSLQJ 16: $XVWUDOLD 3KRQH )D[ 6KDQJKDL 5HSUHVHQWDWLYH 2IILFH /7 6TXDUH %XLOGLQJ 6XLWH &KHQJGX 1RUWK 5RDG 6KDQJKDL 35& 3KRQH )D[ +RQJ .RQJ WK )ORRU 6XLWHV +DUERXU &HQWUH +DUERXU 5RDG :DQFKDL +RQJ .RQJ 3KRQH )D[ ,QGLD 5HJLRQDO 2IILFH 6RXWK $VLD &DSLWDO 7UXVW +RXVH &RPPXQLW\ &HQWUH )ULHQGV &RORQ\ 1HZ 'HOKL ,QGLD 3KRQH )D[ .RUHD 5RRP 1R .RUHD 7H[WLOH &HQWUH %XLOGLQJ 'DHFKLGRQJ .DQJQDP 32 %R[ .DQJQDPNX 6HRXO .RUHD 3KRQH )D[ 7DLZDQ +HDGTXDUWHUV 5RRP ,QWHUQDWLRQDO 7UDGH %OGJ .HHOXQJ 5RDG 6HFWLRQ , 7DLSHL 7DLZDQ 52& 3KRQH )D[ -DSDQ +HDGTXDUWHUV 6KLPRPRWR %OGJ +DWVXGDL 6KLEX\DNX 7RN\R -DSDQ 3KRQH )D[ 628'