cystek CYStech Electronics Corp. Spec. No. : C504A3 Issued Date : 2003.03.21 Revised Date : Page No. : 1/9 Adjustable shunt regulator PL432XA3/N3 Description Features The PL432 is a three terminal adjustable shunt regulator with thermal stability guaranteed over temperature. The output voltage can be adjusted to any value from 1.24V(VREF) to 20V with two external resistors. The PL432 has a typical dynamic output impedance of 0.05Ω. Active output circuitry provides a very sharp turn on characteristic, making the PL432 an excellent replacement for zener diodes. The PL432 shunt regulator is available with four Voltage tolerances(0.25%,0.5%,1% and 2%), and two package options(TO-92 and SOT-23). This allows the designer the opportunity to select the optimum combination of cost and performance for their application. ◆Low voltage operation(down to 1.24V) ◆Wide operating current range 80μA to 100mA ◆Low dynamic output impedance 0.05Ω typ. ◆Trimmed bandgap design ±0.25% ◆Upgrade for PL431 ◆Available in TO-92 and SOT-23 packages Applications ◆Linear Regulators ◆Adjustable Supplies ◆Switching Power Supplies ◆Battery Operated Computers ◆Instrumentation ◆ Computer Disk Drives Typical Application Circuit(Note 1,2) Notes: VIN R VOUT R1 VREF PL432 R2 GND PL432XA3/N3 1) Set VOUT according to the following equation: VOUT=VREF(1+R1/R2)+IREFR1 2) Choose the value for R as follows: ˙The maximum limit for R should be such that the cathode current, Iz, is greater than the minimum operating current(80μA) at VIN(MIN). ˙The minimum limit for R should be as such that Iz does not exceed 100mA under all load conditions, and the instantaneous turn-on value for Iz does not exceed 150mA. Both of the following conditions must be met: Rmin≥VIN(max)/150mA(to limit instantaneous turn-on Iz) Rmin≥ VIN(max)-VOUT (to limit Iz under IOUT(min)+100mA normal operating conditions) CYStek Product Specification cystek Spec. No. : C504A3 Issued Date : 2003.03.21 Revised Date : Page No. : 2/9 CYStech Electronics Corp. Absolute Maximum Ratings Parameter Cathode Voltage Continuous Cathode Current Reference Input Current Power Dissipation at TA=25℃ SOT-23 TO-92 Thermal Resistance SOT-23 TO-92 Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Lead Temperature(Soldering) 10 seconds ESD Rating(Human Body Model) Symbol Vz IZ IREF Maximum 20 100 3 Units V mA mA PD 0. 37 0.95 W 336 132 0 to +70 0 to +150 -65 to +150 300 2 ΘJA TA TJ Tstg T LEAD V ESD ℃/W ℃ ℃ ℃ ℃ kV Electrical Characteristics Unless otherwise specified, TA=25℃. Values in bold apply over full operating ambient temperature range. PL432D Parameter Reference Voltage VREF Temperature Deviation Ratio of Change in VREF to change in VZ Reference Input Current IREF Temperature Deviation Off-state Cathode Current Dynamic Output Impedance Minimum Operating Current PL432XA3/N3 Symbol Condition VREF VZ=VREF,IZ=10mA(Note 1) VDEV VZ=VREF,IZ=10mA(Note 1) ΔVREF IZ=10mA, ΔVZ=16V to VREF ΔVZ IREF R1=10kΩ,R2=∞, IZ=10mA(Note2) IREF(DEV) R1=10kΩ,R2=∞, IZ=10mA(Note 2) IZ(OFF) VREF=0V,VZ=6V(Note 3) VREF=0V,VZ=16V(Note 3) f <1kHz,VZ=VREF rz IZ=100μA to 100mA(Note 1) IZ(MIN) VZ=VREF(Note 1) Min 1.237 1.224 - Typ 1.240 PL432C 10 Max 1.243 1.256 25 Min 1.234 1.222 - Typ Max 1.240 1.246 1.258 10 25 Unit V - -1.0 -2.7 - -1.0 -2.7 mV/V - 0.15 0.5 - 0.15 0.5 μA - 0.1 0.4 - 0.1 0.4 μA - 0.125 0.135 0.05 0.150 0.150 0.15 - 0.125 0.135 0.05 0.150 0.150 0.15 μA - 20 80 - 20 80 μA mV Ω CYStek Product Specification cystek Spec. No. : C504A3 Issued Date : 2003.03.21 Revised Date : Page No. : 3/9 CYStech Electronics Corp. Electrical Characteristics(Cont.) Unless otherwise specified, TA=25℃. Values in bold apply over full operating ambient temperature range. PL432B Parameter Reference Voltage Symbol Condition VREF VZ=VREF,IZ=10mA(Note 1) VREF Temperature VDEV Deviation Ratio of Change in ΔVREF VREF to change in VZ ΔVZ Reference Input IREF Current IREF Temperature IREF(DEV) Deviation Off-state Cathode IZ(OFF) Current Dynamic Output rz Impedance Minimum Operating IZ(MIN) Current Notes: (1) See Test Circuit 1. (2) See Test Circuit 2. (3) See Test Circuit 3. Min 1.228 1.215 - Typ 1.240 IZ=10mA, ΔVZ=16V to VREF R1=10kΩ,R2=∞, IZ=10mA(Note2) R1=10kΩ,R2=∞, IZ=10mA(Note 2) VREF=0V,VZ=6V(Note 3) VREF=0V,VZ=16V(Note 3) f<1kHz,VZ=VREF IZ=100μA to 100mA(Note 1) VZ=VREF(Note 1) VZ=VREF,IZ=10mA(Note 1) PL432A 10 Max 1.252 1.265 25 Min 1.215 1.200 - Typ Max 1.240 1.265 1.280 10 35 Unit V - -1.0 -2.7 - -1.0 -2.7 mV/V - 0.15 0.5 - 0.15 0.5 μA - 0.1 0.4 - 0.1 0.4 μA - 0.125 0.135 0.05 0.150 0.150 0.15 - 0.125 0.135 0.05 0.150 0.150 0.15 μA - 20 80 - 20 80 μA mV Ω Recommended Operating Conditions Cathode Voltage Cathode Current Symbol Min Max Unit VZ IZ VREF 0.08 16 100 V mA Test Circuits VIN VZ IREF IZ VIN VZ R1 VIN VZ IZ IREF IZ(off) VREF R2 Test Circuit 1 VZ=VREF PL432XA3/N3 Test Circuit 2 VZ>VREF Test Circuit 3 Off-State CYStek Product Specification cystek TO-92(Top View) SOT-23(Top View) 2 Anode Spec. No. : C504A3 Issued Date : 2003.03.21 Revised Date : Page No. : 4/9 CYStech Electronics Corp. Cathode 3 Cathode Anode 2 3 1 Reference Reference 1 Block Diagram Symbol Cathode Cathode REF REF VREF Anode Anode Ordering Information Package TO-92 SOT-23 PL432XA3/N3 Tolerance 0.25% PL432DA3 PL432DN3 0.5% PL432CA3 PL432CN3 1% PL432BA3 PL432BN3 2% PL432AA3 PL432AN3 CYStek Product Specification cystek Spec. No. : C504A3 Issued Date : 2003.03.21 Revised Date : Page No. : 5/9 CYStech Electronics Corp. Characteristic Curves Cathode Current vs Cathode Voltage Cathode Current vs Cathode Voltage 150 Vz=VREF TA=25℃ 200 Cathode Current---Iz(mA) Cathode Current---IZ(μA) 300 100 0 -100 Vz=VREF TA=25℃ 100 50 0 -50 -100 -200 -150 -1.5 -300 -1 -0.5 0 0.5 1 -1 -0.5 1.5 0 0.5 1 1.5 Cathode Voltage---Vz(V) Cathode Voltage---Vz(V) Reference Input Current vs Junction Temperature Reference Voltage vs Junction Temperature 150 Reference Input Current---IREF(nA) Reference Voltage---VREF(V) 1.248 Iz=10mA 1.246 1.244 1.242 1.24 1.238 IZ=60μA 1.236 125 100 1.234 -50 0 50 100 -50 -25 0 25 50 75 100 125 150 Junction Temperature---TJ(℃) Off-State Cathode Current vs Junction Temperature Ratio of Delta Reference Voltage to Delta Cathode Voltage vs Junction Temperature 250 Off-State Cathode Current---Iz (off)(nA) ΔVREF/ΔVz---(-mV/V) 75 50 150 Junction Temperature---TJ(℃) 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Iz=10mA R1=10kΩ R2=∞ Iz=10mA ΔVz=16V to VREF VREF=0V Vz=16V 200 150 100 Vz=6V 50 0 -50 -25 0 25 50 75 100 Junction Temperature---TJ(℃) PL432XA3/N3 125 150 -50 -25 0 25 50 75 100 125 150 Junction Temperature---TJ(℃) CYStek Product Specification cystek CYStech Electronics Corp. Reference Impedance vs Frequency Reference Impedance vs Junction Temperature 100 0.5 0.4 0.35 Reference Impedance---rz(Ω) Reference Impedance---rz(Ω) TA=25℃ Iz=0.1 to 100mA Vz=VREF f<1kHz 0.45 0.3 0.25 0.2 0.15 0.1 0.05 -50 -25 0 25 50 75 100 10 1 0.1 1000 0 125 150 10000 100000 1000000 Frequency---f(Hz) Junction Temperature---TJ(℃) Small-Signal Phase Shift vs Frequency Small-Signal Gain vs Frequency -180 Small-Signal Phase Shift---(Deg) 70 60 Small-Signal Gain---AV(dB) Spec. No. : C504A3 Issued Date : 2003.03.21 Revised Date : Page No. : 6/9 50 40 30 20 10 0 -225 -270 -315 -10 -360 -20 100 1000 10000 100000 1000000 Frequency---f(Hz) 100 1000 10000 100000 1000000 Frequency---f(Hz) Stability Boundary Condition For Shunt Regulation vs Cathode Current and Load Capacitance 3.5 TA=25℃ Cathode Current---Iz(mA) 3 2.5 Stable Stable 2 1.5 Vz=VREF 1 0.5 Vz=2V 0 0.001 PL432XA3/N3 0.01 0.1 1 Load Capacitance---CL(μF) 10 CYStek Product Specification cystek Test Circuit-Small-Signal Gain and Phase OUT Test Circuit-Stability R Iz 15k PL432 + 10μF Spec. No. : C504A3 Issued Date : 2003.03.21 Revised Date : Page No. : 7/9 CYStech Electronics Corp. Iz 232 R1 CL PL432 8.25k R2 GND Applications Information - Stability Selection of load capacitance when using PL432 as a shunt regulator When the PL432 is used as a shunt regulator, two options for selection of CL(see diagram on page 6) are recommended for optimal stability: 1) No load capacitance across the device, decouple at the load. 2) Large capacitance across the device, optimal decoupling at the load. The reason for this is that PL432 exhibits instability with capacitances in the range of 10nF to 1μF (approx.) at light cathode currents(up to 3mA typical). The device is less stable the lower the cathode voltage has been set for. Therefore while the device will be perfectly stable operating at a cathode current of (say) 10mA with a 0.1μF capacitor across it, it will oscillate transiently during start-up as the cathode current passes through the instability region. Selecting a very low (or preferably, no) capacitance, or alternatively a high capacitance(such as 10μF) will avoid this issue altogether. Since the user will probably wish to have local decoupling at the load anyway, the most cost effective method is to use no capacitance at all directly across the device. PCB trace/via resistance and inductance prevent the local load decoupling from causing the oscillation during the transient start-up phase. Note : if the PL432 is located right at the load, so the load decoupling capacitor is directly across it, then this capacitor will have to be ≤1nF or ≥10μF. PL432XA3/N3 CYStek Product Specification cystek Spec. No. : C504A3 Issued Date : 2003.03.21 Revised Date : Page No. : 8/9 CYStech Electronics Corp. TO-92 Dimension α2 A Marking: B 1 2 C 432 PL431 3 α3 C D H I G α1 E Style: Pin 1.Reference 2.Anode 3.Cathode F 3-Lead TO-92 Plastic Package CYStek Package Code: A3 *: Typical Inches Min. Max. 0.1704 0.1902 0.1704 0.1902 0.5000 0.0142 0.0220 *0.0500 0.1323 0.1480 DIM A B C D E F Millimeters Min. Max. 4.33 4.83 4.33 4.83 12.70 0.36 0.56 *1.27 3.36 3.76 DIM G H I α1 α2 α3 Inches Min. Max. 0.0142 0.0220 *0.1000 *0.0500 *5° *2° *2° Millimeters Min. Max. 0.36 0.56 *2.54 *1.27 *5° *2° *2° Notes: 1.Controlling dimension: millimeters. 2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.If there is any question with packing specification or packing method, please contact your local CYStek sales office. Material: • Lead: 42 Alloy ; solder plating • Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0 PL432XA3/N3 CYStek Product Specification cystek Spec. No. : C504A3 Issued Date : 2003.03.21 Revised Date : Page No. : 9/9 CYStech Electronics Corp. SOT-23 Dimension Marking: A L 3 B 432 S 2 1 G V 3-Lead SOT-23 Plastic Surface Mounted Package CYStek Package Code: N3 C Style: D K H Pin 1.Reference 3.Anode 2.Cathode J *: Typical Inches Min. Max. 0.1102 0.1204 0.0472 0.0630 0.0335 0.0512 0.0118 0.0197 0.0669 0.0910 0.0005 0.0040 DIM A B C D G H Millimeters Min. Max. 2.80 3.04 1.20 1.60 0.89 1.30 0.30 0.50 1.70 2.30 0.013 0.10 DIM J K L S V Inches Min. Max. 0.0034 0.0070 0.0128 0.0266 0.0335 0.0453 0.0830 0.1083 0.0098 0.0256 Millimeters Min. Max. 0.085 0.177 0.32 0.67 0.85 1.15 2.10 2.75 0.25 0.65 Notes: 1.Controlling dimension: millimeters. 2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.If there is any question with packing specification or packing method, please contact your local CYCtek sales office. Material: • Lead: 42 Alloy; solder plating • Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0 Important Notice: • All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek. • CYStek reserves the right to make changes to its products without notice. • CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems. • CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. PL432XA3/N3 CYStek Product Specification