DS5000(T) DS5000(T) Soft Microcontroller Module FEATURES PIN ASSIGNMENT • 8–bit 8051 compatible Microcontroller adapts to task– at–hand: – 8 or 32K bytes of nonvolatile RAM for program and/or data memory storage – Initial downloading of software in end system via on–chip serial port – Capable of modifying its own program and/or data memory in end use • Crashproof operation: – Maintains all nonvolatile resources for 10 years in the absence of VCC – Power–fail reset – Early warning power–fail interrupt – Watchdog timer • Software Security Feature: – Executes encrypted software to prevent unauthorized disclosure • On–chip, full–duplex serial I/O ports • Two on–chip timer/event counters P1.0 1 40 VCC P1.1 2 39 P0.0 AD0 P1.2 3 38 P0.1 AD1 P1.3 4 37 P0.2 AD2 P1.4 5 36 P0.3 AD3 P1.5 6 35 P0.4 AD4 P1.6 7 P0.5 AD5 P1.7 8 9 34 33 32 P0.7 AD7 RST P0.6 AD6 RXD P3.0 10 31 EA TXD P3.1 11 30 ALE INT0 P3.2 12 29 PSEN INT1 P3.3 13 28 P2.7 A15 T0 P3.4 14 27 P2.6 A14 T1 P3.5 26 P2.5 A13 WR P3.6 15 16 25 P2.4 A12 RD P3.7 17 24 P2.3 A11 XTAL2 18 23 P2.2 A10 XTAL1 19 22 P2.1 A9 GND 20 21 P2.0 A8 40–PIN ENCAPSULATED PACKAGE • 32 parallel I/O lines • Compatible with industry standard 8051 instruction set and pinout • Optional Permanently Powered Real–Time Clock (DS5000T) DESCRIPTION The DS5000(T) Soft Microcontroller Module is a fully 8051 compatible 8–bit CMOS microcontroller that offers “softness” in all aspects of its application. This is accomplished through the comprehensive use of nonvolatile technology to preserve all information in the absence of system VCC. The internal program/data memory space is implemented using either 8K or 32K bytes of nonvolatile CMOS SRAM. Furthermore, internal data registers and key configuration registers are also nonvolatile. An optional real time clock gives permanently powered timekeeping. The clock keeps time to a hundredth of a second using an on–board crystal. 021998 1/19 DS5000(T) ORDERING INFORMATION PART NUMBER RAM SIZE MAX CRYSTAL SPEED TIMEKEEPING? DS5000–8–16 8K bytes 16 MHz No DS5000–32–16 32K bytes 16 MHz No DS5000–8–16 8K bytes 16 MHz Yes DS5000T–32–16 32K bytes 16 MHz Yes Operating information is contained in the User’s Guide section of the Secure Microcontroller Data Book. This data sheet provides ordering information, pinout, and electrical specification. DS5000(T) BLOCK DIAGRAM Figure 1 DS5000(T) VCC ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ VCCO P0.0–0.7 P2.0–2.7 P3.0–3.7 ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ BYTE–WIDE ADDRESS BUS P1.0–1.7 BYTE–WIDE DATA BUS DS5000FP CE1 RST R/W ALE PSEN EA XTAL1 XTAL2 CE2 GND +3V 021998 2/19 8K OR 32K SRAM (DS5000T) REAL TIME CLOCK DS5000(T) PIN DESCRIPTION PIN NUMBER 1–8 DESCRIPTION 1 P1.0 – P1.7. General purpose I/O Port 1. 9 RST – Active high reset input. A logic 1 applied to this pin will activate a reset state. This pin is pulled down internally so this pin can be left unconnected if not used. 10 P3.0 RXD. General purpose I/O port pin 3.0. Also serves as the receive signal for the on board UART. This pin should not be connected directly to a PC COM port. 11 P3.1 TXD. General purpose I/O port pin 3.1. Also serves as the transmit signal for the on board UART. This pin should not be connected directly to a PC COM port. 12 P3.2 INT0. General purpose I/O port pin 3.2. Also serves as the active low External Interrupt 0. 13 P3.3 INT1. General purpose I/O port pin 3.3. Also serves as the active low External Interrupt 1. 14 P3.4 T0. General purpose I/O port pin 3.4. Also serves as the Timer 0 input. 15 P3.5 T1. General purpose I/O port pin 3.5. Also serves as the Timer 1 input. 16 P3.6 WR. General purpose I/O port pin. Also serves as the write strobe for Expanded bus operation. 17 P3.7 RD. General purpose I/O port pin. Also serves as the read strobe for Expanded bus operation. 18, 19 XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is the input to an inverting amplifier and XTAL2 is the output. 20 GND. Logic ground. 21–28 P2.0–P2.7. General purpose I/O Port 2. Also serves as the MSB of the Expanded Address bus. 29 PSEN – Program Store Enable. This active low signal is used to enable an external program memory when using the Expanded bus. It is normally an output and should be unconnected if not used. PSEN also is used to invoke the Bootstrap Loader. At this time, PSEN will be pulled down externally. This should only be done once the DS5000(T) is already in a reset state. The device that pulls down should be open drain since it must not interfere with PSEN under normal operation. 30 ALE – Address Latch Enable. Used to de–multiplex the multiplexed Expanded Address/Data bus on Port 0. This pin is normally connected to the clock input on a ’373 type transparent latch. When using a parallel programmer, this pin also assumes the PROG function for programming pulses. 31 EA – External Access. This pin forces the DS5000(T) to behave like an 8031. No internal memory (or clock) will be available when this pin is at a logic low. Since this pin is pulled down internally, it should be connected to +5V to use NV RAM. In a parallel programmer, this pin also serves as VPP for super voltage pulses. 021998 3/19 DS5000(T) PIN NUMBER 32–39 40 DESCRIPTION P0.7–P0.0. General purpose I/O Port 0. This port is open–drain and can not drive a logic 1. It requires external pull–ups. Port 0 is also the multiplexed Expanded Address/Data bus. When used in this mode, it does not require pull–ups. VCC – +5 volts. INSTRUCTION SET The DS5000(T) executes an instruction set which is object code compatible with the industry standard 8051 microcontroller. As a result, software development packages which have been written for the 8051 are compatible with the DS5000(T), including cross–assemblers, high–level language compilers, and debugging tools. A complete description for the DS5000(T) instruction set is available in the User’s Guide section of the Secure Microcontroller Data Book. MEMORY ORGANIZATION Figure 2 illustrates the address spaces which are accessed by the DS5000(T). As illustrated in the figure, separate address spaces exist for program and data 021998 4/19 memory. Since the basic addressing capability of the machine is 16 bits, a maximum of 64K bytes of program memory and 64K bytes of data memory can be accessed by the DS5000(T) CPU. The 8K or 32K byte RAM area inside of the DS5000(T) can be used to contain both program and data memory. The Real time Clock (RTC) in the DS5000T is reached in the memory map by setting a SFR bit. The MCON.2 bit (ECE2) is used to select an alternate data memory map. While ECE2=1, all MOVXs will be routed to this alternate memory map. The real time clock is a serial device that resides in this area. A full description of the RTC access and example software is given in the User’s Guide section of the Secure Microcontroller Data Book. If the ECE2 bit is set on a DS5000 without a timekeeper, the MOVXs will simply go to a nonexistent memory. Software execution would not be affected otherwise. DS5000(T) ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÏÏÏÏÏ ÎÎÎÎÎ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ DS5000(T) LOGICAL ADDRESS SPACES Figure 2 127 64K – 32K – 32K – 8K – 8K – NV RAM PROGRAM MEMORY 255 128 0 0 DATA REGISTERS SPECIAL FUNCTION REGISTERS ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÏÏÏÏÏ ÎÎÎÎÎ ÏÏÏÏÏ ÏÏÏÏÏ ÎÎÎÎÎ ÏÏÏÏÏ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ 64K – PROGRAM MEMORY RANGE ADDR. NV RAM DATA MEMORY PARTITION ADDR. 0 DATA MEMORY INTERNAL REGISTERS LEGEND: = ON–CHIP REGISTERS ÏÏ ÏÏ ÎÎ ÎÎ = ACCESSED VIA EXPANDED BUS = NV RAM MEMORY PROGRAM LOADING The Program Load Modes allow initialization of the NV RAM Program/Data Memory. This initialization may be performed in one of two ways: 1. Serial Program Loading which is capable of performing Bootstrap Loading of the DS5000(T). This feature allows the loading of the application program to be delayed until the DS5000(T) is installed in the end system. Dallas Semiconductor strongly recommends the use of serial program loading because of its versatility and ease of use. The DS5000(T) is placed in its Program Load configuration by simultaneously applying a logic 1 to the RST pin and forcing the PSEN line to a logic 0 level. Immediately following this action, the DS5000(T) will look for a parallel Program Load pulse, or a serial ASCII carriage return (0DH) character received at 9600, 2400, 1200, or 300 bps over the serial port. The hardware configurations used to select these modes of operation are illustrated in Figure 3. 2. Parallel Program Load cycles which perform the initial loading from parallel address/data information presented on the I/O port pins. This mode is timing– set compatible with the 8751H microcontroller programming mode. 021998 5/19 DS5000(T) PROGRAM LOADING CONFIGURATIONS Figure 3 VCC GND VCC DS5000 PROGRAM ADDRESS A7–A0 P1.7– P1.0 P0.7– P0.0 A11–A8 P2.3– P2.0 P3.7– P3.4 D7–D0 PROGRAM DATA IN/VERIFY DATA OUT A15–A12 PROGRAM ADDRESS EA/VPP P1.7– P1.0 P0.7– P0.0 P2.5– P2.0 P3.7– P3.2 P2.6 ALE/PROG PROGRAM CONTROL GND DS5000 TXD P2.7 RXD DRIVE/ RS232C RCV P2.7 P2.6 R<2K P2.5 XTAL1 R<2K RST PSEN XTAL1 11.059 MHz XTAL2 SERIAL BOOTSTRAP LOADER The Serial Program Load Mode is the easiest, fastest, most reliable, and most complete method of initially loading application software into the DS5000(T) nonvolatile RAM. Communication can be performed over a standard asynchronous serial communications port. A typical application would use a simple RS232C serial interface to program the DS5000(T) as a final production procedure. The hardware configuration which is required for the Serial Program Load mode is illustrated in Figure 3. Port pins 2.7 and 2.6 must be either open or pulled high to avoid placing the DS5000(T) in a parallel load cycle. Although an 11.0592 MHz crystal is shown in Figure 3, a variety of crystal frequencies and loader baud rates are supported, shown in Table 2. The serial loader is designed to operate across a three–wire interface from a standard UART. The receive, transmit, and ground wires are all that are necessary to establish communication with the DS5000(T). The Serial Bootstrap Loader implements an easy–to– use command line interface which allows an application 021998 6/19 PSEN XTAL2 PARALLEL LOADING Table 1 summarizes the selection of the available Parallel Program Load cycles. The timing associated with these cycles is illustrated in the electrical specs. RST SERIAL LOADING program in an Intel hex representation to be loaded into and read back from the device. Intel hex is the typical format which existing 8051 cross–assemblers output. The serial loader responds to single character commands which are summarized below: COMMAND C D F K L R T U V W Z P G FUNCTION Return CRC–16 checksum of embedded RAM Dump Intel Hex File Fill embedded RAM block with constant Load 40–bit Encryption Key Load Intel Hex File Read MCON register Trace (Echo) incoming Intel Hex data Clear Security Lock Verify Embedded RAM with incoming Intel Hex Write MCON register Set Security Lock Put a value to a port Get a value from a port DS5000(T) PARALLEL PROGRAM LOAD CYCLES Table 1 MODE RST PSEN PROG EA P2.7 P2.6 P2.5 Program 1 0 0 VPP 1 0 X Security Set 1 0 0 VPP 1 1 X Verify 1 X X 1 0 0 X Prog Expanded 1 0 0 VPP 0 1 0 Verify Expanded 1 0 1 1 0 1 0 Prog MCON or Key registers 1 0 0 VPP 0 1 1 Verify MCON registers 1 0 1 1 0 1 1 The Parallel Program Cycle is used to load a byte of data into a register or memory location within the DS5000(T). The Verify Cycle is used to read this byte back for comparison with the originally loaded value to verify proper load ing. The Security Set Cycle may be used to enable and the Software Security feature of the DS5000(T). One may also enter bytes for the MCON register or for the five encryption registers using the Program MCON cycle. When using this cycle, the absolute register address must be presented at Ports 1 and 2 as in the normal program cycle (Port 2 should be 00H). The MCON contents can likewise be verified using the Verify MCON cycle. When the DS5000(T) first detects a Parallel Program Strobe pulse or a Security Set Strobe pulse while in the Program Load Mode following a Power–On Reset, the internal hardware of the DS5000(T) is initialized so that an existing 4K byte program can be programmed into a DS5000(T) with little or no modification. This initialization automatically sets the Range Address for 8K bytes and maps the lowest 4K byte bank of Embedded RAM as program memory. The next 4K bytes of Embedded RAM are mapped as Data Memory. In order to program more than 4K bytes of program code, the Program/Verify Expanded cycles can be used. Up to 32K bytes of program code can be entered and verified. Note that the expanded 32K byte Program/ Verify cycles take much longer than the normal 4K byte Program/Verify cycles. A typical parallel loading session would follow this procedure. First, set the contents of the MCON register with the correct range and partition only if using expanded programming cycles. Next, the encryption registers can be loaded to enable encryption of the program/data memory (not required). Then, program the DS5000(T) using either normal or expanded program cycles and check the memory contents using Verify cycles. The last operation would be to turn on the security lock feature by either a Security Set cycle or by explicitly writing to the MCON register and setting MCON.0 to a 1. 021998 7/19 DS5000(T) SERIAL LOADER BAUD RATES FOR DIFFERENT CRYSTAL FREQUENCIES Table 2 BAUD RATE CRYSTAL FREQ (MHz) 300 14.7456 1200 2400 9600 19200 Y Y Y Y Y 11.0592 Y Y Y Y 9.21600 Y Y Y Y 7.37280 Y Y Y Y 5.52960 Y Y Y Y 1.84320 Y Y Y Y ADDITIONAL INFORMATION A complete description for all operational aspects of the DS5000(T), is provided in the User’s Guide section of the Secure Microcontroller Data Book. DEVELOPMENT SUPPORT Dallas Semiconductor offers a kit package for developing and testing user code. The DS5000TK Evaluation 021998 8/19 57600 Y Kit allows the user to download Intel hex formatted code directly to the DS5000(T) from a PC–XT/AT or compatible computer. The kit consists of a DS5000T–32, an interface pod, demo software, and an RS232 connector that attaches to the COM1 or COM2 serial port of a PC. See the Development Tools section of the Secure Microcontroller Data Book for further details. DS5000(T) ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature –0.3V to +7.0V 0°C to 70°C –40°C to +70°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC CHARACTERISTICS PARAMETER (tA = 0°C to70°C; VCC = 5V + 5%) SYMBOL MIN Input Low Voltage VIL Input High Voltage Input High Voltage RST, XTAL1 Output Low Voltage @ IOL=1.6 mA (Ports 1, 2, 3) VOL1 Output Low Voltage @ IOL=3.2 mA (Ports 0, ALE, PSEN) VOL2 Output High Voltage @ IOH=–80 µA (Ports 1, 2, 3) VOH1 2.4 Output High Voltage @ IOH=–400 µA (Ports 0, ALE, PSEN) VOH2 2.4 TYP MAX UNITS NOTES –0.3 0.8 V 1 VIH1 2.0 VCC +0.3 V 1 VIH2 3.5 VCC +0.3 V 1 0.15 0.45 V 0.15 0.45 V 1 4.8 V 1 4.8 V 1 Input Low Current VIN = 0.45V (Ports 1, 2, 3) IIL –50 µA Transition Current; 1 to 0 VIN = 2.0V (Ports 1, 2, 3) ITL –500 µA Input Leakage Current 0.45 < VIN < VCC (Port 0) IL +10 µA 125 KΩ 80 µA 4 RST, EA Pulldown Resistor RRE Stop Mode Current ISM 40 Power–Fail Warning Voltage VPFW 4.15 4.6 4.75 V 1 Minimum Operating Voltage 4.5 4.65 V 1 13 V 1 VCCmin 4.05 Programming Supply Voltage (Parallel Program Mode) VPP 12.5 Program Supply Current IPP 15 20 mA Operating Current DS5000–8K@8 MHz DS5000–32K @ 12 MHz DS5000T–32–16 @ 16 MHz ICC 25.2 35.7 45.6 43 48 54 mA 2 Idle Mode Current @ 12 MHz ICC 4.5 6.2 mA 3 021998 9/19 DS5000(T) AC CHARACTERISTICS EXPANDED BUS MODE TIMING SPECIFICATIONS SYMBOL (tA = 0°C to70°C; VCC = 5V + 5%) # PARAMETER MIN MAX UNITS 1 Oscillator Frequency 2 ALE Pulse Width 1/tCLK 1.0 16 MHz tALPW 2tCLK –40 ns 3 4 Address Valid to ALE Low tAVALL tCLK –40 ns Address Hold After ALE Low tAVAAV tCLK –35 ns 5 ALE Low to Valid Instr. In 6 ALE Low to PSEN Low 7 PSEN Pulse Width 8 PSEN Low to Valid Instr. In 9 Input Instr. Hold after PSEN Going High 10 Input Instr. Float after PSEN Going High tPSIX 11 Address Hold after PSEN Going High tPSAV 12 Address Valid to Valid Instr. In @12 MHz @16 MHz tAVVI 13 PSEN Low to Address Float tPSLAZ 0 ns 14 RD Pulse Width tRDPW 6tCLK –100 ns 15 WR Pulse Width tWRPW 6tCLK –100 16 RD Low to Valid Data In 17 Data Hold after RD High tRDHDV 18 Data Float after RD High tRDHDZ 2tCLK –70 ns 19 ALE Low to Valid Data In @12 MHz @16 MHz tALLVD 8CLK –150 8tCLK –90 ns ns 20 Valid Addr. to Valid Data In @12 MHz @16 MHz tAVDV 9tCLK –165 9tCLK –105 ns ns 21 ALE Low to RD or WR Low 3tCLK +50 ns 22 23 24 Data Valid to WR High @12 MHz @16 MHz @12 MHz @16 MHz @12 MHz @16 MHz tALLVI 4tCLK –150 4tCLK –90 tALLPSL tCLK –25 tPSPW 3tCLK –35 tPSLVI tPSIV ns ns 3tCLK –150 3tCLK –90 0 ns ns ns tCLK –20 tCLK –8 ns ns 5tCLK –150 5tCLK –90 tRDLDV ns ns ns ns ns 5tCLK –165 5tCLK –105 0 ns ns ns tALLRDL 3tCLK –50 Address Valid to RD or WR Low tAVRDL 4tCLK –130 ns Data Valid to WR Going Low tDVWRL tCLK –60 ns tDVWRH 7tCLK –150 7tCLK –90 ns @12 MHz @16 MHz 25 Data Valid after WR High tWRHDV 26 RD Low to Address Float tRDLAZ 27 RD or WR High to ALE High 021998 10/19 tRDHALH ns tCLK –50 tCLK –40 ns 0 ns tCLK +50 ns DS5000(T) EXPANDED PROGRAM MEMORY READ CYCLE 2 ALE 6 7 5 8 11 PSEN 13 PORT 0 10 9 3 4 A7–A0 INSTR IN A7–A0 12 PORT 2 A15–A8 A15–A8 EXPANDED DATA MEMORY READ CYCLE 27 ALE PSEN 19 21 14 RD 16 18 3 PORT 0 26 4 A7–A0 (Rn OR DPL) 17 DATA IN A7–A0 (PCL) INSTR IN 22 20 PORT 2 P2.7–P2.0 OR A15–A8 FROM DPH A15–A8 FROM PCH 021998 11/19 DS5000(T) EXPANDED DATA MEMORY WRITE CYCLE 27 ALE PSEN 21 15 WR 23 PORT 0 25 4 3 24 A7–A0 (Rn OR DPL) A7–A0 (PCL) DATA OUT 22 PORT 2 P2.7–P2.0 OR A15–A8 FROM PDH A15–A8 FROM PCH EXTERNAL CLOCK TIMING 28 29 30 31 1 021998 12/19 INSTR IN DS5000(T) AC CHARACTERISTICS (cont’d) EXTERNAL CLOCK DRIVE # PARAMETER 28 External Clock High Time 29 (tA = 0°C to70°C; VCC = 5V + 5%) SYMBOL MIN @12 MHz @16 MHz tCLKHPW 20 15 ns ns External Clock Low Time @12 MHz @16 MHz tCLKLPW 20 15 ns ns 30 External Clock Rise Time @12 MHz @16 MHz tCLKR 20 15 ns ns 31 External Clock Fall Time @12 MHz @16 MHz tCLKF 20 15 ns ns AC CHARACTERISTICS (cont’d) SERIAL PORT TIMING – MODE 0 # PARAMETER 35 MAX UNITS (tA = 0°C to70°C; VCC = 5V + 5%) SYMBOL MIN MAX UNITS Serial Port Cycle Time tSPCLK 12tCLK µs 36 Output Data Setup to Rising Clock Edge tDOCH 10tCLK –133 ns 37 Output Data Hold after Rising Clock Edge tCHDO 2tCLK –117 ns 38 Clock Rising Edge to Input Data Valid tCHDV 39 Input Data Hold after Rising Clock Edge tCHDIV 10tCLK –133 ns 0 ns SERIAL PORT TIMING – MODE 0 INSTRUCTION 0 1 2 3 4 5 6 7 8 ALE 35 CLOCK 36 37 DATA OUT 0 1 2 3 4 5 6 7 SET TI WRITE TO SBUF REGISTER 39 38 INPUT DATA SET RI VALID VALID VALID VALID VALID VALID VALID CLEAR RI 021998 13/19 DS5000(T) AC CHARACTERISTICS (cont’d) POWER CYCLING TIMING (tA = 0°C to70°C; VCC = 5V + 5%) # PARAMETER SYMBOL MIN tF 40 MAX 32 Slew Rate from VCCmin to 3.3V 33 Crystal Start up Time tCSU (note 5) 34 Power–On Reset Delay tPOR 21504 UNITS µs tCLK POWER CYCLE TIMING VCC VPFW VCCMIN VLI 32 INTERRUPT SERVICE ROUTINE 33 CLOCK OSC 34 INTERNAL RESET LITHIUM CURRENT 021998 14/19 DS5000(T) AC CHARACTERISTICS (cont’d) PARALLEL PROGRAM LOAD TIMING # PARAMETER 40 (tA = 0°C to70°C; VCC = 5V + 5%) SYMBOL MIN MAX UNITS Oscillator Frequency 1/tCLK 1.0 12.0 MHz 41 Address Setup to PROG Low tAVPRL 0 42 Address Hold after PROG High tPRHAV 0 43 Data Setup to PROG Low tDVPRL 0 44 Data Hold after PROG High tPRHDV 0 45 P2.7, 2.6, 2.5 Setup to VPP tP27HVP 0 46 VPP Setup to PROG Low tVPHPRL 0 47 VPP Hold after PROG Low tPRHVPL 0 48 PROG Width Low tPRW 2400 49 Data Output from Address Valid tAVDV 48 1800* tCLK 50 Data Output from P2.7 Low tDVP27L 48 1800* tCLK 51 Data Float after P2.7 High tP27HDZ 0 48 1800* tCLK 52 Delay to Reset/PSEN Active after Power–On tPORPV 21504 tCLK 53 Reset/PSEN Active (or Verify Inactive) to VPP High tRAVPH 1200 tCLK 54 VPP Inactive (Between Program Cycles) tVPPPC 1200 tCLK 55 Verify Active Time tVFT 48 2400* tCLK tCLK * Second set of numbers refers to expanded memory programming up to 32K bytes. 021998 15/19 DS5000(T) PARALLEL PROGRAM LOAD TIMING P2.3–P2.0 P1.7–P1.0 ADDRESS 41 ADDRESS ADDRESS 42 49 DATA PORT DATA DATA 44 43 ALE/PROG 51 47 46 48 54 VPP EA/VPP VIH 45 50 53 P2.7, P2.6, P2.5 ACTIVE 55 +5V VCC 52 53 RST PSEN CAPACITANCE PARAMETER (test frequency = 1 MHz; tA = 25°C) SYMBOL MIN TYP MAX UNITS Output Capacitance CO 10 pF Input Capacitance CI 10 pF 021998 16/19 NOTES DS5000(T) DS5000(T) TYPICAL ICC VS. FREQUENCY 45.0 16 MHz 40.0 12 MHz 35.0 30.0 8 MHz Icc CURRENT (mA) 25.0 NORMAL OPERATION 20.0 15.0 10.0 IDLE MODE OPERATION 5.0 0 0.0 5.0 10.0 15.0 FREQUENCY OF OPERATION (MHz) (VCC=+5V, tA=25°C) Normal operation is measured using: 1) 2) 3) 4) External crystals on XTAL1 and 2 All port pins disconnected RST=0 volts and EA=VCC Part performing endless loop writing to internal memory. Idle mode operation is measured using: 1) 2) 3) 4) External clock source at XTAL1; XTAL2 floating All port pins disconnected RST=0 volts and EA=VCC Part set in IDLE mode by software. 021998 17/19 DS5000(T) NOTES: 1. All voltages are referenced to ground. 2. Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF=10 ns, VIL = 0.5V; XTAL2 disconnected; EA = RST = PORT0 = VCC. 3. Idle mode ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF = 10 ns, VIL = 0.5V; XTAL2 disconnected; EA = PORT0 = VCC, RST = VSS. 4. Stop mode ICC is measured with all output pins disconnected; EA = PORT0 = VCC; XTAL2 not connected; RST = VSS. 5. Crystal start–up time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit until the first clock pulse is produced by the on–chip oscillator. The user should check with the crystal vendor for the worst case spec on this time. PACKAGE DRAWING INCHES A DIM MIN MAX A IN. 2.080 2.100 B IN. 0.680 0.700 C IN. 0.290 0.325 D IN. 0.090 0.110 E IN. 0.030 0.060 F IN. 0.145 0.185 G IN. 0.016 0.020 H IN. 0.590 0.610 I IN. 0.009 0.015 1 E C G F 1.900 B I H 021998 18/19 D DS5000(T) DATA SHEET REVISION SUMMARY The following represent the key differences between the dates 07/20/95 to 07/24/96 of the DS5000(T) data sheet. Please review this summary carefully. 1. Correct Figure 3 to show RST active high. 2. Add Data Sheet Revision Summary. 021998 19/19