3D3521 data 3 delay devices, inc. MONOLITHIC MANCHESTER ENCODER (SERIES 3D3521) FEATURES • • • • • • • PACKAGES All-silicon, low-power CMOS technology 3.3V operation CMOS compatible inputs and outputs Vapor phase, IR and wave solderable Auto-insertable (DIP pkg.) Low ground bounce noise Maximum data rate: 50 MBaud CLK 1 8 VDD RESB 2 7 N/C DAT 3 6 TXB GND 3D3521M 3D3521H 3D3521Z 4 5 TX DIP (.300) Gull Wing (.300) SOIC (.150) CLK 1 14 VDD N/C 2 13 N/C N/C 3 12 N/C RESB 4 11 N/C DAT 5 10 N/C N/C 6 9 TXB GND 7 8 TX 3D3521 DIP (.300) 3D3521G Gull Wing (.300) 3D3521D SOIC (.150) For mechanical dimensions, click here. For package marking details, click here. FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS The 3D3521 is a monolithic CMOS Manchester Encoder. The clock and data, present at the unit input, are combined into a single bi-phaselevel signal. In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is represented by a low-to-high transition. The unit operating baud rate (in Mbaud) is equal to the input clock frequency (in MHZ). All pins marked N/C must be left unconnected. DAT CLK RESB TX TXB VDD GND Data Input Clock Input Reset Signal Output Inverted Signal Output +3.3 Volts Ground The all-CMOS 3D3521 integrated circuit has been designed as a reliable, economic alternative to hybrid Manchester Encoders. It is CMOS-compatible and is offered in standard 8-pin and 14-pin auto-insertable DIPs and space saving surface mount 8-pin and 14-pin SOICs. Doc #06004 5/8/2006 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 1 3D3521 APPLICATION NOTES The 3D3521 Manchester Encoder samples the data input at the rising edge of the input clock. The sampled data is used in conjunction with the clock rising and falling edges to generate the byphase level Manchester code. OUTPUT SIGNAL CHARACTERISTICS The 3D3521 presents at its outputs the true and the complimented encoded data. The High-to-Low time skew of the selected data output should be budgeted by the user, as it relates to his application, to satisfactorily estimate the distortion of the transmitted data stream. INPUT SIGNAL CHARACTERISTICS The 3D3521 Manchester Encoder inputs are CMOS compatible. The user should assure himself that the 50% (of VDD) threshold is used when referring to all timing, especially to the input clock duty cycle. Such an estimate is very useful in determining the functionality and margins of the data link, if a 3D3522 Manchester Decoder is used to decode the received data. CLOCK DUTY CYCLE ERRORS The 3D3521 Manchester Encoder employs the timing of the clock rising and falling edges (duty cycle) to implement the required coding scheme. To reduce the difference between the output data high time and low time, it is essential that the deviation of the input clock duty cycle from 50/50 be minimized. RESET (RESB) POWER SUPPLY AND TEMPERATURE CONSIDERATIONS CMOS integrated circuitry is strongly dependent on power supply and temperature. The monolithic 3D3521 Manchester encoder utilizes novel and innovative compensation circuitry to minimize timing variations induced by fluctuations in power supply and/or temperature. Power-on reset (Left high for normal operation) 1/fC 1 0 1 1 0 0 1 0 CLOCK (CIN) tDS tDH DATA (DIN) T2H T2L TRANSMIT (TXB) T1H TRANSMIT (TX) 1 0 1 1 0 T1L 0 1 0 Figure 1: Timing Diagram Doc #06004 5/8/2006 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 2 3D3521 DEVICE SPECIFICATIONS TABLE 1: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature SYMBOL VDD VIN IIN TSTRG TLEAD MIN -0.3 -0.3 -10 -55 MAX 7.0 VDD+0.3 10 150 300 UNITS V V mA C C NOTES 25C 10 sec TABLE 2: DC ELECTRICAL CHARACTERISTICS (-40C to 85C, 3.0V to 3.6V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current SYMBOL IDD VIH VIL IIH IIL IOH MIN Low Level Output Current IOL 4.0 Output Rise & Fall Time MAX 5 2.0 1.0 1.0 1.0 -4.0 mA TR & TF 2 *IDD(Dynamic) = 2 * CLD * VDD * F where: CLD = Average capacitance load/pin (pf) F = Input frequency (GHz) UNITS mA V V µA µA mA ns NOTES VIH = VDD VIL = 0V VDD = 3.0V VOH = 2.4V VDD = 3.0V VOL = 0.4V CLD = 5 pf Input Capacitance = 10 pf typical Output Load Capacitance (CLD) = 25 pf max TABLE 3: AC ELECTRICAL CHARACTERISTICS (-40C to 85C, 3.0V to 3.6V) PARAMETER Input Baud Rate Clock Frequency Data set-up to clock rising Data hold from clock rising TX High-Low time skew TXB High-Low time skew TX - TXB High/Low time skew SYMBOL MIN fBN fC tDS tDH t1H - t1L t2H - t2L t1H - t2L 3.5 0 -3.5 -2.0 -3.0 TYP MAX 50 50 3.5 2.0 3.0 UNITS MBaud MHz ns ns ns ns ns NOTES 1 1 1 Notes: 1: Assumes a 50% duty cycle clock input Doc #06004 5/8/2006 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 3 3D3521 SILICON DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: Ambient Temperature: 25oC ± 3oC Supply Voltage (Vcc): 5.0V ± 0.1V Input Pulse: High = 3.0V ± 0.1V Low = 0.0V ± 0.1V Source Impedance: 50Ω Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) Pulse Width: PWIN = 1/(2*BAUD) Period: PERIN = 1/BAUD OUTPUT: Rload: Cload: Threshold: 10KΩ ± 10% 5pf ± 10% 1.5V (Rising & Falling) Device Under Test Digital Scope 10KΩ 5pf 470Ω NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. PRINTER COMPUTER SYSTEM WAVEFORM GENERATOR OUT IN TRIG DEVICE UNDER TEST (DUT) OUT IN DIGITAL SCOPE TRIG Figure 2: Test Setup PERIN PW IN tRISE INPUT SIGNAL tFALL VIH 2.4V 1.5V 0.6V 2.4V 1.5V 0.6V tPLH OUTPUT SIGNAL VIL tPHL 1.5V VOH 1.5V VOL Figure 3: Timing Diagram Doc #06004 5/8/2006 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 4