3D3522 data 3 delay devices, inc. MONOLITHIC MANCHESTER DECODER (SERIES 3D3522) FEATURES • • • • • • • • PACKAGES All-silicon, low-power CMOS technology 3.3V operation CMOS compatible inputs and outputs Vapor phase, IR and wave solderable Auto-insertable (DIP pkg.) Low ground bounce noise Maximum data rate: 50 MBaud Data rate range: ±15% RX 1 14 VDD N/C 2 13 N/C N/C 3 12 N/C VDD CLK 4 11 N/C N/C 5 10 N/C N/C 6 9 N/C GND 7 8 DATB RX 1 CLK 2 7 N/C N/C 3 6 N/C GND 4 8 5 DATB 3D3522-xxx DIP (.300) 3D3522G-xxx Gull Wing (.300) 3D3522D-xxx SOIC (.150) 3D3522M-xxx DIP (.300) 3D3522H-xxx Gull Wing (.300) 3D3522Z-xxx SOIC (.150) For mechanical dimensions, click here. For package marking details, click here. FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS The 3D3522 product family consists of monolithic CMOS Manchester RX Signal Input Decoders. The unit accepts at the RX input a bi-phase-level, CLK Signal Output (Clock) embedded-clock signal. In this encoding mode, a logic one is DATB Signal Output (Data) represented by a high-to-low transition within the bit cell, while a logic VDD +3.3 Volts zero is represented by a low-to-high transition. The recovered clock GND Ground and data signals are presented on CLK and DATB, respectively, with the data signal inverted. The operating baud rate (in MBaud) is specified by the dash number. The input baud rate may vary by as much as ±15% from the nominal device baud rate without compromising the integrity of the information received. Because the 3D3522 is not PLL-based, it does not require a long preamble in order to lock onto the received signal. Rather, the device requires at most one bit cell before the data presented at the output is valid. This is extremely useful in cases where the information arrives in bursts and the input is otherwise turned off. The all-CMOS 3D3522 integrated circuit has been designed as a reliable, economic alternative to hybrid Manchester Decoders. It is CMOS-compatible and is offered in standard 8-pin and 14-pin auto-insertable DIPs and space saving surface mount 8-pin and 14-pin SOICs. TABLE 1: PART NUMBER SPECIFICATIONS PART NUMBER 3D3522-0.5 3D3522-1 3D3522-5 3D3522-10 3D3522-20 3D3522-25 3D3522-50 BAUD RATE (MBaud) Nominal Minimum Maximum 0.50 1.00 5.00 10.00 20.00 25.00 50.00 0.43 0.85 4.25 8.50 17.00 21.25 42.50 0.57 1.15 5.75 11.50 23.00 28.75 57.50 NOTES: Any baud rate between 0.5 and 50 MBaud not shown is also available at no extra cost. 2006 Data Delay Devices Doc #06005 5/8/2006 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 1 3D3522 APPLICATION NOTES The 3D3522 Manchester Decoder samples the input at precise pre-selected intervals to retrieve the data and to recover the clock from the received data stream. Its architecture comprises finely tuned delay elements and proprietary circuitry which, in conjunction with other circuits, implement the data decoding and clock recovery function. OUTPUT SIGNAL CHARACTERISTICS The 3D3522 presents at its outputs the decoded data (inverted) and the recovered clock. The decoded data is valid at the rising edge of the clock. The clock recovery function operates in two modes dictated by the input data stream bit sequence. When a data bit is succeeded by its inverse, the clock recovery circuit is engaged and forces the clock output low for a time equal to one over twice the baud rate. Otherwise, the input is presented at the clock output unchanged, shifted in time. INPUT SIGNAL CHARACTERISTICS Encoded data transmitted from a source arrives at its destination corrupted. Such corruption of the received data manifests itself as jitter and/or pulse width distortion at the input to the device. The instantaneous deviations from nominal Baud Rate and/or Pulse Width (high or low) adversely impact the data extraction and clock recovery function if their published limits are exceeded. See Table 4, Allowed Baud Rate/Duty Cycle. When engaged, the clock recovery circuit generates a low-going pulse of fixed width. Therefore, the clock duty cycle is strongly dependent on the baud rate, as this will affect the clock-high duration. The 3D3522 Manchester Decoder Data Input is CMOS compatible. The user should assure that the 50% (of VDD) threshold is used when referring to all timing, especially the input pulse widths. The clock output falling edge is not operated on by the clock recovery circuitry. It, therefore, preserves more accurately the clock frequency information embedded in the transmitted data. Therefore, it can be used, if it is desired, to retrieve clock frequency information. FREQUENCY (JITTER) ERRORS POWER SUPPLY AND TEMPERATURE CONSIDERATIONS The 3D3522 Manchester Decoder, being a selftimed device, is tolerant of frequency modulation (jitter) present in the input data stream, provided that the input data pulse width variations remain within the allowable ranges. ENCODED 0 1 0 CMOS integrated circuitry is strongly dependent on power supply and temperature. The monolithic 3D3522 Manchester Decoder utilizes novel and innovative compensation circuitry to minimize timing variations induced by fluctuations in power supply and/or temperature. . 1 1 0 0 1 RECEIVED (RX) tC tCL tCWL tCD CLOCK (CLK) DATA (DATB) DECODED 1 0 1 1 0 0 1 Figure 1: Timing Diagram Doc #06005 5/8/2006 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 2 3D3522 DEVICE SPECIFICATIONS TABLE 2: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature SYMBOL VDD VIN IIN TSTRG TLEAD MIN -0.3 -0.3 -10 -55 MAX 7.0 VDD+0.3 10 150 300 UNITS V V mA C C NOTES 25C 10 sec TABLE 3: DC ELECTRICAL CHARACTERISTICS (-40C to 85C, 3.0V to 3.6V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current SYMBOL IDD VIH VIL IIH IIL IOH MIN Low Level Output Current IOL 4.0 Output Rise & Fall Time MAX 5 2.0 1.0 1.0 1.0 -4.0 TR & TF UNITS mA V V µA µA mA mA 2 *IDD(Dynamic) = 2 * CLD * VDD * F where: CLD = Average capacitance load/pin (pf) F = Input frequency (GHz) ns NOTES VIH = VDD VIL = 0V VDD = 3.0V VOH = 2.4V VDD = 3.0V VOL = 0.4V CLD = 5 pf Input Capacitance = 10 pf typical Output Load Capacitance (CLD) = 25 pf max TABLE 4: AC ELECTRICAL CHARACTERISTICS (-40C to 85C, 3.0V to 3.6V, except as noted) PARAMETER Nominal Input Baud Rate Allowed Input Baud Rate Deviation SYMBOL fBN fB MIN 5 -0.15 fBN Allowed Input Baud Rate Deviation Allowed Input Baud Rate Deviation fB fB -0.05 fBN -0.03 fBN Allowed Input Duty Cycle Bit Cell Time Input Data Edge to Clock Falling Edge Clock Width Low Clock Falling Edge to Data Transition Doc #06005 5/8/2006 42.5 tc tCL tCWL tCD 3.0 TYP 50.0 1000/fB 0.75 tc 500/fBN 4.0 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 MAX 50 0.15 fBN UNITS MBaud MBaud 0.05 fBN 0.03 fBN MBaud MBaud 57.5 % ns ns ns ns 5.0 NOTES 0C to 70C 25C, 3.3V 3.0V to 3.6V -55C to 125C 3.0V to 3.6V ±2ns or 5% 3 3D3522 SILICON DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: Ambient Temperature: 25oC ± 3oC Supply Voltage (Vcc): 5.0V ± 0.1V Input Pulse: High = 3.0V ± 0.1V Low = 0.0V ± 0.1V Source Impedance: 50Ω Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) Pulse Width: PWIN = 1/(2*BAUD) Period: PERIN = 1/BAUD OUTPUT: Rload: Cload: Threshold: 10KΩ ± 10% 5pf ± 10% 1.5V (Rising & Falling) Device Under Test Digital Scope 10KΩ 5pf 470Ω NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. PRINTER COMPUTER SYSTEM WAVEFORM GENERATOR OUT IN TRIG DEVICE UNDER TEST (DUT) OUT IN DIGITAL SCOPE TRIG Figure 2: Test Setup PERIN PW IN tRISE INPUT SIGNAL tFALL VIH 2.4V 1.5V 0.6V 2.4V 1.5V 0.6V tPLH OUTPUT SIGNAL VIL tPHL 1.5V VOH 1.5V VOL Figure 3: Timing Diagram Doc #06005 5/8/2006 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 4