PDU138
data 3
delay
devices, inc.
3-BIT PROGRAMMABLE
DELAY LINE
(SERIES PDU138)
FEATURES
•
•
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•
•
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PACKAGES
Digitally programmable in 8 delay steps
Monotonic delay-versus-address variation
Precise and stable delays
Input & outputs fully TTL interfaced & buffered
2
10 T L fan-out capability
Fits standard 16-pin DIP socket
Auto-insertable
N/C
1
16
VCC
N/C
2
15
N/C
N/C
3
14
N/C
IN
4
13
N/C
OUT
5
12
N/C
N/C
6
11
A0
EN/
7
10
A1
GND
8
9
A2
PDU138-xx
PDU138-xxM
DIP
Military DIP
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The PDU138-series device is a 3-bit digitally programmable delay line.
The delay, TDA, from the input pin (IN) to the output pin (OUT) depends on
the address code (A2-A0) according to the following formula:
IN
OUT
A2
A1
A0
EN/
VCC
GND
TDA = TD0 + TINC * A
where A is the address code, TINC is the incremental delay of the device,
and TD0 is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns
through 50ns, inclusively. The enable pin (EN/) is held LOW during normal
operation. When this signal is brought HIGH, OUT is forced into the LOW
state. The address is not latched and must remain asserted during normal operation.
Delay Line Input
Non-inverted Output
Address Bit 2
Address Bit 1
Address Bit 0
Output Enable
+5 Volts
Ground
SERIES SPECIFICATIONS
DASH NUMBER SPECIFICATIONS
•
Part
Number
PDU138-.5
PDU138-1
PDU138-2
PDU138-5
PDU138-10
PDU138-12
PDU138-15
PDU138-20
PDU138-40
PDU138-50
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Total programmed delay tolerance: 5% or 1ns,
whichever is greater
Inherent delay (TD0): 7ns typical (OUT)
Setup time and propagation delay:
Address to input setup (TAIS):
12ns typ.
Disable to output delay (TDISO): 12ns typ.
Operating temperature: 0° to 70° C
Temperature coefficient: 100PPM/°C (excludes TD0)
Supply voltage VCC: 5VDC ± 5%
Supply current: ICCH = 45ma
ICCL = 20ma
Minimum pulse width: 20% of total delay
Incremental Delay
Per Step (ns)
.5 ± .3
1 ± .4
2 ± .4
5 ± .6
10 ± 1.0
12 ± 1.2
15 ± 1.3
20 ± 1.5
40 ± 2.0
50 ± 2.5
Total Delay
Change (ns)
3.5 ± 1.0
7 ± 1.0
14 ± 1.0
35 ± 1.8
70 ± 3.5
84 ± 4.2
105 ± 5.3
140 ± 7.0
280 ± 14.0
350 ± 17.5
NOTE: Any dash number between .5 and 50 not
shown is also available.
2002 Data Delay Devices
Doc #02004
5/6/02
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
PDU138
APPLICATION NOTES
ADDRESS UPDATE
INPUT RESTRICTIONS
The PDU138 is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
conditions are those for which the delay tolerance
specifications and monotonicity are guaranteed.
The suggested conditions are those for which
signals will propagate through the unit without
significant distortion. The absolute conditions
are those for which the unit will produce some
type of output for a given input.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time, TOAX,
is required before the address lines can change.
This time is given by the following relation:
TOAX = max { (Ai - A i-1) * TINC , 0 }
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will remain
constant from pulse to pulse if the input pulse
width and period remain fixed. In other words,
the delay of the unit exhibits frequency and pulse
width dependence when operated beyond the
recommended conditions. Please consult the
technical staff at Data Delay Devices if your
application has specific high-frequency
requirements.
where A i-1 and Ai are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT pin.
The possibility of spurious signals persists until
the required TOAX has elapsed.
A similar situation occurs when using the EN/
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the EN/ signal high and the
IN signal low for a time given by:
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
TDISH = Ai * TINC
Violation of this constraint may, depending on the
history of the input signal, cause spurious signals
to appear on the OUT pin. The possibility of
spurious signals persists until the required TDISH
has elapsed.
A2-A0
A i-1
Ai
TOAX
TAENS
TAIS
EN/
TENIS
PWIN
TDISH
IN
TDA
PWOU
TDISO
OUT
Figure 1: Timing Diagram
Doc #02004
5/6/02
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
PDU138
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER
Total Programmable Delay
Inherent Delay
Disable to Output Low Delay
Address to Enable Setup Time
Address to Input Setup Time
Enable to Input Setup Time
Output to Address Change
Disable Hold Time
Absolute
Input Period
Suggested
Recommended
Absolute
Input Pulse Width
Suggested
Recommended
SYMBOL
TDT
TD0
TDISO
TAENS
TAIS
TENIS
TOAX
TDISH
PERIN
PERIN
PERIN
PWIN
PWIN
PWIN
MIN
TYP
7
7.0
12.0
UNITS
TINC
ns
ns
ns
ns
ns
2.0
12.0
12.0
See Text
See Text
20
50
200
10
25
100
% of TDT
% of TDT
% of TDT
% of TDT
% of TDT
% of TDT
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
SYMBOL
VCC
VIN
TSTRG
TLEAD
MIN
-0.3
-0.3
-55
MAX
7.0
VDD+0.3
150
300
UNITS
V
V
C
C
NOTES
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
High Level Output Voltage
SYMBOL
VOH
Low Level Output Voltage
VOL
High Level Output Current
Low Level Output Current
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current at Maximum
Input Voltage
High Level Input Current
Low Level Input Current
Short-circuit Output Current
Output High Fan-out
Output Low Fan-out
IOH
IOL
VIH
VIL
VIK
IIHH
Doc #02004
5/6/02
IIH
IIL
IOS
MIN
2.5
TYP
3.4
MAX
UNITS
V
0.35
0.5
V
-1.0
20.0
0.8
-1.2
0.1
mA
mA
V
V
V
mA
20
-0.6
-150
25
12.5
µA
mA
mA
Unit
Load
2.0
-60
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
NOTES
VCC = MIN, IOH = MAX
VIH = MIN, VIL = MAX
VCC = MIN, IOL = MAX
VIH = MIN, VIL = MAX
VCC = MIN, II = IIK
VCC = MAX, VI = 7.0V
VCC = MAX, VI = 2.7V
VCC = MAX, VI = 0.5V
VCC = MAX
3
PDU138
PACKAGE DIMENSIONS
16
11 10
9
.410
MAX
4
5
7
8
.820 MAX
.020
TYP
.280
MAX
.150
±.030
.012 TYP
.100
TYP
.018 TYP
.700 TYP
.300
TYP
Commercial DIP (PDU138-xx)
16
11 10
9
.410
MAX
4
5
7
8
.820 MAX
.020
TYP
.320
MAX
.150
±.030
.018 TYP
.700 TYP
.012 TYP
.100
TYP
.300
TYP
Military DIP (PDU138-xxM)
Doc #02004
5/6/02
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
4
PDU138
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
o
o
Ambient Temperature: 25 C ± 3 C
Supply Voltage (Vcc): 5.0V ± 0.1V
Input Pulse:
High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
Source Impedance:
50Ω Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width:
PWIN = 1.5 x Total Delay
Period:
PERIN = 4.5 x Total Delay
OUTPUT:
Load:
Cload:
Threshold:
1 FAST-TTL Gate
5pf ± 10%
1.5V (Rising & Falling)
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PRINTER
COMPUTER
SYSTEM
REF
PULSE
GENERATOR
OUT
IN
TRIG
DEVICE UNDER
TEST (DUT)
OUT
IN
TRIG
TIME INTERVAL
COUNTER
Test Setup
PERIN
PWIN
TRISE
INPUT
SIGNAL
TFALL
VIH
2.4V
1.5V
0.6V
2.4V
1.5V
0.6V
TDAR
OUTPUT
SIGNAL
VIL
TDAF
VOH
1.5V
1.5V
VOL
Timing Diagram For Testing
Doc #02004
5/6/02
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5