PRELIMINARY TECHNICAL DATA a Quad +15V 256-Step DigiPOTs with Pin Selectable SPI / I2C Digital Interface Preliminary Technical Data FEATURES 256 Position 4-Channel (Independently Programmable) 20k, 50k, 200k Ohms Low Temperature Coefficient 50ppm/oC Selectable Digital Interface (3-Wire SPI Compatible or 2-Wire I2C Compatible Serial Data Input) Operating temperature range -40 to 125ºC +5 to +15V Single-Supply; ±5V Dual-Supply Operation AD5263 Functional Block Diagram A1 B1 A2 W2 B2 A3 W3 B3 A4 W4 VDD VSS SHDN RESB / AD1 RDAC 1 REGISTER RDAC 2 REGISTER VL CLK /SCL APPLICATIONS Mechanical Potentiometer Replacement Optical Network Laser LED Adjust Instrumentation: Gain, Offset Adjustment Stereo Channel Audio Level Control Automotive Electronics Adjustment Programmable Voltage to Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Low Resolution DAC Replacement W1 RDAC 4 REGISTER AD5263 8 ADDRESS DECODER SDI / SDA CS / AD0 RDAC 3 REGISTER SPI / I2C SELECT LOGIC SERIAL INPUT REGISTER GND DIS NC / O2 SDO / O1 GENERAL DESCRIPTION The AD5263 is the industry first quad channel, 256 position, digital potentiometer1 selectable digital interface. These devices perform the same electronic adjustment function as mechanical potentiometers or variable resistor with enhanced resolution, solidstate reliability, and superior low temperature coefficient performance. Each Channel of the AD5263 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the 3 wire SPI or 2-wire I2C compatible serial-input register. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the RDAC latch1. The variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper or the B terminal and the wiper. The fixed A to B terminal resistance of 20k, 50k or 200kΩ has a nominal temperature coefficient of 50 ppm/°C. Unlike majority of the digital potentiometers in the market, these devices can operate up to 15V or ±5V provided proper supply voltages are furnished. Figure 1 Normalized Gain Flatness Versus Frequency. The AD5263 are available in thin narrow body TSSOP-24. All parts are guaranteed to operate over the extended automotive temperature range of -40°C to +125°C. 08 AUG ’02, REV PrD Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 B4 PRELIMINARY TECHNICAL DATA Quad +15V Digital Potentiometers AD5263 ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION (VDD = +5V, VSS = -5V, VL = +5V, VA = +VDD, VB = 0V, -40°C < TA < +125°C unless otherwise noted.) Parameter Symbol Conditions Min Typ 1 Max Units DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs Resistor Differential NL2 R-DNL RWB, VA=NC -1 ±1/4 +1 LSB Resistor Nonlinearity2 R-INL RWB, VA=NC -2 ±1/2 +2 LSB Nominal resistor tolerance3 Resistance Temperature Coefficient Wiper Resistance ∆RAB ∆RAB/∆T RW TA = 25°C Wiper = No Connect IW = 1 V/RAB, VDD = +5V -30 30 % ppm/°C Ω 30 50 100 DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs Resolution Differential Nonlinearity4 Integral Nonlinearity4 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error N DNL INL ∆VW/∆T VWFSE VWZSE 8 –1 –2 Code = 40H Code = FFH Code = 00H Voltage Range5 Capacitance6 Ax, Bx Capacitance6 Wx VA,B,W CA,B CW f = 1 MHz, measured to GND, Code = 40H f = 1 MHz, measured to GND, Code = 40H Common-Mode Leakage ICM VA =VB = VDD / 2 –2 0 ±1/4 ±1/2 5 -1 +1 +1 +2 +0 +2 Bits LSB LSB ppm/°C LSB LSB RESISTOR TERMINALS VSS TBD TBD VDD V pF pF 1 nA DIGITAL INPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current VIH VIL VIH VIL IIL Input Capacitance6 CIL 2.4 0.8 VL = +3V, VSS = 0V VL = +3V, VSS = 0V VIN = 0V or +5V 2.1 0.6 ±1 5 V V V V µA pF DIGITAL Output O1, O2 O1, O2 SDA SDA Three-State Leakage Current Output Capacitance6 VOH VOL VOL VOL IOZ COZ IOH=0.4mA IOL=-1.6mA IOL = -6mA IOL = -3mA VIN = 0V or +5V 2.4 0 3 5.5 0.4 0.6 0.4 ±1 8 V V µA pF 5.5 16.5 ±5.5 60 1 1 V V V µA µA µA 0.6 0.005 mW %/% V V POWER SUPPLIES Logic Supply Power Single-Supply Range Power Dual-Supply Range Logic Supply Current Positive Supply Current Negative Supply Current VL VDD RANGE VDD/SS RANGE IL IDD ISS 2.7 5 ±4.5 VL = +5V VIH = +5V or VIL = 0V VSS = -5V Power Dissipation9 Power Supply Sensitivity PDISS PSS VIH = +5V or VIL = 0V, VDD = +5V, VSS = -5V ∆VDD = +5V ±10% 0.0002 BW_20K THDW tS eN_WB RAB = 20KΩ VA =1Vrms, VB = 0V, f=1KHz, RAB = 20KΩ VA= 10V, VB=0V, ±1 LSB error band RWB = 10KΩ, f = 1KHz, RS = 0 400 0.008 2 9 VSS = 0V DYNAMIC CHARACTERISTICS6, 10 Bandwidth –3dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage 08 AUG ’02, REV PrD -2- KHz % µs nV√Hz PRELIMINARY TECHNICAL DATA Quad +15V Digital Potentiometers AD5263 ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION (VDD = +5V, VSS = -5V, VL = +5V, VA = +VDD, VB = 0V, -40°C < TA < +125°C unless otherwise noted.) Parameter Symbol Conditions Min Typ 1 Max Units SPI (DIS=’0’) INTERFACE TIMING CHARACTERISTICS applies to all parts (Notes 6,12) Input Clock Pulse Width Data Setup Time Data Hold Time CLK to SDO Propagation Delay13 CS Setup Time CS High Pulse Width Reset Pulse Width CLK Fall to CS Rise Hold Time CS Rise to Clock Rise Setup tCH,tCL tDS tDH tPD tCSS tCSW tRS tCSH tCS1 Clock level high or low RL = 1KΩ, CL < 20pF 50 20 20 1 20 40 90 0 10 150 ns ns ns ns ns ns ns ns ns I2C (DIS=’1’) INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12) SCL Clock Frequency tBUF Bus free time between STOP & START tHD;STA Hold Time (repeated START) tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setup Time For START Condition tHD;DAT Data Hold Time tSU;DAT Data Setup Time tF Fall Time of both SDA & SCL signals tR Rise Time of both SDA & SCL signals tSU;STO Setup time for STOP Condition fSCL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 After this period the first clock pulse is generated 0 1.3 0.6 1.3 0.6 0.6 0 100 400 0.9 300 300 0.6 KHz µs µs µs µs µs µs ns ns ns µs NOTES: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Typicals represent average readings at +25°C and VDD = +5V, VSS = -5V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD=+5V, VSS=-5V. VAB = VDD, Wiper (VW) = No connect INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V. DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions. Resistor terminals A, B, W have no limitations on polarity with respect to each other. Guaranteed by design and not subject to production test. Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode. Worst case supply current consumed when input all logic-input levels set at 2.4V, standard characteristic of CMOS logic. PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. All dynamic characteristics use VDD = +5V, VSS = -5V, VL = +5V. Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change. See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2ns(10% to 90% of +3V) and timed from a voltage level of 1.5V. Switching characteristics are measured using VL = +5V. Propagation delay depends on value of VDD, RL, and CL see applications text. The AD5260/AD5262 contains 1,968 transistors. Die Size: 89mil x 105mil, 9,345sq. mil. 08 AUG ’02, REV PrD -3- PRELIMINARY TECHNICAL DATA Quad +15V Digital Potentiometers Infrared (15 sec)...............................................+220 °C Thermal Resistance* θJA, TSSOP-24........................................................ 143°C/W ABSOLUTE MAXIMUM RATINGS (TA = +25°C, unless otherwise noted) VDD to GND ........................................................... -0.3, +15V VSS to GND................................................................. 0V, -7V VDD to VSS....................................................................... +15V VA, VB, VW to GND ................................................. VSS, VDD AX – BX, AX – WX, BX – WX Intermittent2...................................................±20mA Continuous ......................................................±2mA Digital Inputs & Output Voltage to GND .................. 0V, +7V Operating Temperature Range .........................-40°C to +85°C Maximum Junction Temperature (TJ MAX) .................. +150°C Storage Temperature ......................................-65°C to +150°C Lead Temperature (Soldering, 10 sec) ......................... +300°C Vapor Phase (60 sec)....................................... +215 °C Model AD5263BRU20 AD5263BRU20-REEL7 AD5263BRU50 AD5263BRU50-REEL7 AD5263BRU200 AD5263BRU200-REEL7 RAB (kΩ) 20 20 50 50 200 200 AD5263 Package Power Dissipation = (TJMAX - TA) / θJA * NOTES 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. ORDERING GUIDE Package Package Description Option -40/+125°C TSSOP-24 RU-24 -40/+125°C TSSOP-24 RU-24 -40/+125°C TSSOP-24 RU-24 -40/+125°C TSSOP-24 RU-24 -40/+125°C TSSOP-24 RU-24 -40/+125°C TSSOP-24 RU-24 Temp # Parts per Container 62 1,000 62 1,000 62 1,000 Top Mark* AD5263B20 AD5263B20 AD5263B50 AD5263B50 AD5263B200 AD5263B200 *Line 1 contains part number, line 2 branding containing differentiating detail by part type and ADI logo symbol, line 3 contains date code YWW. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5263 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 08 AUG ’02, REV PrD -4- PRELIMINARY TECHNICAL DATA Quad +15V Digital Potentiometers AD5263 SPI Compatible Digital Interface (DIS=’0’) SDI (Data In) TABLE IA: SPI 10-Bit Serial-Data Word Format ADDR B9 A1 DATA B8 B7 B6 B5 A0 D7 D6 D5 MSB 27 29 B4 D4 B3 D3 B2 D2 1 Ax or Dx Ax or Dx 0 tDH tDS SDO (Data Out) B1 D1 1 A'x or D'x A'x or D'x 0 tPD_MAX tCH B0 D0 LSB 20 1 tCS1 CLK 0 tCSH0 1 tCSH1 tCL tCSS CS tCSW 0 tS 1 S DI A1 A0 D7 D6 D5 D4 D3 0 C LK D2 D 1 V DD D0 0V ±1 LSB ERROR BAND 1 Figure 1B. Detail SPI Timing Diagram 0 1 CS ±1 LSB VOUT RDAC REGISTER LOAD 0 1 VOUT 0 Figure 1A. SPI Timing Diagram I2C Compatible Digital Interface (DIS=’1’) TABLE IIA: I2C Write Mode Data Word Format S 0 1 0 1 1 A D 1 A D 0 A W X A 1 Slave Address Byte A 0 R S S D O 1 O 2 X A D 7 Instruction Byte D 6 D 5 D 4 D 3 D 2 D 1 D 0 A Data Byte TABLE IIB: I2C Read Mode Data Word Format: S 0 1 0 1 1 0 A D 0 A R D 7 D 8 D 5 Slave Address Byte D 4 D 3 D 2 D 1 D 0 A P Data Byte S = Start Condition P = Stop Condition A = Acknowledge AD1, AD0 = Package pin programmable address bits, Must match with the logic states at pins AD1, AD0 A1, A0 = RDAC sub address select RS = Software Reset wiper (A1, A0) to mid scale position SD = Shutdown active high, ties wiper (A1, A0) to terminal A, opens terminal B, RDAC register contents are not disturbed. To exit shutdown a command SD = ‘0’ must be executed for each RDAC (A1, A0). W = Write = ‘0’ R = Read = ‘1’ D7,D6,D5,D4,D3,D2,D1,D0 = Data Bits X = Don’t Care t8 SDA t1 t8 t6 t9 SCL t2 t3 P t4 t5 S t7 Sr Figure 2. I2C Compatible Detail Timing Diagram 08 AUG ’02, REV PrD -5- t10 P P PRELIMINARY TECHNICAL DATA Quad +15V Digital Potentiometers AD5263 9 DIS 10 VLOGIC 11 SDI/SDA 12 13 CLK/SCL CS/AD0 14 RESB/AD1 15 SHDN 16 SDO/O1 17 NC/O2 TABLE III: AD5263 PIN Descriptions Pin Name Description 18 VSS Digital Interface Select (SPI/I2C Select); SPI when DIS=’0’, I2C when DIS=’1’ Logic Supply Voltage, needs to be same voltage as the digital logic controlling the AD5263. SDI = 3-wire Serial Data Input/ SDA = 2-wire Serial Data Input/Output Serial Clock Input Chip Select / I2C Compatabile Device Address Bit 0 RESETB/I2C Compatabile Device Address Bit 1 Shutdown -- Ties wiper to terminal A, opens terminal B Serial Data Output, Open Drain transistor requires pull-up resistor/Digital Output O1, can be used to drive external logic No Connection/Digital Output O2, can be used to drive external logic Negative power supply, specified for 1 2 3 4 5 6 7 B1 A1 W1 B3 A3 W3 VDD Resistor terminal B1 Resistor terminal A1 (ADDR=00) Wiper terminal W1 Resistor terminal B3 Resistor terminal A3 Wiper terminal W3 (ADDR=10) Positive power supply, specified for 19 20 21 22 23 24 W4 A4 B4 W2 A2 B2 operation from 0 to -5V. Wiper terminal W4 (ADDR=11) Resistor terminal A4 Resistor terminal B4 Wiper terminal W2 (ADDR=01) Resistor terminal A2 Resistor terminal B2 8 GND +5V to +15V operation Ground AD5263 PIN CONFIGURATION B1 1 24 B2 A1 2 23 A2 22 W2 W1 3 B3 4 A3 5 W3 6 19 W4 VDD 7 18 VSS GND 8 17 NC/O2 DIS 9 16 SDO/O1 VLOGIC 10 15 SHDN SDI/SDA 11 14 RESB/AD1 CLK/SCL 12 AD5263 TSSOP-24 21 B4 20 A4 13 CS/AD0 OUTLINE DIMENSIONS Dimensions shown in inches and (mm) 08 AUG ’02, REV PrD -6-