DCD DF6811

DF6811
8-bit FAST Microcontrollers Family
ver 3.01
OVERVIEW
Document contains brief description of
DF6811 core functionality. The DF6811 is a
advanced 8-bit MCU IP Core with highly sophisticated, on chip peripheral capabilities.
DF6811 soft core is binary-compatible with the
industry standard 68HC11 8-bit microcontroller and can achieve a performance 45-100
million instructions per second. The DF6811
has FAST architecture that is 4 times faster
compared to original implementation. Core in
standard configuration has integrated on chip
major peripheral function. There are two serial
interfaces: an asynchronous serial communications interface (SCI) and a separate synchronous serial peripheral interface (SPI). The
main 16-bit, free-running timer system has
implemented three input capture lines, five
output-compare lines, and a real-time interrupt
function. An 8-bit pulse accumulator subsystem can count external events or measure
external periods.
Self-monitoring circuitry is included on-chip to
protect against system errors. A computer
operating properly (COP) watchdog system
protects against software failures. An illegal
opcode detection circuit provides a nonmaskable interrupt if illegal opcode is detected. Two software-controlled power-saving
modes, WAIT and STOP, are available to
conserve additional power. These modes
make the DF6811 IP Core especially attractive for automotive and battery-driven applications. The DF6811 have built in the developAll trademarks mentioned in this document
are trademarks of their respective owners.
ment support features designed into DF6811.
The LIR signal is intended as a debugging aid.
This signal is driven to active low for the first
bus cycle of each new instruction, making it
easy to reverse assemble (disassemble) instructions from the display of a logic analyzer.
DF6811 is fully customizable, which means
it is delivered in the exact configuration to
meet users requirements. There is no need to
pay extra for not used features and wasted
silicon. It includes fully automated testbench
with complete set of tests allowing easy
package validation at each stage of SoC design flow.
CPU FEATURES
●
FAST architecture, 4 times faster than the
original implementation
●
Software compatible with industry standard 68HC11
●
10 times faster multiplication
●
16 times faster division
●
●
●
●
●
256 bytes of remapped System Function
Registers space (SFRs)
Up to 16M bytes of Data Memory
De-multiplexed Address/Data Bus to allow
easy connection to memory
Two power saving modes: STOP, WAI
Ready pin allows Core to operate with
slow program and data memories
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●
Fully synthesizable, static synchronous
design with no internal tri-states
●
No internal reset generator or gated clock
The peripherals listed below are implemented
in standard configuration of DF6811.
●
Scan test ready
●
●
Technology independent HDL source code
○ Processor execution control
●
Core can be fully customized
○ Read, write all processor contents
●
1 GHz virtual clock frequency compared to
original implementation
DESIGN FEATURES
♦
♦
♦
PERIPHERALS
ONE GLOBAL SYSTEM CLOCK
SYNCHRONOUS RESET
The DF6811 has 3 reset vectors
sources, which easy identify a cause of
system reset.
○ Hardware execution breakpoints
○ Three wire communication interface
●
Four 8-bit I/O Ports
●
Interrupt Controller
○ 20 interrupt sources
○ 17 priority levels
○ Dedicated Interrupt vector for each interrupt
●
ALL ASYNCHRONOUS INPUT SIGNALS ARE
○ Four stage programmable prescaller
DATA MEMORY:
○ Timer clocked by internal source
The DF6811 can address up to 16M
bytes of Data Memory via the function interconnect signals. The 256 bytes of Data
Memory in every 64k page is reserved for
the Function Registers. Extra DPP (Data
Page Pointer) register is used for segments
swapping. Data Memory can be implemented as synchronous or asynchronous
RAM.
9
Main16-bit timer/counter system
○ 16 bit free running counter
SYNCHRONIZED BEFORE INTERNAL USE
9
DoCDTM on Chip Debugger
○ Real Time Interrupt
●
○ Three independent input-capture functions
○ Five output-compare channels
○ Events capturing
○ Pulses and digital signals generation
○ Gated timers
SYSTEM FUNCTION REGISTERS:
Up to 256 System Function Registers(SFRs) may be implemented to the
DF6811 design. SFRs are memory
mapped into Data Memory within any 4k
bytes address space.
16-bit Compare/Capture Unit
○ Sophisticated comparator
○ Pulse width modulation
○ Pulse width measuring
●
8-bit Pulse accumulator
○ Two major modes of operation
9
PROGRAM MEMORY:
Up to 64kB of Program Memory may be
implemented to the DF6811 design. Program Memory can be implemented as synchronous or asynchronous ROM.
○ Simple event counter
○ Gated time accumulation
○ Clocked by internal source or external pin
●
SPI – Master and Slave Serial Peripheral
Interface
○ Supports speeds up 1/8 of system clock
○ Software selectable polarity and phase of se-
rial clock SCK
○ System errors detection
○ Allows operation from a wide range of system
clock frequencies (build-in 5-bit timer)
○ Interrupt generation
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
●
Full-duplex UART - SCI
●
○ Standard Nonreturn to Zero format (NRZ)
○ VHDL, Verilog source code called HDL Source
○ 8 or 9 bit data transfer
○ Encrypted, or plain text EDIF called Netlist
○ Integrated baud rate generator
●
○ Noise, Overrun and Framing error detection
○ IDLE and BREAK characters generation
●
DELIVERABLES
♦
♦
♦
♦
♦
Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
Synthesis scripts
Example application
Technical support
◊ IP Core implementation support
◊ 3 months maintenance
Delivery the IP Core updates, minor
and major versions changes
●
Delivery the documentation updates
○ Phone & email support
●
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC implementation.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA bitstreams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restriction except One Year license where time of
use is limited to 12 months.
Unlimited Designs license for
○ HDL Source
from IDLE condition
○ Three SCI related interrupts
One Year license for
○ Encrypted Netlist only
○ Wake-up block to recognize UART wake-up
♦
Single Design license for
○ Netlist
●
Upgrade from
○ HDL Source to Netlist
○ Single Design to Unlimited Designs
CONFIGURATION
The following parameters of the DF6811 core
can be easy adjusted to requirements of
dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in
package file. There is no need to change any
parts of the code.
TM
• DoCD Hardware Debugger
-
used
unused
• Architecture type
-
Harvard
Von Neumann
• Memories type
-
Synchronous
Asynchronou
• Data Memory size
-
64 kB
16 MB
• Memories wait-states
-
used
unused
• Power saving STOP mode
-
used
unused
• WATCHDOG Timer
-
used
unused
• Timer system & Com, Cap
-
used
unused
• Pulse Accumulator
-
used
unused
• PORTS A, B, C, D
-
used
unused
• SCI – UART Interface
-
used
unused
• SPI Interface
-
used
unused
- used
- unused
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Support for MUL and DIV
• Instructions
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are trademarks of their respective owners.
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
PINS DESCRIPTION
PIN
ACTIVE
TYPE
clk
-
input
Global system clock
por
Low
input
Power on reset vector fetch
cmf
Low
input
Clock monitor fail vector fetch
-
input
Program memory bus input
prgdata[7:0]
ready
DESCRIPTION
Low
input
Ready for Code and Data mem.
datai[7:0]
-
input
Memory bus input
ufrdatai[7:0]
-
input
UFRs data bus input
irq
*
input
Interrupt input
xirq
Low
input
Non-maskable interrupt input
portxi[7:0]
-
input
Port A, B, C, D input
cap1,2,3
Low
input
Capture inputs
*
input
Pulse accumulator input
pai
rxd
Low
input
SCI receiver data input
si
High
input
SPI slave input
mi
High
input
SPI master input
*
input
SPI clock input
SPI slave select
scki
ss
Low
input
prgaddr[15:0]
-
output
Program memory address bus
prgoe
-
output
Program memory output enable
datao[7:0]
-
output
Data memory & UFR bus output
addr[23:0]
-
output
Data memory address bus
ramwe
Low
output
Data memory write enable
ramoe
Low
output
Data memory output enable
ufraddr[7:0]
ufrwe
-
output
UFR address bus
Low
output
UFRs write enable
ufroe
Low
output
UFRs output enable
lir
Low
output
Load instruction register
halt
High
output
Halt clock system (STOP inst.)
-
output
Port A, B, C, D output
portxo[7:0]
ddrx[7:0]
-
output
Port A, B, C, D direction control
cmp1,2,3,4,5
*
output
Compare outputs
cmp1en,2,3,4,5
High
output
Output compare enable
txd
Low
output
SCI transmitter data output
so
High
output
SPI slave output
mo
High
output
SPI master output
scko
*
output
SPI clock output
scken
High
output
SPI clock output enable
soen
High
output
SPI Slave Output enable
clkdocd
-
input
DoCD
TM
clock input
docddatai
-
input
DoCD
TM
serial Data input
Serial Data Output
Serial Clock Output
docddatao
-
output
DoCD
TM
docdclk
-
output
DoCD
TM
SYMBOL
lir
halt
clk
por
cmf
datao(7:0)
dataen
ready
iromdata(7:0)
iromaddr(12:0)
iromoe
iromwe
iramdata(7:0)
iramaddr(9:0)
iramwe
iramoe
xramdata(7:0
xramaddr(23:0)
xramwe
xramoe
ufrdatai(7:0)
ufraddr(7:0)
ufrwe
ufroe
portai(7:0)
portbi(7:0)
portci(7:0)
portdi(7:0)
portao(7:0)
portbo(7:0)
portco(7:0)
portdo(7:0)
ddra(7:0)
ddrb(7:0)
ddrc(7:0)
ddrd(7:0)
irq
xirq
cmp1
cmp2
cmp3
cmp4
cmp5
cmp1en
cmp2en
cmp3en
cmp4en
cmp5en
cap1
cap2
cap3
pai
moda
modb
rxd
si
mi
txd
so
mo
soen
scko
scken
scki
ss
clkdocd
docddatai
TM
DoCD
docddatao
docdclk
Interface
* Kind of activity is configurable
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
BLOCK DIAGRAM
Control Unit - Performs the core synchronization and data flow control. This module
manages execution of all instructions. The
Control Unit also manages execution of STOP
instruction and waking-up the processor from
the STOP mode.
Opcode Decoder - Performs an instruction
opcode decoding and the control functions for
all other blocks.
ALU - Arithmetic Logic Unit performs the
arithmetic and logic operations during execution of an instruction. Contains accumulator
(A, B), Condition Code Register (CCREG),
Index registers X, Y and related logic such as
arithmetic and logic unit, and multiplier/divider.
Bus Controller – Program Memory, Data
Memory & SFR’s (Special Function Register)
interface controls access into the program and
data memories and special registers. It contains Program Counter (PC), Stack Pointer
(SP) register, INIT register (INIT), Data Page
Pointer (DPP), and related logic.
Interrupt Controller - DF6811 extended IC
has implemented 17-level interrupt priority
control. The interrupt requests may come from
external pins (IRQ and XIRQ) as well as from
particular peripherals. The DF6811 peripheral
systems generate maskable interrupts, which
are recognized only if the global interrupt
mask bit (I) in the CCR is cleared. Maskable
interrupts are prioritized according to default
arrangement (look at the table below) established during reset. However any one source
may be elevated to the highest maskable priority position using HPRIO register. When
interrupt condition occurs, an interrupt status
flag is set to indicate the condition.
I/O Ports - All ports are 8-bit general-purpose
bi-directional I/O system. The PORTA,
PORTB, PORTC, PORTD data registers have
their corresponding data direction registers
DDRA, DDRB, DDRC, DDRD to control ports
data flow. It assures that all DF6811’s ports
have full I/O selectable registers. Writes to
any ports pins cause data to be stored in the
data registers. If any port pins are configured
as output then data registers are driven out of
those pins. Reads from port pins configured
as input causes that input pin is read. If port
pins is configured as output, during read data
register is read. Writes to any ports pins not
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are trademarks of their respective owners.
configured as outputs do not cause data to be
driven out of those pins, but the data is stored
in the output registers. Thus, if the pins later
become outputs, the last data written to port
will be driven out the port pins.
clk
por
cmf
halt
lir
Opcode
Decoder
Control
Unit
BUS
Controller
irq
xirq
Interrupt
Controller
Watchdog
Timer
pai
Pulse
Accumulator
rxd
txd
SCI Unit
so
si
mo
mi
scko
scki
scken
soen
ss
SPI Unit
ALU
clkdocd
docddatai
docddatao
docdclk
I/O
Ports
Timer
with
Compare /
Capture
Unit
TM
DoCD
Debugger
ready
datao
dataen
iromdata
iromaddr
iromwe
iromoe
iramdata
iramaddr
iramwe
iramoe
xramdata
xramaddr
xramwe
xramoe
ufrdata
ufraddr
ufrwe
ufroe
moda
modb
portai
portbi
portci
portdi
portao
portbo
portco
portdo
ddra
ddrb
ddrc
ddrd
cap1
cap2
cap3
cmp1
cmp2
cmp3
cmp4
cmp5
cmp1en
cmp2en
cmp3en
cmp4en
cmp5en
Timer, Compare Capture & COP Watchdog
- This timer system is based on a free-running
16-bit counter with a 4-stage programmable
prescaler. A timer overflow function allows
software to extend the timing capability of the
system beyond the 16-bit range of the counter. Three independent input-capture functions
are used to automatically record the time
when a selected transition is detected at a
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compare functions are included for generating
output signals or for timing software delays.
Since the input-capture and output-compare
functions may not be familiar to all users,
these concepts are explained in greater detail.
A programmable periodic interrupt circuit
called RTI is tapped off of the main 16-bit
timer counter. Software can select one of four
rates for the RTI, which is most commonly
used to pace the execution of software routines. The COP watchdog function is loosely
related to the main timer in that the clock input
to the COP system (clk*217) is tapped off the
free-running counter chain. The timer subsystem involves more registers and control
bits than any other subsystem on the MCU.
Each of the three input-capture functions has
its own 16-bit time capture latch (input-capture
register) and each of the five output-compare
functions has its own 16-bit compare register.
All timer functions, including the timer overflow
and RTI, have their own interrupt controls and
separate interrupt vectors. Additional control
bits permit software to control the edge(s) that
trigger each input-capture function and the
automatic actions that result from outputcompare functions. Although hardwired logic
is included to automate many timer activities,
this timer architecture is essentially a software-oriented system. This structure is easily
adaptable to a very wide range of applications
although it is not as efficient as dedicated
hardware for some specific timing applications.
SCI - The SCI is a full-duplex UART type
asynchronous system, using standard non
return to zero (NRZ) format : 1 start bit, 8 or 9
data bits and a 1 stop bit. The DF6811 resynchronizes the receiver bit clock on all one to
zero transitions in the bit stream. Therefore
differences in baud rate between the sending
device and the SCI are not as likely to cause
reception errors. Three logic samples are
taken near the middle of data bit time, and
majority logic decides the sense for the bit.
For the start and stop bits seven logic samples are taken. Even if noise causes one of
these samples to be incorrect, the bit will still
be received correctly. The receiver also has
the ability to enter a temporary standby mode
(called receiver wakeup) to ignore messages
intended for a different receiver. Logic automatically wakes up the receiver in time to see
the first character of the next message. This
wakeup feature greatly reduces CPU overAll trademarks mentioned in this document
are trademarks of their respective owners.
head in multi-drop SCI networks. The SCI
transmitter can produce queued characters of
idle (whole characters of all logic 1) and break
(whole characters of all logic 0). In addition to
the usual transmit data register empty (TDRE)
status flag, this SCI also provides a transmit
complete (TC) indication that can be used in
applications with a modem.
SPI Unit – it’s a fully configurable master/slave Serial Peripheral Interface, which
allows user to configure polarity and phase of
serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system.
A serial clock line (SCK) synchronizes shifting
and sampling of the information on the two
independent serial data lines. SPI data are
simultaneously transmitted and received. SPI
system is flexible enough to interface directly
with numerous standard product peripherals
from several manufacturers. Data rates as
high as CLK/8. Clock control logic allows a
selection of clock polarity and a choice of two
fundamentally different clocking protocols to
accommodate most available synchronous
serial peripheral devices. When the SPI is
configured as a master, software selects one
of four different bit rates for the serial clock.
Error-detection logic is included to support
interprocessor communications. A writecollision detector indicates when an attempt is
made to write data to the serial shift register
while a transfer is in progress. A multiplemaster mode-fault detector automatically disables SPI output drivers if more than one SPI
devices simultaneously attempts to become
bus master.
Pulse Accumulator – This system is based
on an 8-bit counter and can be configured to
operate as a simple event counter or for gated
time accumulation. Unlike the main timer, the
8-bit pulse accumulator counter can be read
or written at any time (the 16-bit counter in the
main timer cannot be written). Control bits
allow the user to configure and control the
pulse accumulator subsystem. Two maskable
interrupts are associated with the system,
each having its own controls and interrupt
vector. The PAI pin associated with the pulse
accumulator can be configured to act as a
clock (event counting mode) or as a gate signal to enable a free-running E divided by 64
clock to the 8-bit counter (gated time accumulation mode). The alternate functions of the
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pulse accumulator input (PAI) pin present
some interesting application possibilities.
○ Wide range of system clock frequencies
DoCDTM - Debug Unit – it’s a real-time hardware debugger provides debugging capability
of a whole SoC system. In contrast to other
on-chip debuggers DoCD™ provides nonintrusive debugging of running application. It
can halt, run, step into or skip an instruction,
read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can
be set and controlled on program memory,
internal and external data memories, as well
as on SFRs. Hardware breakpoint is executed
if any write/read occurred at particular address
with certain data pattern or without pattern.
The DoCDTM system includes three-wire interface and complete set of tools to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off to save silicon and
reduce power consumption. A special care on
power consumption has been taken, and
when debugger is not used it is automatically
switched in power save mode. Finally whole
debugger is turned off when debug option is
no longer used.
○ Interrupt generation
○ User defined data setup time on I2C lines
●
PWM – Pulse Width Modulation Timer
○ 4 independent 8-bit PWM channels, concate-
nated on two 16-bit PWM channel
○ Software-selectable duty from 0% to 100% and
pulse period
○ Software-selectable polarity of output wave-
form
● Fixed-Point arithmetic coprocessor
○ Multiplication - 16bit * 16bit
○ Division - 32bit / 16bit
○ Division - 16bit / 16bit
○ Left and right shifting - 1 to 31 bits
○ Normalization
● Floating-Point
arithmetic
coprocessor
IEEE-754 standard single precision
○ FADD, FSUB - addition, subtraction
○ FMUL, FDIV- multiplication, division
○ FSQRT- square root
○ FUCOM - compare
○ FCHS - change sign
OPTIONAL
PERIPHERALS
There are also available an optional peripherals, not included in presented DF6811
Microcontroller Core. The optional peripherals,
can be implemented in microcontroller core
upon customer request.
● I2C bus controller - Master
○ 7-bit and 10-bit addressing modes
○ NORMAL, FAST, HIGH speeds
○ Multi-master systems supported
○ Clock arbitration and synchronization
○ User defined timings on I2C lines
○ FABS - absolute value
● Floating-Point math coprocessor - IEEE754 standard single precision real, word
and short integers
○ FADD, FSUB- addition, subtraction
○ FMUL, FDIV- multiplication, division
○ FSQRT- square root
○ FUCOM- compare
○ FCHS - change sign
○ FABS - absolute value
○ FSIN, FCOS- sine, cosine
○ FTAN, FATAN – tangent arcs tangent
○ Wide range of system clock frequencies
○ Interrupt generation
● I2C bus controller - Slave
○ NORMAL speed 100 kbs
○ FAST speed 400 kbs
○ HIGH speed 3400 kbs
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are trademarks of their respective owners.
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
PERFORMANCE
IMPROVEMENT
The following table gives a survey about
the Core area and performance in the
ALTERA® devices after Place & Route:
For user the most important is application
speed improvement. The most commonly
used arithmetic functions and theirs improvement are shown in table below. Improvement
was computed as {M68HC11 clock periods}
divided by {DF6811 clock periods} required to
execute an identical function. More details are
available in core documentation
Speed
Logic Cells
Fmax
grade
CYCLONE
-6
2958
58 MHz
STRATIX
-5
2957
62 MHz
APEX II
-7
3092
50 MHz
APEX20KC
-7
2972
43 MHz
APEX20KE
-1
2972
39 MHz
ACEX1K
-1
3023
33 MHz
FLEX10KE
-1
3023
33 MHz
Core performance in ALTERA® devices
Device
Function
8-bit addition (immediate data)
8-bit addition (direct addressing)
8-bit addition (indirect addressing)
8-bit subtraction (immediate data)
8-bit subtraction (direct addressing)
8-bit subtraction (indirect addressing)
16-bit addition (immediate data)
16-bit addition (direct addressing)
16-bit addition (indirect addressing
16-bit subtraction (immediate data)
16-bit subtraction (direct addressing)
16-bit subtraction (indirect addressing
Multiplication
Fractional division
Integer division
Area utilized by the each unit of DF6811 core
in vendor specific technologies is summarized
in table below.
Component
Area
[LC]
CPU*
Main Timer
COM/CAP
Watchdog
Pulse Acc.
SPI Interface
UART - SCI
I/O Ports
Total area
[FFs]
1 986
180
400
74
44
138
272
160
3 254
Improvement
4
4
4
4
4
4
4
4
4
4
4
4
10
14,9
16.4
284
50
224
36
19
62
129
64
829
*CPU – consisted of ALU, Control Unit and Instruction Decoder, Bus
Controller with support for 16MB RAM, External IRQ and XIRQ pin
Interrupt Controller
Core components area utilization
DF68XX FAMILY OVERVIEW
+
*
*
*
+
4
4
4
+
+
*
*
*
*
+
+
*
+
DF68XX family of High Performance Microcontroller Cores
+ optional
* configurable
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are trademarks of their respective owners.
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
Size – ASIC gates
DoCD Debugger
Interface for
additional SFRs
1*
1*
1*
+
Pulse accumulator
2/2*
2/2*
5/3*
+
Watchdog Timer
*
*
*
*
SPI M/S Interface
1*
1*
I\O Ports
7
7
17
3
SCI (UART)
7
7
20
3
Main Timer System
-
Compare\Capture
Interrupt levels
64k
64k
16M
16M
READY for Prg. and
Data memories
Interrupt sources
64k
64k
64k
64k
Data Pointers
Motorola Memory Expansion Logic
4.1
3.2
4.4
4.4
Real Time Interrupt
Paged Data Memory
space
DF6805
DF6808
DF6811
DF6811CPU
Physical Linear memory space
Design
Speed acceleration
The main features of each DF68XX family member have been summarized in table below. It gives
a briefly member characterization helping user to select the most suitable IP Core for its application.
User can specify its own peripheral set (including listed below and the others) and requests the core
modifications.
6 700
8 900
12 000
6 500
CONTACTS
For any modification or special request
please contact to Digital Core Design or local
distributors.
Headquarters:
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