DCD DFP2INT

DFP2INT
Floating Point To Integer Pipelined Converter
ver 2.20
OVERVIEW
The DFP2INT is the pipelined floating point
to integer converter. The input and output
numbers format is according to IEEE-754
standard. DFP2INT supports single precision
real numbers and double word integers (4
Bytes). Convert operation is pipelined to 2
levels. Input data are fed every clock cycle.
The first result appears after latency equal to
2 clock periods and next results are available
each clock cycle. Full precision and accuracy are accomplished.
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DELIVERABLES
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APPLICATION
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Math coprocessors
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DSP algorithms
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Embedded arithmetic coprocessor
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Data processing & control
KEY FEATURES
Fully synthesizable, static synchronous
design with no internal tri-states
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Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
VHDL & VERILOG test bench environment
◊ Active-HDL automatic simulation macros
◊ NCSim automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
Synthesis scripts
Example application
Technical support
◊ IP Core implementation support
◊ 3 months maintenance
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Full IEEE-754 compliance
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Single precision real input numbers
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Double word output numbers(4 Bytes)
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Simple interface
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No programming required
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2 levels pipelining
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Full accuracy and precision
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Results available at every clock
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Overflow, underflow and invalid operation
flags
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Fully configurable
All trademarks mentioned in this document
are trademarks of their respective owners.
Delivery the IP Core updates, minor
and major versions changes
Delivery the documentation updates
Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of
IP Core easy and simply.
Single Design license allows using IP Core in
single FPGA bitstream and ASIC implementation. It also permits FPGA prototyping before ASIC production.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
Unlimited Designs license allows using IP
Core in unlimited number of FPGA bitstreams
and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time of use
limitations.
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Source
○ Encrypted, or plain text EDIF called Netlist
Unlimited Designs license for
○ HDL Source
○ Netlist
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datai(31:0)
Argument
Checker
Main FP
Pipelined Unit
Result
Composer
datao(31:0)
ofo
ufo
ifo
en
rst
clk
Single Design license for
○ VHDL, Verilog source code called HDL
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BLOCK DIAGRAM
Upgrade from
○ Netlist to HDL Source
○ Single Design to Unlimited Designs
SYMBOL
datai(31:0)
datao(31:0)
ofo
ufo
ifo
en
rst
clk
Arguments Checker - performs input data
analyze against IEEE-754 number standard
compliance. The appropriate numbers and
information about the input data classes are
given as the results to Main FP Pipelined
Unit.
Main FP Pipelined Unit - performs floating
point to integer conversion. Gives the complex information about the results to Result
Composer module.
Result Composer - performs result rounding
function, data alignment to IEEE-754 standard, and the final flags setting.
PINS DESCRIPTION
PIN
TYPE
DESCRIPTION
clk
Input
Global system clock
rst
Input
Global system reset
en
Input
Enable computing
datai[31:0]
Input
Data bus input
datao[31:0]
Output Data bus output
ofo
Output Overflow flag
ufo
Output Underflow flag
ifo
Output Invalid result flag
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
PERFORMANCE
CONTACTS
The following table gives a survey about the
Core area and performance in the ALTERA®
devices after Place & Route :
For any modification or special request
please contact to Digital Core Design or local
distributors.
Speed
Logic Cells
Fmax
grade
FLEX10KE
-1
335
67 MHz
ACEX1K
-1
335
71 MHz
APEX20K
-1
295
69 MHz
APEX20KE
-1
295
67 MHz
APEX20KC
-7
295
88 MHz
APEX-II
-7
295
114 MHz
MERCURY
-5
270
208 MHz
STRATIX
-5
245
184 MHz
CYCLONE
-6
245
165 MHz
STRATIX-II
-3
185
214 MHz
CYCLONE-II
-6
265
133 MHz
Core performance in ALTERA® devices
Device
All trademarks mentioned in this document
are trademarks of their respective owners.
Headquarters:
Wroclawska 94
41-902 Bytom, POLAND
nfo@dcd.pl
e-mail: iinfo@dcd.pl
tel.
: +48 32 282 82 66
fax
: +48 32 282 74 37
Distributors:
ttp://www.dcd.pl/apartn.php
Please check hhttp://www.dcd.pl/apartn.php
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.