DFPCOMP Floating Point Comparator Unit ver 2.10 OVERVIEW The DFPCOMP compares two arguments. The input numbers format is according to IEEE-754 standard. DFPCOMP supports single precision real numbers. Compare operation was pipelined up to 1 level. Input data are fed every clock cycle. The first result appears after 1 clock period latency and next results are available each clock cycle. Full IEEE-754 unordered compare function is included. APPLICATION ● Math coprocessors ● DSP algorithms ● Embedded arithmetic coprocessor ● Data processing & control KEY FEATURES ● Full IEEE-754 compliance ● Single precision real format support ● Simple interface ● No programming required ● 1 level pipeline ● Results available at every clock ● Fully configurable ● Fully synthesizable, static synchronous design with no internal tri-states DELIVERABLES ♦ Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment ◊ Active-HDL automatic simulation macros ◊ NCSim automatic simulation macros ◊ ModelSim automatic simulation macros ◊ Tests with reference responses Technical documentation ◊ ◊ ◊ ♦ ● Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support ◊ IP Core implementation support ◊ 3 months maintenance ◊ ◊ ◊ ♦ ♦ ♦ ● ● ● Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support LICENSING All trademarks mentioned in this document are trademarks of their respective owners. Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows using IP Core in single FPGA bitstream and ASIC implementation. It also permits FPGA prototyping before ASIC production. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. Unlimited Designs license allows using IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time of use limitations. ● Single Design license for ○ VHDL, Verilog source code called HDL BLOCK DIAGRAM adatai(31:0) Arguments Checker bdatai(31:0) Main FP Pipelined Unit gto eqo lto ifo en rst clk Source ○ Encrypted, or plain text EDIF called Netlist ● Unlimited Designs license for ○ HDL Source ○ Netlist ● Upgrade from ○ Netlist to HDL Source ○ Single Design to Unlimited Designs SYMBOL adatai(31:0) bdatai(31:0) en rst clk gto eqo lto ifo Main FP Pipelined Unit - performs floating point compare function. Gives the complex information about the results and makes final flags settings. PERFORMANCE The following table gives a survey about the Core area and performance in the ALTERA® devices after Place & Route : PINS DESCRIPTION PIN Arguments Checker - performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and information about the input data classes are given as the results to Main FP Pipelined Unit. TYPE DESCRIPTION clk Input Global system clock rst Input Global system reset en Input Enable computing adatai[31:0] Input A data bus input bdatai[31:0] Input B data bus input gto output A>B output eqo output A=B output lto output A<B output ifo output Invalid result flag All trademarks mentioned in this document are trademarks of their respective owners. Speed Logic Cells Fmax grade FLEX10KE -1 83 81 MHz ACEX1K -1 83 82 MHz APEX20K -1 79 60 MHz APEX20KE -1 79 76 MHz APEX20KC -7 79 98 MHz APEX-II -7 79 118 MHz MERCURY -5 85 178 MHz STRATIX -5 82 152 MHz CYCLONE -6 81 140 MHz STRATIX-II -3 66 225 MHz CYCLONE -II -6 81 141 MHz Core performance in ALTERA® devices Device http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND [email protected] e-mail: [email protected] tel. : +48 32 282 82 66 fax : +48 32 282 74 37 Distributors: ttp://www.dcd.pl/apartn.php Please check hhttp://www.dcd.pl/apartn.php All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.