DFPMUL Floating Point Pipelined Multiplier Unit ver 2.70 OVERVIEW The DFPMUL uses the pipelined mathematics algorithm to multiply two arguments. The input numbers format is according to IEEE754 standard. DFPMUL supports single precision real number. Multiply operation was pipelined up to 7 levels. Input data are fed every clock cycle. The first result appears after latency depending on pipeline level and next results are available each clock cycle. Full IEEE-754 precision and accuracy were included. ● DELIVERABLES ♦ Math coprocessors ● DSP algorithms ● Embedded arithmetic coprocessor ● Data processing & control ♦ ♦ KEY FEATURES ● Full IEEE-754 compliance ● Single precision real format support ● Simple interface ● No programming required ● 7 levels pipeline ● Full accuracy and precision ● Overflow, underflow and invalid operation flags ● Results available at every clock ● Fully configurable All trademarks mentioned in this document are trademarks of their respective owners. Source code: VHDL Source Code or/and VERILOG Source Code or/and ALTERA’s Megafunction or/and EDIF netlist VHDL & VERILOG test bench environment ◊ Active-HDL automatic simulation macros ◊ NCSim automatic simulation macros ◊ ModelSim automatic simulation macros ◊ Tests with reference responses Technical documentation ◊ Installation notes ◊ HDL core specification ◊ Datasheet Synthesis scripts Example application Technical support ◊ IP Core implementation support ◊ 3 months maintenance ◊ ◊ ◊ ◊ APPLICATION ● Fully synthesizable, static synchronous design with no internal tri-states ♦ ♦ ♦ ● ● ● Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows using IP Core in single FPGA bitstream and ASIC implemenhttp://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. tation. It also permits FPGA prototyping before ASIC production. Unlimited Designs license allows using IP Core in unlimited number of FPGA bitstreams and ASIC implementations. BLOCK DIAGRAM adatai(31:0) Arguments Checker bdatai(31:0) In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time of use limitations. ● Single Design license for ○ VHDL, Verilog source code called HDL Source ○ Encrypted, or plain text EDIF called Netlist ● Unlimited Designs license for ○ HDL Source ○ Netlist ● Upgrade from ○ Netlist to HDL Source ○ Single Design to Unlimited Designs SYMBOL adatai(31:0) datao(31:0) bdatai(31:0) ofo ufo ifo en rst clk TYPE DESCRIPTION clk Input Global system clock rst Input Global system reset en Input Enable computing adatai[31:0] Input A data bus input bdatai[31:0] Input B data bus input datao[31:0] Output Data bus output ofo Output Overflow flag ufo Output Underflow flag ifo Output Invalid result flag All trademarks mentioned in this document are trademarks of their respective owners. datao(31:0) Result Composer ofo ufo ifo en rst clk Arguments Checker - performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and information about the input data classes are given as the results to Main FP Pipelined Unit. Main FP Pipelined Unit - performs floating point multiply function. Gives the complex information about the results and makes final flags settings. Result Composer - performs result rounding function, data alignment to IEEE-754 standard, and the final flags setting. PERFORMANCE The following table gives a survey about the Core area and performance in the ALTERA® devices after Place & Route : PINS DESCRIPTION PIN Main FP Pipelined Unit Device FLEX10KE ACEX1K APEX20K APEX20KE APEX20KC APEX-II MERCURY STRATIX CYCLONE STRATIX-II CYCLONE-II Speed grade -1 -1 -1 -1 -7 -7 -5 -5 -6 -3 -6 Logic Cells Fmax 1340 1340 1210 1210 1210 1210 1290 440+8M1 1170 410+8M1 480+8M1 40 MHz 40 MHz 50 MHz 50 MHz 51 MHz 67 MHz 77 MHz 93 MHz 72 MHz 134 MHz 117 MHz 1 - 9-bit DSP block Core performance in ALTERA® devices http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND [email protected] e-mail: [email protected] tel. : +48 32 282 82 66 fax : +48 32 282 74 37 Distributors: ttp://www.dcd.pl/apartn.php Please check hhttp://www.dcd.pl/apartn.php All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.