DI2CSB I2C Bus Interface Slave - Base version ver 1.15 OVERVIEW I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance between many devices. The DI2CSB provides an interface between a passive target device e.g. memory, LCD display, pressure sensors etc. and an I2C bus. It can works as a slave receiver or transmitter depending on working mode determined by a master device. Very simple interface, composed with the read, write and data signals, allows easy connection to the target devices. The core doesn’t required programming and is ready to work after power up/reset. The read, write, burst read, burst write and repeated start transmissions are automatically recognized by the core. The core incorporates all features required by I2C specification. The DI2CSB supports the following transmission modes: Standard, Fast and High Speed. KEY FEATURES ● Conforms to v.2.1 of the I2C specification ● Slave operation ○ Slave transmitter ○ Slave receiver ● ● ● Support for reads, writes, burst reads, burst writes, and repeated start ● 7-bit addressing ● No programming required ● Simple interface allows easy connection to target device e.g. memory, LCD display, pressure sensors etc. ● Fully synthesizable ● Static synchronous design with positive edge clocking and synchronous reset ● No internal tri-states ● Scan test ready APPLICATIONS ● Embedded microprocessor boards ● Consumer and professional audio/video ● Home and automotive radio ● Low-power applications ● Communication systems ● Cost-effective reliable automotive systems DELIVERABLES Supports 3 transmission speed modes ○ Standard (up to 100 kb/s) ○ Fast (up to 400 kb/s) ○ High Speed (up to 3,4 Mb/s) Allows operation from a wide range of input clock frequencies All trademarks mentioned in this document are trademarks of their respective owners. ♦ Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment ◊ Active-HDL automatic simulation macros ◊ ModelSim automatic simulation macros ◊ ◊ ◊ ♦ http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. Tests with reference responses Technical documentation ◊ Installation notes ◊ HDL core specification ◊ Datasheet Synthesis scripts Example application Technical support ◊ IP Core implementation support ◊ 3 months maintenance ◊ ♦ ♦ ♦ ♦ ● ● ● SYMBOL datai(7:0) rd wr scli sdai sdao clk rst Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support LICENSING datao(7:0) PINS DESCRIPTION PIN TYPE DESCRIPTION clk input Global clock rst input Global reset datai(7:0) input Data bus from target device Single Design license allows use IP Core in single FPGA bitstream and ASIC implementation. scli input I2C bus clock line (input) sdai input I2C bus data line (input) datao(7:0) output Data bus to target device Unlimited Designs, One Year licenses allow use IP Core in unlimited number of FPGA bitstreams and ASIC implementations. wr output Write strobe for target device rd output Read strobe for target device sdao output I2C bus data line (output) Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months. ● Single Design license for ○ VHDL, Verilog source code called HDL Source ○ Encrypted, or plain text EDIF called Netlist ● One Year license for ○ ● ○ ● Figure below shows the DI2CSB IP Core block diagram. Target device Interface – Performs the interface functions between DI2CSB internal blocks and target device. Allows easy connection of the core to a passive devices e.g. memory, LCD display, pressure sensors, I/O devices etc.. Encrypted Netlist only Unlimited Designs license for ○ BLOCK DIAGRAM HDL Source Receive Data datai(7:0) datao(7:0) we rd Netlist Upgrade from ○ HDL Source to Netlist ○ Single Design to Unlimited Designs Send Data Input Filter sdai Output Register sdao Own address detection Control Logic rst clk All trademarks mentioned in this document are trademarks of their respective owners. Shift Register Target device Interface Synchronization Logic Input Filter http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. scli Control Logic – Manages execution of all commands sent via interface. Synchronizes internal data flow. PERFORMANCE The following table gives a survey about the Core area and performance in the ALTERA® devices after Place & Route (all key features have been included): Shift Register – Controls SDA line, performs data and address shifts during the data transmission and reception. Input Filter – Performs spike filtering. Speed Logic Cells Fmax grade MERCURY -5 95 220 MHz STRATIX -5 95 230 MHz CYCLONE -6 95 195 MHz APEX II -7 95 220 MHz APEX20KC -7 95 170 MHz APEX20KE -1 95 130 MHz APEX20K -1 95 94 MHz ACEX1K -1 95 99 MHz FLEX10KE -1 95 95 MHz MAX 7000AE -4 50 107 MHz MAX 3000A -4 50 107 MHz MAX II -3 75 154 MHz Core performance in ALTERA® devices Device Synchronization Logic – Synchronizes data and address shifts during the data transmission and reception. SCLI spikes are filtered by this unit. - - Spike filtering User defined timing High-speed mode Fast mode - Standard mode - 10-bit addressing - - 7-bit addressing Arbitration - Clock synchronization Passive device interface CPU interface - Slave operation 2.1 2.1 2.1 Interrupt generation DI2CM DI2CS DI2CSB Master operation Design I2C specification version The main features of each Digital Core Design I2C compliant cores have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. - I2C cores summary table All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND [email protected] e-mail: [email protected] tel. : +48 32 282 82 66 fax : +48 32 282 74 37 Distributors: ttp://www.dcd.pl/apartn.php Please check hhttp://www.dcd.pl/apartn.php All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.