DCD DP80390CPU

DP80390CPU
Pipelined High Performance
8-bit Microcontroller
ver 4.02
OVERVIEW
DP80390CPU is an ultra high performance, speed optimized soft core of a singlechip 8-bit embedded controller dedicated for
operation with fast (typically on-chip) and slow
(off-chip) memories. It supports up to 8 MB of
linear code and 16 MB of linear data spaces.
The core has been designed with a special
concern about performance to power consumption ratio. This ratio is extended by an
advanced power management unit PMU.
DP80390CPU soft core is 100% binarycompatible with the industry standard 80390 &
8051 8-bit microcontroller. There are two configurations of DP80390CPU: Harward where
internal data and program buses are separated, and von Neumann with common program and external data bus. DP80390CPU has
Pipelined RISC architecture 10 times faster
compared to standard architecture and executes 85-200 million instructions per second.
This performance can also be exploited to
great advantage in low power applications
where the core can be clocked over ten times
more slowly than the original implementation
for no performance penalty.
DP80390CPU is delivered with fully
automated testbench and complete set of
tests allowing easy package validation at each
stage of SoC design flow.
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are trademarks of their respective owners.
CPU FEATURES
●
100% software compatible with industry
standard 80390 & 8051
○ LARGE mode – 8051 instruction set
○ FLAT mode – 80390 instruction set
●
Pipelined RISC architecture enables to
execute instructions 10 times faster compared to standard 8051
●
24 times faster multiplication
●
12 times faster addition
●
Up to 256 bytes of internal (on-chip) Data
Memory
●
Up to 8M bytes of linear Program Memory
○ 64 kB of internal (on-chip) Program Memory
○ 8 MB external (off-chip) Program Memory
●
Up to 16M bytes of external (off-chip) Data
Memory
●
User programmable Program Memory Wait
States solution for wide range of memories
speed
●
User programmable External Data Memory
Wait States solution for wide range of
memories speed
●
De-multiplexed Address/Data bus to allow
easy connection to memory
●
Dedicated signal for Program Memory
writes.
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●
Interface for additional Special Function
Registers
●
Fully synthesizable, static synchronous
design with positive edge clocking and no
internal tri-states
●
Scan test ready
●
2.0 GHz virtual clock frequency in a 0.25u
technological process
PERIPHERALS
●
DoCD™ debug unit
○ Processor execution control
Run
Halt
Step into instruction
Skip instruction
○ Read-write all processor contents
Program Counter (PC)
Program Memory
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
○ Code execution breakpoints
one real-time PC breakpoint
unlimited number of real-time OPCODE breakpoints
○ Hardware execution watch-point
one at Internal (direct) Data Memory
one at Special Function Registers (SFRs)
one at External Data Memory
○ Hardware watch-points activated at a certain
address by any write into memory
address by any read from memory
address by write into memory a required data
address by read from memory a required data
○ Unlimited number of software watch-points
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
○ Unlimited number of software breakpoints
Program Memory(PC)
○ Automatic adjustment of debug data transfer
speed rate between HAD and Silicon
○ JTAG Communication interface
●
Power Management Unit
○ Power management mode
○ Switchback feature
○ Stop mode
●
Interrupt Controller
○ 2 priority levels
○ 2 external interrupt sources
CONFIGURATION
The following parameters of the DP80390CPU
core can be easy adjusted to requirements of
dedicated application and technology. Configuration of the core can be prepared by effortless
changing appropriate constants in package file.
There is no need to change any parts of the
code.
•
Internal Program Memory
type
- synchronous
- asynchronous
•
Internal Program ROM
Memory size
0 - 64kB
-
•
Internal Program RAM
Memory size
0 - 64kB
-
•
Internal Program Memory
fixed size
- true
- false
-
• Power Management Mode
- used
- unused
• Stop mode
- used
- unused
• DoCD™ debug unit
- used
- unused
Besides mentioned above parameters all
available peripherals and external interrupts
can be excluded from the core by changing
appropriate constants in package file.
DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
●
●
●
All trademarks mentioned in this document
are trademarks of their respective owners.
subroutines
location
• Interrupts
Delivery the IP Core updates, minor and
major versions changes
Delivery the documentation updates
Phone & email support
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
DESIGN FEATURES
♦
Single Design license allows using IP Core in
single FPGA bitstream and ASIC implementation. It also permits FPGA prototyping before
ASIC production.
○ ROM located in address range between
0x0000 ÷ (ROMsize-1)
Unlimited Designs license allows using IP Core
in unlimited number of FPGA bitstreams and
ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time of use
limitations.
●
○ RAM located in address range between
(64kB-RAMsize) ÷ 0xFFFF
External Program Memory can be implemented as ROM or RAM located in address range between ROMsize ÷ 8 MB excluding area occupied by RAMsize.
♦
INTERNAL DATA MEMORY:
The DP80390CPU can address Internal
Data Memory of up to 256 bytes The Internal Data Memory can be implemented as
Single-Port synchronous RAM.
♦
EXTERNAL DATA MEMORY:
The DP80390CPU soft core can address
up to 16 MB of External Data Memory. Extra DPX (Data Pointer eXtended) register is
used for segments swapping.
♦
USER SPECIAL FUNCTION REGISTERS:
Up to 104 External (user) Special Function Registers (ESFRs) may be added to
the DP80390CPU design. ESFRs are
memory mapped into Direct Memory between addresses 0x80 and 0xFF in the
same manner as core SFRs and may occupy any address that is not occupied by a
core SFR.
♦
WAIT STATES SUPPORT:
The DP80390CPU soft core is dedicated
for operation with wide range of Program
and Data memories. Slow Program and External Data memory may assert a memory
Wait signal to hold up CPU activity.
Single Design license for
○ VHDL, Verilog source code called HDL Sour-
ce
○ Encrypted, or plain text EDIF called Netlist
●
Unlimited Designs license for
○ HDL Source
○ Netlist
●
Upgrade from
○ Netlist to HDL Source
○ Single Design to Unlimited Designs
All trademarks mentioned in this document
are trademarks of their respective owners.
PROGRAM MEMORY:
The DP80390 soft core is dedicated for
operation with Internal and External Program Memory. It maximal linear size is
equal to 8 MB. Internal Program Memory
can be implemented as:
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SYMBOL
prgromdata(7:0)
prgramdata(7:0)
xdatai(7:0)
iprgromsize(2:0)
iprgramsize(2:0)
ramdatai(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
xaddr(23:0)
xdatao(7:0)
xdataz
ready
sxdmxdatai(7:0)
BLOCK DIAGRAM
Opcode
decoder
prgramdata(7:0)
prgromdata(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
xaddr(23:0)
xdatao(7:0)
xdatai(7:0)
xdataz
ready
xprgrd
xprgwr
xdatard
xdatawr
xprgrd
xprgwr
xdatard
xdatawr
sxdmadd(15:0)
sxdmdatao(7:0)
sxdmwe
sxdmoe
rsto
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Control
Unit
User SFR’s
interface
Power
Management Unit
DoCD™
Debug Unit
int0
int1
stop
pmm
tdi
tck
tms
tdo
rtck
coderun
debugacs
ALU
clk
reset
PINS DESCRIPTION
PIN
reset
clk
Interrupt
controller
sfraddr(6:0)
sfrdatao(7:0)
sfrdatao(7:0)
sfroe
sfrwe
stop
pmm
tck
tms
sxdmaddr
sxdmdatao
sxdmdatai
sxdmoe
sxdmwe
interface
Internal data
memory
interface
sfraddr(6:0)
sfrdatao(7:0)
sfroe
sfrwe
tdo
rtck
coderun
debugacs
External
memory
ramaddr(7:0)
ramdatao(7:0)
ramdatai(7:0)
ramwe
ramoe
sfrdatai(7:0)
tdi
SXDM
interface
iprgromsize(2:0)
iprgramsize(2:0)
ramaddr(7:0)
ramdatao(7:0)
ramwe
ramoe
int0
int1
Program
memory
interface
TYPE
DESCRIPTION
clk
input
Global clock
reset
input
Global reset
port0i[7:0]
input
Port 0 input
port1i[7:0]
input
Port 1 input
port2i[7:0]
input
Port 2 input
port3i[7:0]
input
Port 3 input
iprgramsize[2:0]
input
Size of on-chip RAM CODE
iprgromsize[2:0]
input
Size of on-chip ROM CODE
prgramdata[7:0]
input
Data bus from int. RAM prog. memory
prgromdata[7:0]
input
Data bus from int. ROM prog. memory
sxdmdatai[7:0]
input
Data bus from sync external data
memory (SXDM)
ready
input
External memory data ready
ramdatai[7:0]
input
Data bus from internal data memory
sfrdatai[7:0]
input
Data bus from user SFR’s
int0
input
External interrupt 0
int1
input
External interrupt 1
tdi
input
DoCD™ TAP data input
tck
input
DoCD™ TAP clock input
tms
input
DoCD™ TAP mode select input
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PIN
TYPE
DESCRIPTION
rsto
output Reset output
port0o[7:0]
output Port 0 output
port1o[7:0]
output Port 1 output
port2o[7:0]
output Port 2 output
port3o[7:0]
output Port 3 output
prgaddr[15:0]
output Internal program memory address bus
prgdatao[7:0]
output Data bus for internal program memory
prgramwr
output Internal program memory write
sxdmaddr[15:0]
output Sync XDATA memory address bus
(SXDM)
sxdmdatao[7:0]
output Data bus for Sync XDATA memory
(SXDM)
sxdmoe
output Sync XDATA memory read (SXDM)
sxdmwe
output Sync XDATA memory write (SXDM)
xaddr[23:0]
output Address bus for external memories
xdatao[7:0]
output Data bus for external memories
xdataz
output Turn xdata bus into ‘Z’ state
xprgrd
output External program memory read
xprgwr
output External program memory write
xdatard
output External data memory read
xdatawr
output External data memory write
ramaddr[7:0]
output Internal Data Memory address bus
ramdatao[7:0]
output Data bus for internal data memory
ramoe
output Internal data memory output enable
ramwe
output Internal data memory write enable
sfraddr[6:0]
output Address bus for user SFR’s
sfrdatao[7:0]
output Data bus for user SFR’s
sfroe
output User SFR’s read enable
sfrwe
output User SFR’s write enable
tdo
output DoCD™ TAP data output
rtck
output DoCD™ return clock line
debugacs
output DoCD™ accessing data
coderun
output CPU is executing an instruction
pmm
output Power management mode indicator
stop
output Stop mode indicator
UNITS SUMMARY
ALU – Arithmetic Logic Unit performs the
arithmetic and logic operations during execution of an instruction. It contains accumulator
(ACC), Program Status Word (PSW), (B) registers and related logic such as arithmetic unit,
logic unit, multiplier and divider.
Opcode Decoder – Performs an instruction
opcode decoding and the control functions for
all other blocks.
Control Unit – Performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and
manages execution of all microcontroller tasks.
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are trademarks of their respective owners.
Program Memory Interface – Contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program
Memory can be also written. This feature allows usage of a small boot loader loading new
program into RAM, EPROM or FLASH
EEPROM storage via UART, SPI, I2C or
DoCD™ module.
External Memory Interface - Contains memory access related registers such as Data
Page High (DPH), Data Page Low (DPL) and
Data Pointer eXtended (DPX) registers. It performs the external Program and Data Memory
addressing and data transfers. Program fetch
cycle length can be programmed by user. This
feature is called Program Memory Wait States,
and allows core to work with different speed
program memories.
Synchronous
eXternal
Data
Memory
(SXDM) Interface – contains XDATA memory
access related logic allowing fast access to
synchronous memory devices. It performs the
external Data Memory addressing and data
transfers. This memory can be used to store
large variables frequently accessed by CPU,
improving overall performance of application.
Internal Data Memory Interface – Internal
Data Memory interface controls access into the
internal 256 bytes memory. It contains 8-bit
Stack Pointer (SP) register and related logic.
User SFRs Interface – Special Function Registers interface controls access to the special
registers. It contains standard and used defined registers and related logic. User defined
external devices can be quickly accessed
(read, written, modified) using all direct addressing mode instructions.
Interrupt Controller – Interrupt control module
is responsible for the interrupt manage system
for the external and internal interrupt sources.
It contains interrupt related registers such as
Interrupt Enable (IE), Interrupt Priority (IP) and
(TCON) registers.
Power Management Unit – Block contains
advanced power saving mechanisms with
switchback feature, allowing external clock
control logic to stop clocking (Stop mode) or
run core in lower clock frequency (Power Management Mode) to significantly reduce power
consumption. Switchback feature allows
UARTs, and interrupts to be processed in full
speed mode if enabled. It is very desired when
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microcontroller is planned to use in portable
and power critical applications.
DoCD™ Debug Unit – it’s a real-time hardware debugger provides debugging capability
of a whole SoC system. In contrast to other onchip debuggers DoCD™ provides non-intrusive
debugging of running application. It can halt,
run, step into or skip an instruction, read/write
any contents of microcontroller including all
registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read
occurred at particular address with certain data
pattern or without pattern. Two additional pins
CODERUN, DEBUGACS indicate the sate of
the debugger and CPU. CODERUN is active
when CPU is executing an instruction. DEBUGACS pin is active when any access is performed by DoCD™ debugger. The DoCD™
system includes JTAG interface and complete
set of tools to communicate and work with core
in real time debugging. It is built as scalable
unit and some features can be turned off to
save silicon and reduce power consumption. A
special care on power consumption has been
taken, and when debugger is not used it is
automatically switched in power save mode.
Finally whole debugger is turned off when debug option is no longer used.
PROGRAM CODE SPACE
IMPLEMENTATION
The figure below shows an example Program Memory space implementation in systems with DP80390CPU Microcontroller core.
The On-chip Program Memory located in address space between 0kB and 1kB is typically
used for BOOT code with system initialization
functions. This part of the code is typically implemented as ROM. The On-chip Program
Memory located in address space between
60kB and 64kB is typically used for timing critical part of the code e.g. interrupt subroutines,
arithmetic functions etc. This part of the code is
typically implemented as RAM and can be
loaded by the BOOT code during initialization
phase from Off-chip memory or through RS232
interface from external device. From the two
mentioned above spaces program code is
executed without wait-states and can achieve
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tions per second (many instructions executed
in one clock cycle). The Off-chip Program
Memory located in address space between
1kB and 60kB, and above 64 kB is typically
used for main code and constants. This part of
the code is usually implemented as ROM,
SRAM or FLASH device. Because of relatively
long access time the program code executed
from mentioned above devices must be
fetched with additional Wait-States. Number of
required Wait-States depends on memory access time and DP80390CPU clock frequency.
In most cases the proper number of WaitStates cycles is between 2-5. The READY pin
can be also dynamically modulated e.g. by
SDRAM controller.
0x7FFFFF
Off chip Memory
(implemented as ROM,
SRAM or FLASH)
0x00FFFF
0x00F000
On chip Memory
(implemented as RAM)
Off chip Memory
(implemented as ROM,
SRAM or FLASH)
0x000400
0x000000
On-chip Memory
(implemented as ROM)
The figure below shows a typical Program
Memories connections in system with
DP80390CPU Microcontroller core.
prgramdatai
prgdatao
8
8
prgramwr
On-chip Memory
12
(implemented as RAM)
0 Wait-State access
prgaddr
10
prgromdata
i
DP80390CPU
xdatai
8
ASIC or FPGA
chip
8
xdatao
xaddr
On-chip Memory
(implemented as ROM)
0 Wait-State access
Off-chip Memory
24
xprgrd
(implemented as
FLASH, or SRAM)
eg. 2-5 Wait-State
access
xprgwr
ready
Wait-States
manager
The described above implementation should be
treated as an example. All Program Memory
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spaces are fully configurable. For timing-critical
applications whole program code can be implemented as on-chip ROM and (or) RAM and
executed without Wait-States, but for some
other applications whole program code can be
implemented as off-chip ROM or FLASH and
executed with required number Wait-State cycles.
PERFORMANCE
The following tables give a survey about the
Core area and performance in Programmable
Logic Devices after Place & Route (CPU features and peripherals have been included):
Device
FLEX10KE
ACEX1K
APEX20K
APEX20KE
APEX20KC
APEX-II
MERCURY
CYCLONE
CYCLONE-II
STRATIX
STRATIX-II
Speed grade
-1
-1
-1
-1
-7
-7
-5
-6
-6
-5
-3
Fmax
57 MHz
56 MHz
50 MHz
63 MHz
76 MHz
74 MHz
101 MHz
93 MHz
95 MHz
98 MHz
160 MHz
Core performance in ALTERA® devices
For a user the most important is application
speed improvement. The most commonly used
arithmetic functions and theirs improvement
are shown in table below. Improvement was
computed as {80C51 clock periods} divided by
{DP80390CPU clock periods} required to execute an identical function. More details are
available in core documentation.
Function
8-bit addition (immediate data)
8-bit addition (direct addressing)
8-bit addition (indirect addressing)
8-bit addition (register addressing)
8-bit subtraction (immediate data)
8-bit subtraction (direct addressing)
8-bit subtraction (indirect addressing)
8-bit subtraction (register addressing)
8-bit multiplication
8-bit division
16-bit addition
16-bit subtraction
16-bit multiplication
32-bit addition
32-bit subtraction
32-bit multiplication
Average speed improvement:
Improvement
9,00
9,00
9,00
12,00
9,00
9,00
9,00
12,00
16,00
9,60
12,00
12,00
13,60
12,00
12,00
12,60
11,12
Dhrystone Benchmark Version 2.1 was used to
measure Core performance. The following table gives a survey about the DP80390CPU
performance in terms of Dhrystone/sec and
VAX MIPS rating.
Clock
frequency
80C51
12 MHz
80C310
33 MHz
DP80390CPU STRATIX-II
150 MHz
Device
Target
Dhry/sec
(VAX MIPS)
268 (0.153)
1550 (0.882)
26220 (14.924)
Core performance in terms of Dhrystones
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26220
27000
24000
21000
18000
15000
12000
9000
6000
3000
0
1550
268
80C51 (12MHz)
80C310 (33MHz)
DP80390CPU (150MHz)
Area utilized by the each unit of DP80390CPU
core in vendor specific technologies is summarized in table below.
Component
CPU*
Interrupt Controller
Power Management Unit
Total area
Area
[LC]
[FFs]
1790
100
10
1900
315
40
5
360
*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &
Internal & External Memory Interfaces, User SFRs Interface
Core components area utilization in all technologies except
STRATIX-II
Component
CPU*
Interrupt Controller
Power Management Unit
Total area
Area
[LC]
[FFs]
1380
75
10
1465
315
40
5
360
*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &
Internal & External Memory Interfaces, User SFRs Interface
Core components area utilization in STRATIX-II
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1
2
4
4
-
-
-
-
-
Fixed Point
Coprocessor
Floating Point
Coprocessor
I\O Ports
2
3
SPI
UART
1
1
2
Master I2C Bus
Controller
Slave I2C Bus
Controller
Timer/Counters
2
2
2
Watchdog
Data Pointers
2
5
15
Compare/Capture
Interrupt levels
64k 64k 8M 256 256 16M
64k 64k 8M 256 256 16M
64k 64k 8M 256 256 16M
Interrupt sources
Interface for
additional SFRs
Power Management Unit
Internal Data Memory
space
External Data Memory
space
External Data / Program
Memory Wait States
Stack space size
off-chip
10
10
10
on-chip ROM
DP80390CPU
DP80390
DP80390XP
Program
Memory
space
on-chip RAM
Design
Architecture speed grade
The main features of each DP80390 family member have been summarized in table below. It gives
a briefly member characterization helping user to select the most suitable IP Core for its application.
User can specify its own peripheral set (including listed below and the others) and requests the core
modifications.
-
-
DP80390 family of High Performance Microcontroller Cores
4
4
-
-
-
-
DP8051 family of High Performance Microcontroller Cores
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-
Fixed Point
Coprocessor
Floating Point
Coprocessor
1
2
SPI
2
3
Master I C Bus
Controller
Slave I2C Bus
Controller
I\O Ports
1
1
2
2
UART
2
2
2
Watchdog
Timer/Counters
2
5
15
Compare/Capture
Data Pointers
Interface for
additional SFRs
Power Management Unit
Internal Data Memory
space
External Data Memory
space
External Data / Program
Memory Wait States
Stack space size
off-chip
on-chip ROM
64k 64k 64k 256 256 16M
64k 64k 64k 256 256 16M
64k 64k 64k 256 256 16M
Interrupt levels
10
10
10
Interrupt sources
DP8051CPU
DP8051
DP8051XP
Program
Memory
space
on-chip RAM
Design
Architecture speed grade
The main features of each DP8051 family member have been summarized in table below. It gives
a briefly member characterization helping user to select the most suitable IP Core for its application.
User can specify its own peripheral set (including listed below and the others) and requests the core
modifications.
-
-
CONTACTS
For any modification or special request contact to DCD.
Headquarters:
Wroclawska 94
41-902 Bytom, POLAND
nfo@dcd.pl
e-mail: iinfo@dcd.pl
tel.
: +48 32 282 82 66
fax
: +48 32 282 74 37
Distributors:
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Please check hhttp://www.dcd.pl/apartn.php
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