DP80390XP
Pipelined High Performance
8-bit Microcontroller
ver 4.05
OVERVIEW
DP80390XP is an ultra high performance, speed optimized soft core of a singlechip 8-bit embedded controller dedicated for
operation with fast (typically on-chip) and slow
(off-chip) memories. It supports up to 8 MB of
linear code and 16 MB of linear data spaces.
The core has been designed with a special
concern about performance to power consumption ratio. This ratio is extended by an
advanced power management unit PMU.
DP80390XP soft core is 100% binarycompatible with the industry standard 80390 &
8051 8-bit microcontroller. There are two configurations of DP80390XP: Harward where
internal data and program buses are separated, and von Neumann with common program and external data bus. DP80390XP has
Pipelined RISC architecture 10 times faster
compared to standard architecture and executes 85-200 million instructions per second.
This performance can also be exploited to
great advantage in low power applications
where the core can be clocked over ten times
more slowly than the original implementation
for no performance penalty.
DP80390XP is fully customizable, which
means it is delivered in the exact configuration
to meet users’ requirements. There is no need
to pay extra for not used features and wasted
silicon. It includes fully automated testbench
with complete set of tests allowing easy
All trademarks mentioned in this document
are trademarks of their respective owners.
package validation at each stage of SoC design flow.
CPU FEATURES
●
100% software compatible with industry
standard 80390 & 8051
○ LARGE mode – 8051 instruction set
○ FLAT mode – 80390 instruction set
●
Pipelined RISC architecture enables to
execute instructions 10 times faster compared to standard 8051
●
24 times faster multiplication
●
12 times faster addition
●
2 Data Pointers (DPTR) for faster memory
blocks copying
○ Advanced INC & DEC modes
○ Auto-switch of current DPTR
●
●
Up to 256 bytes of internal (on-chip) Data
Memory
Up to 8M bytes of linear Program Memory
○ 64 kB of internal (on-chip) Program Memory
○ 8 MB external (off-chip) Program Memory
●
Up to 16M bytes of external (off-chip) Data
Memory
○ Synchronous eXternal Data Memory (SXDM)
Interface
●
User programmable Program Memory Wait
States solution for wide range of memories
speed
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●
User programmable External Data Memory
Wait States solution for wide range of
memories speed
●
De-multiplexed Address/Data bus to allow
easy connection to memory
●
Dedicated signal for Program Memory
writes.
●
Interface for additional Special Function
Registers
●
Fully synthesizable, static synchronous
design with positive edge clocking and no
internal tri-states
●
Scan test ready
●
2.0 GHz virtual clock frequency in a 0.25u
technological process
○ Up to 7 external interrupt sources
○ Up to 8 interrupt sources from peripherals
●
●
●
●
●
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Power Management Unit
Extended Interrupt Controller
○ 2 priority levels
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NORMAL speed 100 kbs
FAST speed 400 kbs
HIGH speed 3400 kbs
Wide range of system clock frequencies
User defined data setup time on I2C lines
Interrupt generation
SPI – Master and Slave Serial Peripheral
Interface
○ Supports speeds up ¼ of system clock
Mode fault error
Write collision error
○ Four transfer formats supported
○ System errors detection
○ Allows operation from a wide range of system
clock frequencies (build-in 5-bit timer)
○ Interrupt generation
●
●
Programmable Watchdog Timer
16-bit Compare/Capture Unit
○
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Events capturing
Pulses generation
Digital signals generation
Gated timers
Sophisticated comparator
Pulse width modulation
Pulse width measuring
Fixed-Point arithmetic coprocessor
○
○
○
○
○ Power management mode
○ Switchback feature
○ Stop mode
●
7-bit and 10-bit addressing modes
NORMAL, FAST, HIGH speeds
Multi-master systems supported
Clock arbitration and synchronization
User defined timings on I2C lines
Wide range of system clock frequencies
Interrupt generation
I2C bus controller - Slave
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Synchronous mode, fixed baud rate
8-bit asynchronous mode, fixed baud rate
9-bit asynchronous mode, fixed baud rate
9-bit asynchronous mode, variable baud rate
I2C bus controller - Master
○
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speed rate between HAD and Silicon
○ JTAG Communication interface
Full-duplex serial port
○
○
○
○
DoCD™ debug unit
○ Processor execution control
Run
Halt
Step into instruction
Skip instruction
○ Read-write all processor contents
Program Counter (PC)
Program Memory
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
○ Code execution breakpoints
one real-time PC breakpoint
unlimited number of real-time OPCODE breakpoints
○ Hardware execution watch-point
one at Internal (direct) Data Memory
one at Special Function Registers (SFRs)
one at External Data Memory
○ Hardware watch-points activated at a certain
address by any write into memory
address by any read from memory
address by write into memory a required data
address by read from memory a required data
○ Unlimited number of software watch-points
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
○ Unlimited number of software breakpoints
Program Memory(PC)
○ Automatic adjustment of debug data transfer
Three 16-bit timer/counters
○ Timers clocked by internal source
○ Auto reload 8/16-bit timers
○ Externally gated event counters
PERIPHERALS
●
Four 8-bit I/O Ports
○ Bit addressable data direction for each line
○ Read/write of single line and 8-bit group
Multiplication - 16bit * 16bit
Multiplication - 32bit * 32bit
Division - 32bit / 32bit
Division - 16bit / 16bit
Floating-Point
arithmetic
coprocessor
IEEE-754 standard single precision
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○
○
○
○
○
○
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FADD, FSUB - addition, subtraction
FMUL, FDIV- multiplication, division
FSQRT- square root
FUCOM - compare
FCHS - change sign
FABS - absolute value
Floating-Point math coprocessor - IEEE754 standard single precision real, word
and short integers
○
○
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FADD, FSUB- addition, subtraction
FMUL, FDIV- multiplication, division
FSQRT- square root
FUCOM- compare
FCHS - change sign
FABS - absolute value
FSIN, FCOS- sine, cosine
FTAN, FATAN- tangent, arcs tangent
CONFIGURATION
The following parameters of the DP80390XP
core can be easy adjusted to requirements of
dedicated application and technology. Configuration of the core can be prepared by effortless
changing appropriate constants in package file.
There is no need to change any parts of the
code.
•
Internal Program Memory
type
0 - 64kB
-
Internal Program RAM
Memory size
0 - 64kB
-
Internal Program Memory
•
fixed size
•
Second Data Pointer
(DPTR1)
- true
- false
- used
- unused
• DPTR0 decrement
- used
- unused
• DPTR1 decrement
- used
- unused
• Data Pointers auto-switch
- used
- unused
• Interrupts
-
• Timing access protection
- used
- unused
• Power Management Mode
• Stop mode
subroutines
location
DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
●
●
●
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are trademarks of their respective owners.
Delivery the IP Core updates, minor and
major versions changes
Delivery the documentation updates
Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows using IP Core in
single FPGA bitstream and ASIC implementation. It also permits FPGA prototyping before
ASIC production.
Unlimited Designs license allows using IP Core
in unlimited number of FPGA bitstreams and
ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time of use
limitations.
●
Single Design license for
○ VHDL, Verilog source code called HDL Sour-
- used
- unused
- used
- unused
- used
- unused
Besides mentioned above parameters all
available peripherals and external interrupts
can be excluded from the core by changing
appropriate constants in package file.
- synchronous
- asynchronous
Internal Program ROM
•
Memory size
•
• DoCD™ debug unit
ce
○ Encrypted, or plain text EDIF called Netlist
●
Unlimited Designs license for
○ HDL Source
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○ Netlist
●
SYMBOL
Upgrade from
○ Netlist to HDL Source
○ Single Design to Unlimited Designs
DESIGN FEATURES
♦
PROGRAM MEMORY:
The DP80390 soft core is dedicated for
operation with Internal and External Program Memory. It maximal linear size is
equal to 8 MB. Internal Program Memory
can be implemented as:
○ ROM located in address range between
0x0000 ÷ (ROMsize-1)
○ RAM located in address range between
(64kB-RAMsize) ÷ 0xFFFF
port0i(7:0)
port1i(7:0)
port2i(7:0)
port3i(7:0)
ramdatai(7:0)
sfrdatai(7:0)
prgromdata(7:0)
prgramdata(7:0)
xdatai(7:0)
ready
External Program Memory can be implemented as ROM or RAM located in address range between ROMsize ÷ 8 MB excluding area occupied by RAMsize.
iprgromsize(2:0)
iprgramsize(2:0)
♦
INTERNAL DATA MEMORY:
The DP80390XP can address Internal
Data Memory of up to 256 bytes The Internal Data Memory can be implemented as
Single-Port synchronous RAM.
♦
EXTERNAL DATA MEMORY:
The DP80390XP soft core can address
up to 16 MB of External Data Memory. Extra DPX (Data Pointer eXtended) register is
used for segments swapping.
int0
int1
int2
int3
int4
int5
int6
♦
♦
USER SPECIAL FUNCTION REGISTERS:
Up to 60 External (user) Special Function Registers (ESFRs) may be added to
the DP80390XP design. ESFRs are memory mapped into Direct Memory between
addresses 0x80 and 0xFF in the same
manner as core SFRs and may occupy any
address that is not occupied by a core
SFR.
WAIT STATES SUPPORT:
The DP80390XP soft core is dedicated
for operation with wide range of Program
and Data memories. Slow Program and External Data memory may assert a memory
Wait signal to hold up CPU activity.
sxdmxdatai(7:0)
t0
gate0
t1
gate1
t2
t2ex
capture0
capture1
capture2
capture3
rxd0i
rxd1i
scli
sdai
ss
si
mi
scki
reset
clk
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port0o(7:0)
port1o(7:0)
port2o(7:0)
port3o(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
xaddr(23:0)
xdatao(7:0)
xdataz
xprgrd
xprgwr
xdatard
xdatawr
sxdmadd(15:0)
sxdmdatao(7:0)
sxdmwe
sxdmoe
ramaddr(7:0)
ramdatao(7:0)
ramwe
ramoe
sfraddr(7:0)
sfrdatao(7:0)
sfroe
sfrwe
stop
pmm
rxd0o
txd0
rxd1o
txd1
sclhs
sclo
sdao
sso(7:0)
so
mo
scko
scken
soen
coderun
debugacs
rsto
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BLOCK DIAGRAM
PINS DESCRIPTION
PIN
Opcode
decoder
prgramdata(7:0)
prgromdata(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
xramaddr(23:0)
xdatao(7:0)
xdatai(7:0)
xramdataz
ready
xprgrd
xprgwr
xdatard
xdatawr
iprgromsize(2:0)
iprgramsize(2:0)
ramaddr(7:0)
ramdatao(7:0)
ramdatai(7:0)
ramwe
ramoe
sfraddr(6:0)
sfrdatao(7:0)
sfrdatao(7:0)
sfroe
sfrwe
Program
memory
interface
External
memory
I/O Port
registers
Timers
UART
Control
Unit
Internal data
memory
interface
User SFR’s
interface
Interrupt
controller
Power
Management Unit
DoCD™
Debug Unit
SXDM
interface
capture0
capture1
capture2
capture3
Timer 2
int0
int1
int2
int3
int4
int5
int6
Master/
Slave I2C
Unit
ALU
clk
reset
rsto
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DESCRIPTION
clk
input
Global clock
reset
input
Global reset
port0i[7:0]
input
Port 0 input
port1i[7:0]
input
Port 1 input
port2i[7:0]
input
Port 2 input
port3i[7:0]
input
Port 3 input
iprgramsize[2:0]
input
Size of on-chip RAM CODE
iprgromsize[2:0]
input
Size of on-chip ROM CODE
prgramdata[7:0]
input
Data bus from int. RAM prog. memory
prgromdata[7:0]
input
Data bus from int. ROM prog. memory
sxdmdatai[7:0]
input
Data bus from sync external data
memory (SXDM)
xdatai[7:0]
input
Data bus from external memories
ready
input
External memory data ready
ramdatai[7:0]
input
Data bus from internal data memory
input
Data bus from user SFR’s
stop
int0
input
External interrupt 0
pmm
int1
input
External interrupt 1
int2
input
External interrupt 2
int3
input
External interrupt 3
int4
input
External interrupt 4
int5
input
External interrupt 5
tdi
tck
tms
tdo
rtck
coderun
debugacs
sxdmaddr
sxdmdatao
sxdmdatai
sxdmoe
sxdmwe
rxd0o
rxd0i
txd0
UART 1
SPI Unit
TYPE
sfrdatai[7:0]
Compare
Capture
MDU32
sclhs
scli
sclo
sdai
sdao
rxdi
rxdo
txd
Watchdog
Timer
UART 0
rxd1o
rxd1i
txd1
t0
t1
gate0
gate1
interface
Floating
Point Unit
t2
t2ex
port0(7:0)
port1(7:0)
port2(7:0)
port3(7:0)
so
si
mo
mi
scko
scki
scken
ss
sso(7:0)
soen
int6
input
External interrupt 6
t0
input
Timer 0 input
t1
input
Timer 1 input
t2
input
Timer 2 input
gate0
input
Timer 0 gate input
gate1
input
Timer 1 gate input
t2ex
input
Timer 2 gate input
capture0
input
Timer 2 capture 0 line
capture1
input
Timer 2 capture 1 line
capture2
input
Timer 2 capture 2 line
capture3
input
Timer 2 capture 3 line
rxdi0
input
Serial receiver input 0
rxdi1
input
Serial receiver input 1
scli
input
Master/Slave I2C clock line input
sdai
input
Master/Slave I2C data input
ss
input
SPI slave select
si
input
SPI slave input
mi
input
SPI master input
scki
input
SPI clock input
tdi
input
DoCD™ TAP data input
tck
input
DoCD™ TAP clock input
input
DoCD™ TAP mode select input
tms
rsto
output Reset output
port0o[7:0]
output Port 0 output
port1o[7:0]
output Port 1 output
port2o[7:0]
output Port 2 output
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PIN
port3o[7:0]
TYPE
DESCRIPTION
output Port 3 output
prgaddr[15:0]
output Internal program memory address bus
prgdatao[7:0]
output Data bus for internal program memory
prgramwr
output Internal program memory write
sxdmaddr[15:0]
output Sync XDATA memory address bus
(SXDM)
sxdmdatao[7:0]
output Data bus for Sync XDATA memory
(SXDM)
sxdmoe
output Sync XDATA memory read (SXDM)
sxdmwe
output Sync XDATA memory write (SXDM)
xaddr[23:0]
output Address bus for external memories
xdatao[7:0]
output Data bus for external memories
xdataz
output Turn xdata bus into ‘Z’ state
xprgrd
output External program memory read
xprgwr
output External program memory write
xdatard
output External data memory read
xdatawr
output External data memory write
ramaddr[7:0]
output Internal Data Memory address bus
ramdatao[7:0]
output Data bus for internal data memory
ramoe
output Internal data memory output enable
ramwe
output Internal data memory write enable
sfraddr[6:0]
output Address bus for user SFR’s
sfrdatao[7:0]
output Data bus for user SFR’s
sfroe
output User SFR’s read enable
sfrwe
output User SFR’s write enable
tdo
output DoCD™ TAP data output
rtck
output DoCD™ return clock line
debugacs
output DoCD™ accessing data
coderun
output CPU is executing an instruction
pmm
output Power management mode indicator
stop
output Stop mode indicator
rxd0o
output Serial receiver output 0
rxd1o
output Serial receiver output 1
txd0
output Serial transmitter output 0
txd1
output Serial transmitter output 1
sclo
output Master/Slave I2C clock output
sclhs
output High speed Master I2C clock line
sdao
output Master/Slave I2C data output
sso[7:0]
output SPI slave select lines
so
output SPI slave output
mo
output SPI master output
scko
output SPI clock output
scken
output SPI clock line tri-state buffer control
soen
output SPI slave output enable
UNITS SUMMARY
ALU – Arithmetic Logic Unit performs the
arithmetic and logic operations during execution of an instruction. It contains accumulator
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ters and related logic such as arithmetic unit,
logic unit, multiplier and divider.
Opcode Decoder – Performs an instruction
opcode decoding and the control functions for
all other blocks.
Control Unit – Performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and
manages execution of all microcontroller tasks.
Program Memory Interface – Contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program
Memory can be also written. This feature allows usage of a small boot loader loading new
program into RAM, EPROM or FLASH
EEPROM storage via UART, SPI, I2C or
DoCD™ module.
External Memory Interface - Contains memory access related registers such as Data
Page High (DPH), Data Page Low (DPL) and
Data Pointer eXtended (DPX) registers. It performs the external Program and Data Memory
addressing and data transfers. Program fetch
cycle length can be programmed by user. This
feature is called Program Memory Wait States,
and allows core to work with different speed
program memories.
Synchronous
eXternal
Data
Memory
(SXDM) Interface – contains XDATA memory
access related logic allowing fast access to
synchronous memory devices. It performs the
external Data Memory addressing and data
transfers. This memory can be used to store
large variables frequently accessed by CPU,
improving overall performance of application.
Internal Data Memory Interface – Internal
Data Memory interface controls access into the
internal 256 bytes memory. It contains 8-bit
Stack Pointer (SP) register and related logic.
User SFRs Interface – Special Function Registers interface controls access to the special
registers. It contains standard and used defined registers and related logic. User defined
external devices can be quickly accessed
(read, written, modified) using all direct addressing mode instructions.
Interrupt Controller – Interrupt control module
is responsible for the interrupt manage system
for the external and internal interrupt sources.
It contains interrupt related registers such as
Interrupt Enable (IE), Interrupt Priority (IP),
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Extended Interrupt Enable (EIE), Extended
Interrupt priority (EIP) and (TCON) registers.
I/O Ports – Block contains 8051’s general purpose I/O ports. Each of port’s pin can be
read/write as a single bit or as an 8-bit bus
called P0, P1, P2, P3.
Power Management Unit – Block contains
advanced power saving mechanisms with
switchback feature, allowing external clock
control logic to stop clocking (Stop mode) or
run core in lower clock frequency (Power Management Mode) to significantly reduce power
consumption. Switchback feature allows
UARTs, and interrupts to be processed in full
speed mode if enabled. It is very desired when
microcontroller is planned to use in portable
and power critical applications.
DoCD™ Debug Unit – it’s a real-time hardware debugger provides debugging capability
of a whole SoC system. In contrast to other onchip debuggers DoCD™ provides non-intrusive
debugging of running application. It can halt,
run, step into or skip an instruction, read/write
any contents of microcontroller including all
registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read
occurred at particular address with certain data
pattern or without pattern. Two additional pins
CODERUN, DEBUGACS indicate the sate of
the debugger and CPU. CODERUN is active
when CPU is executing an instruction. DEBUGACS pin is active when any access is performed by DoCD™ debugger. The DoCD™
system includes JTAG interface and complete
set of tools to communicate and work with core
in real time debugging. It is built as scalable
unit and some features can be turned off to
save silicon and reduce power consumption. A
special care on power consumption has been
taken, and when debugger is not used it is
automatically switched in power save mode.
Finally whole debugger is turned off when debug option is no longer used.
Floating Point Unit – Block contains floating
point arithmetic IEEE-754 compliant instructions (C float, int, long int types supported). It
is used to execute single precision floating
point operations such as: addition, subtraction,
multiplication, division, square root, comparison absolute value of number and change of
All trademarks mentioned in this document
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sign. Basing on specialized CORDIC algorithm
a full set of trigonometric operations are also
allowed: sine, cosine, tangent, arctangent. It
also has built-in integer to floating point and
vice versa conversion instructions. FPU supports single precision real numbers, 16-bit and
32-bit signed integers. This unit has included
standard software interface allows easy usage
and interfacing with user C/ASM written programs.
MDU32 Multiply Divide Unit – It’s a fixed
point fast 16-bit and 32-bit multiplication and
division unit. It supports unsigned and 2’s
complement signed integer operands. The
MDU32 is controlled by dedicated direct memory access module (called DMA). All arguments and result registers are automatically
read and written back by internal DMA. This
unit has included standard software interface
allows easy usage and interfacing with user
C/ASM written programs. This module is replacement of older MDU.
Timers – System timers module. Contains two
16 bits configurable timers: Timer 0 (TH0,
TL0), Timer 1 (TH1, TL1) and Timers Mode
(TMOD) registers. In the timer mode, timer
registers are incremented every 12 CLK periods when appropriate timer is enabled. In the
counter mode the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are
opened (GATE0, GATE1). T0, T1 input pins
are sampled every CLK period. It can be used
as clock source for UARTs.
Timer 2 – Second system timer module contains one 16-bit configurable timer: Timer 2
(TH2, TL2), capture registers (RLDH, RLDL)
and Timer 2 Mode (T2MOD) register. It can
work as a 16-bit timer / counter, 16-bit autoreload timer / counter. It also supports compare capture unit if it’s presented in system. It
can be used as clock source for UART0.
Compare Capture Unit – The compare / capture / reload unit is one of the most powerful
peripheral units of the core. It can be used for
all kinds of digital signal generation and event
capturing such as pulse generation, pulse
width modulation, measurements etc.
Watchdog Timer – The watchdog timer is a
27-bit counter which is incremented every system clock periods (CLK pin). It performs system protection against software upsets.
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UART0 – Universal Asynchronous Receiver &
Transmitter module is full duplex, meaning it
can transmit and receive concurrently. Includes
Serial Configuration register (SCON), serial
receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning it
can commence reception of a second byte
before a previously received byte has been
read from the receive register. Writing to
SBUF0 loads the transmit register, and reading
SBUF0 reads a physically separate receive
register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized
by Timer 1 or Timer 2.
UART1 – Universal Asynchronous Receiver &
Transmitter module is full duplex, meaning it
can transmit and receive concurrently. Includes
Serial Configuration register (SCON1), serial
receiver and transmitter buffer (SBUF1) registers. Its receiver is double-buffered, meaning it
can commence reception of a second byte
before a previously received byte has been
read from the receive register. Writing to
SBUF1 loads the transmit register, and reading
SBUF1 reads a physically separate receive
register. Works in 3 asynchronous and 1 synchronous modes. UART1 is synchronized by
Timer 1.
Master I2C Unit – I2C bus controller is a Master module. The core incorporates all features
required by I2C specification. Supports both 7bit and 10-bit addressing modes on the I2C
bus. It works as a master transmitter and receiver. It can be programmed to operate with
arbitration and clock synchronization to allow it
operate in multi-master systems. Built-in timer
allows operation from a wide range of the input
frequencies. The timer allows to achieve any
non-standard clock frequency. The I2C controller supports all transmission modes: Standard,
Fast and High Speed up to 3400 kbs.
Slave I2C Unit – I2C bus controller is a Slave
module. The core incorporates all features
required by I2C specification. It works as a
slave transmitter/receiver depending on working mode determined by a master device. The
I2C controller supports all transmission modes:
Standard, Fast and High Speed up to 3400
kbs.
SPI Unit – it’s a fully configurable master/slave
Serial Peripheral Interface, which allows user
to configure polarity and phase of serial clock
signal SCK. It allows the microcontroller to
communicate with serial peripheral devices. It
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is also capable of interprocessor communications in a multi-master system. A serial clock
line (SCK) synchronizes shifting and sampling
of the information on the two independent serial data lines. SPI data are simultaneously
transmitted and received. SPI system is flexible enough to interface directly with numerous
standard product peripherals from several
manufacturers. Data rates as high as CLK/4.
Clock control logic allows a selection of clock
polarity and a choice of two fundamentally different clocking protocols to accommodate most
available synchronous serial peripheral devices. When the SPI is configured as a master,
software selects one of four different bit rates
for the serial clock. SPI automatically drives
slave select outputs SSO[7:0], and address
SPI slave device to exchange serially shifted
data. Error-detection logic is included to support interprocessor communications. A writecollision detector indicates when an attempt is
made to write data to the serial shift register
while a transfer is in progress. A multiplemaster mode-fault detector automatically disables SPI output drivers if more than one SPI
devices simultaneously attempts to become
bus master.
PROGRAM CODE SPACE
IMPLEMENTATION
The figure below shows an example Program Memory space implementation in systems with DP80390XP Microcontroller core.
The On-chip Program Memory located in address space between 0kB and 1kB is typically
used for BOOT code with system initialization
functions. This part of the code is typically implemented as ROM. The On-chip Program
Memory located in address space between
60kB and 64kB is typically used for timing critical part of the code e.g. interrupt subroutines,
arithmetic functions etc. This part of the code is
typically implemented as RAM and can be
loaded by the BOOT code during initialization
phase from Off-chip memory or through RS232
interface from external device. From the two
mentioned above spaces program code is
executed without wait-states and can achieve
a top performance up to 200 million instructions per second (many instructions executed
in one clock cycle). The Off-chip Program
Memory located in address space between
1kB and 60kB, and above 64 kB is typically
used for main code and constants. This part of
the code is usually implemented as ROM,
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SRAM or FLASH device. Because of relatively
long access time the program code executed
from mentioned above devices must be
fetched with additional Wait-States. Number of
required Wait-States depends on memory access time and DP80390XP clock frequency. In
most cases the proper number of Wait-States
cycles is between 2-5. The READY pin can be
also dynamically modulated e.g. by SDRAM
controller.
other applications whole program code can be
implemented as off-chip ROM or FLASH and
executed with required number Wait-State cycles.
0x7FFFFF
Off chip Memory
(implemented as ROM,
SRAM or FLASH)
0x00FFFF
0x00F000
On chip Memory
(implemented as RAM)
Off chip Memory
(implemented as ROM,
SRAM or FLASH)
0x000400
0x000000
On-chip Memory
(implemented as ROM)
The figure below shows a typical Program
Memories connections in system with
DP80390XP Microcontroller core.
prgramdatai
prgdatao
8
8
prgramwr
On-chip Memory
12
(implemented as RAM)
0 Wait-State access
prgaddr
10
prgromdata
i
DP80390XP
xdatai
8
ASIC or FPGA
chip
8
xdatao
xaddr
On-chip Memory
(implemented as ROM)
0 Wait-State access
Off-chip Memory
24
xprgrd
(implemented as
FLASH, or SRAM)
eg. 2-5 Wait-State
access
xprgwr
ready
Wait-States
manager
The described above implementation should be
treated as an example. All Program Memory
spaces are fully configurable. For timing-critical
applications whole program code can be implemented as on-chip ROM and (or) RAM and
executed without Wait-States, but for some
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PERFORMANCE
The following tables give a survey about the
Core area and performance in Programmable
Logic Devices after Place & Route (CPU features and peripherals have been included):
Device
FLEX10KE
ACEX1K
APEX20K
APEX20KE
APEX20KC
APEX-II
MERCURY
CYCLONE
CYCLONE-II
STRATIX
STRATIX-II
Speed grade
-1
-1
-1
-1
-7
-7
-5
-6
-6
-5
-3
Fmax
50 MHz
50 MHz
45 MHz
55 MHz
66 MHz
72 MHz
95 MHz
85 MHz
91 MHz
92 MHz
154 MHz
Core performance in ALTERA® devices
For a user the most important is application
speed improvement. The most commonly used
arithmetic functions and theirs improvement
are shown in table below. Improvement was
computed as {80C51 clock periods} divided by
{DP80390XP clock periods} required to execute an identical function. More details are
available in core documentation.
Function
8-bit addition (immediate data)
8-bit addition (direct addressing)
8-bit addition (indirect addressing)
8-bit addition (register addressing)
8-bit subtraction (immediate data)
8-bit subtraction (direct addressing)
8-bit subtraction (indirect addressing)
8-bit subtraction (register addressing)
8-bit multiplication
8-bit division
16-bit addition
16-bit subtraction
16-bit multiplication
32-bit addition
32-bit subtraction
32-bit multiplication
Average speed improvement:
Improvement
9,00
9,00
9,00
12,00
9,00
9,00
9,00
12,00
16,00
9,60
12,00
12,00
13,60
12,00
12,00
12,60
11,12
31386
33000
30000
27000
24000
21000
18000
15000
12000
9000
6000
3000
0
268
1550
80C51 (12MHz)
80C310 (33MHz)
DP80390XP (150MHz)
Area utilized by the each unit of DP80390XP
core in vendor specific technologies is summarized in table below.
Component
CPU*
DPTR1 register
DPTR0 decrement
DPTR1 decrement
DPTR0 & DPTR1 auto-switch
Timed Access protection
Interrupt Controller
INT2-INT6
Power Management Unit
I/O ports
Timers
Timer 2
UART0
UART1
Master I2C Unit
Slave I2C Unit
SPI Unit
Compare Capture Unit
Watchdog Timer
Multiply Divide Unit
Total area
Area
[LC]
[FFs]
1790
315
50
40
40
30
20
32
0
0
8
10
150
40
100
25
10
100
160
170
210
210
260
160
110
150
100
500
4360
5
35
50
60
60
60
120
70
55
60
45
105
1155
*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &
Internal & External Memory Interfaces, User SFRs Interface
Core components area utilization in all technologies except
STRATIX-II
Dhrystone Benchmark Version 2.1 was used to
measure Core performance. The following table gives a survey about the DP80390XP performance in terms of Dhrystone/sec and VAX
MIPS rating.
Device
Target
80C51
80C310
DP80390XP
STRATIX-II
Clock
frequency
12 MHz
33 MHz
150 MHz
Dhry/sec
(VAX MIPS)
268 (0.153)
1550 (0.882)
31386 (17.85)
Core performance in terms of Dhrystones
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Area
Component
CPU*
[LC]
[FFs]
1380
315
40
30
30
25
15
32
0
0
8
10
120
40
75
25
10
75
125
135
165
165
220
125
85
120
75
800
3815
5
35
50
60
60
60
120
70
55
60
45
105
1155
DPTR1 register
DPTR0 decrement
DPTR1 decrement
DPTR0 & DPTR1 auto-switch
Timed Access protection
Interrupt Controller
INT2-INT6
Power Management Unit
I/O ports
Timers
Timer 2
UART0
UART1
Master I2C Unit
Slave I2C Unit
SPI Unit
Compare Capture Unit
Watchdog Timer
Multiply Divide Unit 32
Total area
*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &
Internal & External Memory Interfaces, User SFRs Interface
Core components area utilization in STRATIX-II
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1
2
4
4
-
-
-
-
-
Fixed Point
Coprocessor
Floating Point
Coprocessor
I\O Ports
2
3
SPI
UART
1
1
2
Master I2C Bus
Controller
Slave I2C Bus
Controller
Timer/Counters
2
2
2
Watchdog
Data Pointers
2
5
15
Compare/Capture
Interrupt levels
64k 64k 8M 256 256 16M
64k 64k 8M 256 256 16M
64k 64k 8M 256 256 16M
Interrupt sources
Interface for
additional SFRs
Power Management Unit
Internal Data Memory
space
External Data Memory
space
External Data / Program
Memory Wait States
Stack space size
off-chip
10
10
10
on-chip ROM
DP80390CPU
DP80390
DP80390XP
Program
Memory
space
on-chip RAM
Design
Architecture speed grade
The main features of each DP80390 family member have been summarized in table below. It gives
a briefly member characterization helping user to select the most suitable IP Core for its application.
User can specify its own peripheral set (including listed below and the others) and requests the core
modifications.
-
-
DP80390 family of Pipelined High Performance Microcontroller Cores
4
4
-
-
-
-
DP8051 family of Pipelined High Performance Microcontroller Cores
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-
Fixed Point
Coprocessor
Floating Point
Coprocessor
1
2
SPI
2
3
Master I C Bus
Controller
Slave I2C Bus
Controller
I\O Ports
1
1
2
2
UART
2
2
2
Watchdog
Timer/Counters
2
5
15
Compare/Capture
Data Pointers
Interface for
additional SFRs
Power Management Unit
Internal Data Memory
space
External Data Memory
space
External Data / Program
Memory Wait States
Stack space size
off-chip
on-chip ROM
64k 64k 64k 256 256 16M
64k 64k 64k 256 256 16M
64k 64k 64k 256 256 16M
Interrupt levels
10
10
10
Interrupt sources
DP8051CPU
DP8051
DP8051XP
Program
Memory
space
on-chip RAM
Design
Architecture speed grade
The main features of each DP8051 family member have been summarized in table below. It gives
a briefly member characterization helping user to select the most suitable IP Core for its application.
User can specify its own peripheral set (including listed below and the others) and requests the core
modifications.
-
-
CONTACTS
For any modification or special request contact to DCD.
Headquarters:
Wroclawska 94
41-902 Bytom, POLAND
[email protected]
e-mail: [email protected]
tel.
: +48 32 282 82 66
fax
: +48 32 282 74 37
Distributors:
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