DP8051XP
Pipelined High Performance
8-bit Microcontroller
ver 3.10
OVERVIEW
DP8051XP is a ultra high performance,
speed optimized soft core of a single-chip 8bit embedded controller dedicated for operation with fast (typically on-chip) and slow (offchip) memories. The core has been designed
with a special concern about performance to
power consumption ratio. This ratio is extended by an advanced power management
unit PMU.
DP8051XP soft core is 100% binarycompatible with the industry standard 8051 8bit microcontroller. There are two configurations of DP8051XP: Harward where internal
data and program buses are separated, and
von Neumann with common program and external data bus. DP8051XP has Pipelined
RISC architecture 10 times faster compared
to standard architecture and executes 85-200
million instructions per second. This performance can also be exploited to great advantage in low power applications where the core
can be clocked over ten times more slowly
than the original implementation for no performance penalty.
DP8051XP is fully customizable, which
means it is delivered in the exact configuration
to meet users’ requirements. There is no need
to pay extra for not used features and wasted
silicon. It includes fully automated testbench
with complete set of tests allowing easy
package validation at each stage of SoC design flow.
All trademarks mentioned in this document
are trademarks of their respective owners.
CPU FEATURES
●
100% software compatible with industry
standard 8051
●
Pipelined RISC architecture enables to
execute instructions 10 times faster compared to standard 8051
●
24 times faster multiplication
●
12 times faster addition
●
2 Data Pointers (DPTR) for faster memory
blocks copying
○
Advanced INC & DEC modes
○
Auto-switch of current DPTR
●
Up to 256 bytes of internal (on-chip) Data
Memory
●
Up to 64K bytes of internal (on-chip) or
external (off-chip) Program Memory
●
Up to 16M bytes of external (off-chip) Data
Memory
●
User programmable Program Memory Wait
States solution for wide range of memories
speed
●
User programmable External Data Memory
Wait States solution for wide range of
memories speed
●
De-multiplexed Address/Data bus to allow
easy connection to memory
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
●
Dedicated signal for Program Memory
writes.
●
Interface for additional Special Function
Registers
●
Fully synthesizable, static synchronous
design with positive edge clocking and no
internal tri-states
○
●
Up to 8 interrupt sources from peripherals
Four 8-bit I/O Ports
○
Bit addressable data direction for each line
○
Read/write of single line and 8-bit group
●
Three 16-bit timer/counters
○
Timers clocked by internal source
●
Scan test ready
○
Auto reload 8/16-bit timers
●
2.0 GHz virtual clock frequency in a 0.35u
technological process
○
Externally gated event counters
●
PERIPHERALS
●
DoCD™ debug unit
○
Processor execution control
Run
○
8-bit asynchronous mode, fixed baud rate
○
9-bit asynchronous mode, fixed baud rate
○
9-bit asynchronous mode, variable baud rate
I2C bus controller - Master
○
7-bit and 10-bit addressing modes
Skip instruction
○
NORMAL, FAST, HIGH speeds
○
Multi-master systems supported
○
Clock arbitration and synchronization
○
User defined timings on I2C lines
○
Wide range of system clock frequencies
○
Interrupt generation
Read-write all processor contents
Program Memory
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
○
Synchronous mode, fixed baud rate
Step into instruction
Program Counter (PC)
○
○
●
Halt
○
Full-duplex serial port
Hardware execution breakpoints
●
I2C bus controller - Slave
Program Memory
○
NORMAL speed 100 kbs
Internal (direct) Data Memory
○
FAST speed 400 kbs
Special Function Registers (SFRs)
○
HIGH speed 3400 kbs
External Data Memory
○
Wide range of system clock frequencies
○
User defined data setup time on I2C lines
○
Interrupt generation
Hardware breakpoints activated at a certain
Program address (PC)
Address by any write into memory
●
SPI – Master and Slave Serial Peripheral
Interface
Address by any read from memory
○
Address by write into memory a required data
Address by read from memory a required data
○
●
Supports speeds up ¼ of system clock
Mode fault error
Three wire communication interface
Write collision error
Power Management Unit
○
Four transfer formats supported
○
Power management mode
○
System errors detection
○
Switchback feature
○
○
Stop mode
Allows operation from a wide range of system
clock frequencies (build-in 5-bit timer)
○
Interrupt generation
●
Extended Interrupt Controller
○
2 priority levels
○
Up to 7 external interrupt sources
●
Programmable Watchdog Timer
●
16-bit Compare/Capture Unit
○
All trademarks mentioned in this document
are trademarks of their respective owners.
Events capturing
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
○
Pulses generation
○
Digital signals generation
○
Gated timers
○
Sophisticated comparator
○
Pulse width modulation
○
Pulse width measuring
●
Fixed-Point arithmetic coprocessor
○
Multiplication - 16bit * 16bit
○
Division - 32bit / 16bit
○
Division - 16bit / 16bit
○
Left and right shifting - 1 to 31 bits
○
Normalization
●
Floating-Point
arithmetic
coprocessor
IEEE-754 standard single precision
○
FADD, FSUB - addition, subtraction
○
FMUL, FDIV- multiplication, division
○
FSQRT- square root
○
FUCOM - compare
○
FCHS - change sign
○
FABS - absolute value
●
Floating-Point math coprocessor - IEEE754 standard single precision real, word
and short integers
○
FADD, FSUB- addition, subtraction
○
FMUL, FDIV- multiplication, division
○
FSQRT- square root
○
FUCOM- compare
○
FCHS - change sign
○
FABS - absolute value
○
FSIN, FCOS- sine, cosine
○
FTAN, FATAN- tangent, arcs tangent
CONFIGURATION
The following parameters of the DP8051XP
core can be easy adjusted to requirements of
dedicated application and technology. Configuration of the core can be prepared by effortless
changing appropriate constants in package file.
There is no need to change any parts of the
code.
All trademarks mentioned in this document
are trademarks of their respective owners.
•
Internal Program Memory
type
- synchronous
- asynchronous
•
Internal Program ROM
Memory size
0 - 64kB
-
•
Internal Program RAM
Memory size
0 - 64kB
-
•
Internal Program Memory
fixed size
- true
- false
•
Second Data Pointer
(DPTR1)
- used
- unused
• DPTR0 decrement
- used
- unused
• DPTR1 decrement
- used
- unused
• Data Pointers auto-switch
- used
- unused
• Interrupts
-
• Timing access protection
- used
- unused
• Power Management Mode
- used
- unused
• Stop mode
- used
- unused
• DoCD debug unit
- used
- unused
subroutines
location
Besides mentioned above parameters all
available peripherals and external interrupts
can be excluded from the core by changing
appropriate constants in package file.
DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
◊
◊
IP Core implementation support
3 months maintenance
●
●
●
Delivery the IP Core updates, minor and
major versions changes
Delivery the documentation updates
Phone & email support
External Program Memory can be implemented as ROM or RAM located in address range between ROMsize ÷ RAMsize.
♦
INTERNAL DATA MEMORY:
The DP8051XP can address Internal
Data Memory of up to 256 bytes The Internal Data Memory can be implemented as
Single-Port synchronous RAM.
♦
EXTERNAL DATA MEMORY:
The DP8051XP soft core can address up
to 16 MB of External Data Memory. Extra
DPX (Data Pointer eXtended) register is
used for segments swapping.
♦
USER SPECIAL FUNCTION REGISTERS:
Up to 60 External (user) Special Function Registers (ESFRs) may be added to
the DP8051XP design. ESFRs are memory
mapped into Direct Memory between addresses 80 hex and FF hex in the same
manner as core SFRs and may occupy any
address that is not occupied by a core
SFR.
♦
WAIT STATES SUPPORT:
The DP8051XP soft core is dedicated for
operation with wide range of Program and
Data memories. Slow Program and External Data memory may assert a memory
Wait signal to hold up CPU activity.
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC implementation.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA bitstreams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restriction
except One Year license where time of use is
limited to 12 months.
●
Single Design license for
○
VHDL, Verilog source code called HDL
Source
○
Encrypted, or plain text EDIF called Netlist
●
One Year license for
○
●
Encrypted Netlist only
Unlimited Designs license for
○
HDL Source
○
Netlist
●
Upgrade from
○
HDL Source to Netlist
○
Single Design to Unlimited Designs
DESIGN FEATURES
♦
PROGRAM MEMORY:
The DP8051XP soft core is dedicated for
operation with Internal and External Program Memory. Internal Program Memory
can be implemented as:
○ ROM located in address range between
0000h ÷ (ROMsize-1)
○ RAM located in address range between
(RAMsize-1) ÷ FFFFh
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
BLOCK DIAGRAM
SYMBOL
clk
reset
clk
reset
ramdatai(7:0)
ramdatao(7:0)
ramaddr(7:0)
ramoe
ramwe
sfrdatao(7:0)
sfraddr(7:0)
sfroe
sfrwe
sfrdatai(7:0)
prgromdatai(7:0)
prgramdatai(7:0)
xdatai(7:0)
ready
iprgromsize(2:0)
iprgramsize(2:0)
prgdatao(7:0)
prgaddr(15:0)
prgramwr
xdatao(7:0)
xaddr(23:0)
xdataz
xdatard
xdatawr
xprgrd
xprgwr
int0
int1
int2
int3
int4
int5
int6
docddatai
port0i(7:0)
port1i(7:0)
port2i(7:0)
port3i(7:0)
docddatao
docdclk
stop
pmm
port0o(7:0)
port1o(7:0)
port2o(7:0)
port3o(7:0)
t0
gate0
t1
gate1
capture0
capture1
capture2
capture3
rxd1i
mscli
msdai
msclhs
msclo
msdao
sscli
ssdai
ssclo
ssdao
ss
si
mi
scki
External
Memory
Interface
Internal Data
Memory
Interface
sfrdatai(7:0)
sfrdatao(7:0)
sfraddr(7:0)
sfroe
sfrwe
User SFR
Interface
docddatai
docddatao
docdclk
t2
t2ex
ALU
Control Unit
Interrupt
Controller
I/O Ports
DoCD™
Debug Unit
Floating
Point Unit
rxd1o
rxd1i
txd1
rxd0o
txd0
rxd1o
txd1
Program
Memory
Interface
ramdatai(7:0)
ramdatao(7:0)
ramaddr(7:0)
ramoe
ramwe
capture0
capture1
capture2
capture3
t2
t2ex
rxd0i
prgromdatai(7:0)
prgramdatai(7:0)
prgdatao(7:0)
prgaddr(15:0)
prgramwr
xdatai(7:0)
xdatao(7:0)
xramaddr(23:0)
xramdataz
xdatard
xdatawr
xprgrd
xprgwr
ready
Opcode
Decoder
Power
Management
Unit
Timer 2
Master
I2C Unit
sscli
ssclo
ssdai
ssdao
Slave
I2C Unit
t0
gate0
t1
gate1
rxd0o
rxd0i
txd0
SPI Unit
so
si
mo
mi
scko
scki
sckz
ss
sso(7:0)
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
stop
pmm
UART 0
sso(7:0)
so
mo
scko
sckz
All trademarks mentioned in this document
are trademarks of their respective owners.
port0i(7:0)
port1i(7:0)
port2i(7:0)
port3i(7:0)
port0o(7:0)
port1o(7:0)
port2o(7:0)
port3o(7:0)
Watchdog
Timer
UART 1
msclhs
mscli
msclo
msdai
msdao
int0
int1
int2
int3
int4
int5
int6
Multiply
Divide Unit
Timers 0 & 1
Compare
Capture Unit
iprgromsize(2:0)
iprgramsize(2:0)
PINS DESCRIPTION
PIN
TYPE
DESCRIPTION
prgdatao[7:0]
output Data bus for internal program memory
prgramwr
output Internal program memory write
xaddr[23:0]
output Address bus for external memories
clk
input
Global clock
xdatao[7:0]
output Data bus for external memories
reset
input
Global reset
xdataz
output Turn xdata bus into ‘Z’ state
port0i[7:0]
input
Port 0 input
xprgrd
output External program memory read
port1i[7:0]
input
Port 1 input
xprgwr
output External program memory write
port2i[7:0]
input
Port 2 input
xramrd
output External data memory read
port3i[7:0]
input
Port 3 input
xramwr
output External data memory write
iprgramsize[2:0]
input
Size of on-chip RAM CODE
ramaddr[7:0]
output Internal Data Memory address bus
iprgromsize[2:0]
input
Size of on-chip ROM CODE
ramdatao[7:0]
output Data bus for internal data memory
prgramdata[7:0]
input
Data bus from int. RAM prog. memory
ramoe
output Internal data memory output enable
prgromdata[7:0]
input
Data bus from int. ROM prog. memory
ramwe
output Internal data memory write enable
xdatai[7:0]
input
Data bus from external memories
sfraddr[6:0]
output Address bus for user SFR’s
ready
input
External memory data ready
sfrdatao[7:0]
output Data bus for user SFR’s
ramdatai[7:0]
input
Data bus from internal data memory
sfroe
output User SFR’s read enable
sfrdatai[7:0]
input
Data bus from user SFR’s
sfrwe
output User SFR’s write enable
int0
input
External interrupt 0
docddatao
output DoCD™ data output
int1
input
External interrupt 1
docdclk
output DoCD™ clock line
int2
input
External interrupt 2
pmm
output Power management mode indicator
int3
input
External interrupt 3
stop
output Stop mode indicator
int4
input
External interrupt 4
rxd0o
output Serial receiver output 0
int5
input
External interrupt 5
rxd1o
output Serial receiver output 1
int6
input
External interrupt 6
txd0
output Serial transmitter output 0
t0
input
Timer 0 input
txd1
output Serial transmitter output 1
t1
input
Timer 1 input
msclo
output Master I2C clock output
t2
input
Timer 2 input
msclhs
output High speed Master I2C clock line
gate0
input
Timer 0 gate input
msdao
output Master I2C data output
gate1
input
Timer 1 gate input
msclo
output Slave I2C clock output
t2ex
input
Timer 2 gate input
msdao
output Slave I2C data output
capture0
input
Timer 2 capture 0 line
sso[7:0]
output SPI slave select lines
capture1
input
Timer 2 capture 1 line
so
output SPI slave output
capture2
input
Timer 2 capture 2 line
mo
output SPI master output
capture3
input
Timer 2 capture 3 line
scko
output SPI clock output
rxdi0
input
Serial receiver input 0
sckz
output SPI clock line tri-state buffer control
rxdi1
input
Serial receiver input 1
mscli
input
Master I2C clock line input
msdai
input
Master I2C data input
sscli
input
Slave I2C clock line input
ssdai
input
Slave I2C data input
ss
input
SPI slave select
si
input
SPI slave input
mi
input
SPI master input
scki
input
SPI clock input
docddatai
input
DoCD™ data input
port0o[7:0]
output Port 0 output
port1o[7:0]
output Port 1 output
port2o[7:0]
output Port 2 output
port3o[7:0]
output Port 3 output
prgaddr[15:0]
output Internal program memory address bus
All trademarks mentioned in this document
are trademarks of their respective owners.
UNITS SUMMARY
ALU – Arithmetic Logic Unit performs the
arithmetic and logic operations during execution of an instruction. It contains accumulator
(ACC), Program Status Word (PSW), (B) registers and related logic such as arithmetic unit,
logic unit, multiplier and divider.
Opcode Decoder – Performs an instruction
opcode decoding and the control functions for
all other blocks.
Control Unit – Performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and
manages execution of all microcontroller tasks.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
Program Memory Interface – Contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program
Memory can be also written. This feature allows usage of a small boot loader loading new
program into ROM, RAM, EPROM or FLASH
EEPROM storage via UART, SPI, I2C or
DoCD™ module.
External Memory Interface - Contains memory access related registers such as Data
Page High (DPH), Data Page Low (DPL) and
Data Pointer eXtended (DPX) registers. It performs the external Program and Data Memory
addressing and data transfers. Program fetch
cycle length can be programmed by user. This
feature is called Program Memory Wait States,
and allows core to work with different speed
program memories.
Internal Data Memory Interface – Internal
Data Memory interface controls access into the
internal 256 bytes memory. It contains 8-bit
Stack Pointer (SP) register and related logic.
User SFRs Interface – Special Function Registers interface controls access to the special
registers. It contains standard and used defined registers and related logic. User defined
external devices can be quickly accessed
(read, written, modified) using all direct addressing mode instructions.
Interrupt Controller – Interrupt control module
is responsible for the interrupt manage system
for the external and internal interrupt sources.
It contains interrupt related registers such as
Interrupt Enable (IE), Interrupt Priority (IP),
Extended Interrupt Enable (EIE), Extended
Interrupt priority (EIP) and (TCON) registers.
I/O Ports – Block contains 8051’s general purpose I/O ports. Each of port’s pin can be
read/write as a single bit or as an 8-bit bus
called P0, P1, P2, P3.
Power Management Unit – Block contains
advanced power saving mechanisms with
switchback feature, allowing external clock
control logic to stop clocking (Stop mode) or
run core in lower clock frequency (Power Management Mode) to significantly reduce power
consumption. Switchback feature allows
UARTs, and interrupts to be processed in full
speed mode if enabled. It is very desired when
microcontroller is planned to use in portable
and power critical applications.
All trademarks mentioned in this document
are trademarks of their respective owners.
DoCD™ Debug Unit – it’s a real-time hardware debugger provides debugging capability
of a whole SoC system. In contrast to other onchip debuggers DoCD™ provides non-intrusive
debugging of running application. It can halt,
run, step into or skip an instruction, read/write
any contents of microcontroller including all
registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read
occurred at particular address with certain data
pattern or without pattern. The DoCD™ system
includes three-wire interface and complete set
of tools to communicate and work with core in
real time debugging. It is built as scalable unit
and some features can be turned off to save
silicon and reduce power consumption. A special care on power consumption has been
taken, and when debugger is not used it is
automatically switched in power save mode.
Finally whole debugger is turned off when debug option is no longer used.
Floating Point Unit – Block contains floating
point arithmetic IEEE-754 compliant instructions (C float, int, long int types supported). It
is used to execute single precision floating
point operations such as: addition, subtraction,
multiplication, division, square root, comparison absolute value of number and change of
sign. Basing on specialized CORDIC algorithm
a full set of trigonometric operations are also
allowed: sine, cosine, tangent, arctangent. It
also has built-in integer to floating point and
vice versa conversion instructions. FPU supports single precision real numbers, 16-bit and
32-bit signed integers. This unit has included
standard software interface allows easy usage
and interfacing with user C/ASM written programs.
Multiply Divide Unit – It’s a fixed point fast
16-bit and 32-bit multiplication and division
unit. It provides shift and normalize operations,
additionally. All operations are performed using
unsigned integer numbers. The MDU contains
MD0 to MD5 operands, the result registers and
one control register called ARCON. This unit
has included standard software interface allows easy usage and interfacing with user
C/ASM written programs.
Timers – System timers module. Contains two
16 bits configurable timers: Timer 0 (TH0,
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
TL0), Timer 1 (TH1, TL1) and Timers Mode
(TMOD) registers. In the timer mode, timer
registers are incremented every 12 CLK periods when appropriate timer is enabled. In the
counter mode the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are
opened (GATE0, GATE1). T0, T1 input pins
are sampled every CLK period. It can be used
as clock source for UARTs.
Timer 2 – Second system timer module contains one 16-bit configurable timer: Timer 2
(TH2, TL2), capture registers (RLDH, RLDL)
and Timer 2 Mode (T2MOD) register. It can
work as a 16-bit timer / counter, 16-bit autoreload timer / counter. It also supports compare capture unit if it’s presented in system. It
can be used as clock source for UART0.
Compare Capture Unit – The compare / capture / reload unit is one of the most powerful
peripheral units of the core. It can be used for
all kinds of digital signal generation and event
capturing such as pulse generation, pulse
width modulation, measurements etc.
Watchdog Timer – The watchdog timer is a
27-bit counter which is incremented every system clock periods (CLK pin). It performs system protection against software upsets.
UART0 – Universal Asynchronous Receiver &
Transmitter module is full duplex, meaning it
can transmit and receive concurrently. Includes
Serial Configuration register (SCON), serial
receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning it
can commence reception of a second byte
before a previously received byte has been
read from the receive register. Writing to
SBUF0 loads the transmit register, and reading
SBUF0 reads a physically separate receive
register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized
by Timer 1 or Timer 2.
UART1 – Universal Asynchronous Receiver &
Transmitter module is full duplex, meaning it
can transmit and receive concurrently. Includes
Serial Configuration register (SCON1), serial
receiver and transmitter buffer (SBUF1) registers. Its receiver is double-buffered, meaning it
can commence reception of a second byte
before a previously received byte has been
read from the receive register. Writing to
SBUF1 loads the transmit register, and reading
SBUF1 reads a physically separate receive
All trademarks mentioned in this document
are trademarks of their respective owners.
register. Works in 3 asynchronous and 1 synchronous modes. UART1 is synchronized by
Timer 1.
Master I2C Unit – I2C bus controller is a Master module. The core incorporates all features
required by I2C specification. Supports both 7bit and 10-bit addressing modes on the I2C
bus. It works as a master transmitter and receiver. It can be programmed to operate with
arbitration and clock synchronization to allow it
operate in multi-master systems. Built-in timer
allows operation from a wide range of the input
frequencies. The timer allows to achieve any
non-standard clock frequency. The I2C controller supports all transmission modes: Standard,
Fast and High Speed up to 3400 kbs.
Slave I2C Unit – I2C bus controller is a Slave
module. The core incorporates all features
required by I2C specification. It works as a
slave transmitter/receiver depending on working mode determined by a master device. The
I2C controller supports all transmission modes:
Standard, Fast and High Speed up to 3400
kbs.
SPI Unit – it’s a fully configurable master/slave
Serial Peripheral Interface, which allows user
to configure polarity and phase of serial clock
signal SCK. It allows the microcontroller to
communicate with serial peripheral devices. It
is also capable of interprocessor communications in a multi-master system. A serial clock
line (SCK) synchronizes shifting and sampling
of the information on the two independent serial data lines. SPI data are simultaneously
transmitted and received. SPI system is flexible enough to interface directly with numerous
standard product peripherals from several
manufacturers. Data rates as high as CLK/4.
Clock control logic allows a selection of clock
polarity and a choice of two fundamentally different clocking protocols to accommodate most
available synchronous serial peripheral devices. When the SPI is configured as a master,
software selects one of four different bit rates
for the serial clock. SPI automatically drives
slave select outputs SSO[7:0], and address
SPI slave device to exchange serially shifted
data. Error-detection logic is included to support interprocessor communications. A writecollision detector indicates when an attempt is
made to write data to the serial shift register
while a transfer is in progress. A multiplemaster mode-fault detector automatically disables SPI output drivers if more than one SPI
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
devices simultaneously attempts to become
bus master.
PROGRAM CODE SPACE
The figure below shows a typical Program
Memories connections in system with
DP8051XP Microcontroller core.
IMPLEMENTATION
The figure below shows an example Program Memory space implementation in systems with DP8051XP Microcontroller core. The
On-chip Program Memory located in address
space between 0kB and 1kB is typically used
for BOOT code with system initialization functions. This part of the code is typically implemented as ROM. The On-chip Program Memory located in address space between 60kB
and 64kB is typically used for timing critical
part of the code e.g. interrupt subroutines,
arithmetic functions etc. This part of the code is
typically implemented as RAM and can be
loaded by the BOOT code during initialization
phase from Off-chip memory or through RS232
interface from external device. From the two
mentioned above spaces program code is
executed without wait-states and can achieve
a top performance up to 200 million instructions per second (many instructions executed
in one clock cycle). The Off-chip Program
Memory located in address space between
1kB and 60kB is typically used for main code
and constants. This part of the code is usually
implemented as ROM, SRAM or FLASH device. Because of relatively long access time
the program code executed from mentioned
above devices must be fetched with additional
Wait-States. Number of required Wait-States
depends on memory access time and
DP8051XP clock frequency. In most cases the
proper number of Wait-States cycles is between 2-5. The READY pin can be also dynamically modulated e.g. by SDRAM controller.
0xFFFF
0xF000
8
prgramdatai
8
prgdatao
prgramwr
On-chip Memory
12
(implemented as RAM)
0 Wait-State access
prgaddr
10
prgromdata
i
DP8051XP
8
ASIC or FPGA
chip
xdatai
8
xdatao
xaddr
On-chip Memory
(implemented as ROM)
0 Wait-State access
Off-chip Memory
16
xprgrd
(implemented as
FLASH, or SRAM)
eg. 2-5 Wait-State
access
xprgwr
ready
Wait-States
manager
The described above implementation should be
treated as an example. All Program Memory
spaces are fully configurable. For timing-critical
applications whole program code can be implemented as on-chip ROM and (or) RAM and
executed without Wait-States, but for some
other applications whole program code can be
implemented as off-chip ROM or FLASH and
executed with required number Wait-State cycles.
On chip Memory
(implemented as RAM)
Off chip Memory
(implemented as ROM,
SRAM or FLASH)
0x0400
0x0000
On-chip Memory
(implemented as ROM)
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
PERFORMANCE
The following tables give a survey about the
Core area and performance in ASICs Devices
(CPU features and peripherals have been included):
Device
0.25u typical
0.25u typical
Optimization
area
speed
Fmax
100 MHz
200 MHz
40000
35000
30000
25000
20000
15000
10000
268
5000
Core performance in ASIC devices
For a user the most important is application
speed improvement. The most commonly used
arithmetic functions and theirs improvement
are shown in table below. Improvement was
computed as {80C51 clock periods} divided by
{DP8051XP clock periods} required to execute
an identical function. More details are available
in core documentation.
41850
45000
1550
0
80C51 (12MHz)
Area utilized by the each unit of DP8051XP
core in vendor specific technologies is summarized in table below.
Component
Function
8-bit addition (immediate data)
8-bit addition (direct addressing)
8-bit addition (indirect addressing)
8-bit addition (register addressing)
8-bit subtraction (immediate data)
8-bit subtraction (direct addressing)
8-bit subtraction (indirect addressing)
8-bit subtraction (register addressing)
8-bit multiplication
8-bit division
16-bit addition
16-bit subtraction
16-bit multiplication
32-bit addition
32-bit subtraction
32-bit multiplication
Average speed improvement:
Improvement
9,00
9,00
9,00
12,00
9,00
9,00
9,00
12,00
16,00
9,60
12,00
12,00
13,60
12,00
12,00
12,60
11,12
Dhrystone Benchmark Version 2.1 was used to
measure Core performance. The following table gives a survey about the DP8051XP performance in terms of Dhrystone/sec and VAX
MIPS rating.
Device
Target
80C51
80C310
DP8051XP
0.25u
80C310 (33MHz)
DP8051XP (200MHz)
CPU*
DPTR1 register
DPTR0 decrement
DPTR1 decrement
DPTR0 & DPTR1 auto-switch
Timed Access protection
Interrupt Controller
INT2-INT6
Power Management Unit
I/O ports
Timers
Timer 2
UART0
UART1
Master I2C Unit
Slave I2C Unit
SPI Unit
Compare Capture Unit
Watchdog Timer
Multiply Divide Unit
Total area
Area
[Gates]
[FFs]
5900
280
300
100
100
50
100
32
8
10
500
40
350
25
50
400
600
600
700
700
900
550
450
550
400
1700
15000
5
35
50
60
60
60
120
70
55
60
45
105
1125
*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &
Internal & External Memory Interfaces, User SFRs Interface
Core components area utilization
Clock
Dhry/sec
frequency
(VAX MIPS)
12 MHz
268 (0.153)
33 MHz
1550 (0.882)
200 MHz 41850 (23,800)
Core performance in terms of Dhrystones
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
1
2
4
4
-
-
-
-
-
Fixed Point
Coprocessor
Floating Point
Coprocessor
2
3
SPI
I\O Ports
1
1
2
Master I2C Bus
Controller
Slave I2C Bus
Controller
UART
2
2
2
Watchdog
Timer/Counters
2
5
15
Compare/Capture
Data Pointers
Interface for
additional SFRs
Power Management Unit
Internal Data Memory
space
External Data Memory
space
External Data / Program
Memory Wait States
Stack space size
off-chip
on-chip ROM
64k 64k 64k 256 256 16M
64k 64k 64k 256 256 16M
64k 64k 64k 256 256 16M
Interrupt levels
10
10
10
Interrupt sources
DP8051CPU
DP8051
DP8051XP
Program
Memory
space
on-chip RAM
Design
Architecture speed grade
The main features of each DP8051 family member have been summarized in table below. It gives
a briefly member characterization helping user to select the most suitable IP Core for its application.
User can specify its own peripheral set (including listed below and the others) and requests the core
modifications.
-
-
DP8051 family of Pipelined High Performance Microcontroller Cores
4
4
-
-
-
-
DP80390 family of Pipelined High Performance Microcontroller Cores
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
-
Fixed Point
Coprocessor
Floating Point
Coprocessor
1
2
SPI
I\O Ports
2
3
Master I C Bus
Controller
Slave I2C Bus
Controller
UART
1
1
2
2
Timer/Counters
2
2
2
Watchdog
Data Pointers
2
5
15
Compare/Capture
Interrupt levels
Interface for
additional SFRs
Interrupt sources
64k 64k 16M 256 256 16M
64k 64k 16M 256 256 16M
64k 64k 16M 256 256 16M
Power Management Unit
Internal Data Memory
space
External Data Memory
space
External Data / Program
Memory Wait States
Stack space size
off-chip
10
10
10
on-chip ROM
DP80390CPU
DP80390
DP80390XP
Program
Memory
space
on-chip RAM
Design
Architecture speed grade
The main features of each DP80390 family member have been summarized in table below. It gives
a briefly member characterization helping user to select the most suitable IP Core for its application.
User can specify its own peripheral set (including listed below and the others) and requests the core
modifications.
-
-
CONTACTS
For any modification or special request contact to DCD.
Headquarters:
Wroclawska 94
41-902 Bytom, POLAND
e-mail: iinnffoo@
@ddccdd..ppll
tel.
: +48 32 282 82 66
fax
: +48 32 282 74 37
Field Office:
Texas Research Park
14815 Omicron Dr. suite 100
San Antonio, TX 78245, USA
USS@
@ddccdd..ppll
e-mail: iinnffooU
tel.
: +1 210 422 8268
fax
: +1 210 679 7511
Distributors:
Please check hhtttpp::///w
ww
ww
w..ddccdd..ppll//aappaarrttnn..pphhpp
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.