DELTA LCP-1250RJ3SR-S

LCP-1250RJ3SR-S
RoHS Compliant Copper Small Form-factor Pluggable (SFP)
Transceiver for Gigabit Ethernet with SGMII Interface
Features
Compatible with specifications for IEEE
802.3z/Gigabit Ethernet
„ Compliant with MSA specifications for Small
Form Factor Pluggable (SFP) Ports
„ Hot-Pluggable SFP footprint
„ Compliant with industry standard RFT
electrical connector and cage
„ EEPROM with serial ID functionality
„ Auto-Negotiation follows IEEE 802.3u Clause
28 (1000BASE-T) and Cisco SGMII Spec.
„ Compatible with the Cisco specification of
SGMII interface. LCP-1250RJ3SR-S supports
the SGMII interface without clock on MAC side
„ Gigabit PHY device is integrated internally
„ Internal PHY IC is configurable by host
system software via SFP 2-wire-interface
„
Applications
Description
The LCP-1250RJ3SR-S is 3.3V copper small
form-factor plug-able (SFP) transceiver. It offers
full duplex 1000Mb/s Ethernet by transporting
data over standard CAT 5 UTP cable (category 5
unshielded twisted pair), with RJ-45 connection.
It takes signals from both CAT 5 UTP cable and
the SFP SerDes interface.
The system host (MAC) must enable SGMII
auto-negotiation while LCP-1250RJ3SR-S is
operated to setup the partner linking at one
speed of 10/100/1000Mbps by 1000Base-T
auto-negotiation.
The Gigabit Ethernet SFP ports on host
systems can work well plugging with both of
Delta fiber SFP transceiver and Delta copper
SFP transceiver, so there is no need of software
to configure MAC on host system.
„
10/100/1000Mbps Copper LAN
„
Gigabit Ethernet over copper
„
Switch to switch interface
„
Switched backplane applications
„
Gigabit Ethernet Interface of File Server
Performance
LCP-1250RJ3SR-S data link up to 100m on
standard CAT 5 UTP
At enhance, the software can configure the
PHY device inner LCP-1250RJ3SR-S via SFP
two-wire-interface.
Dec. 18. 2006 Rev. 1.01
DELTA ELECTRONICS, INC.
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LCP-1250RJ3SR-S
Product Selection
Part Number
Link Indicator on
RX_LOS Pin
Auto-negotiation
on MAC side
Enabled by default
MAC side Interface
Auto-negotiation
on copper side
Enabled by default
Speed Mode
LCP-1250RJ3SR
*note 1
N/A
LCP-1250RJ3SR-L
*note 2
Available
LCP-1250RJ3SR-S
*note 3
N/A
1000Base-X
Yes
SGMII
1.25Gbps SerDes
1000Base-T
1.25Gbps SerDes
1000Base-T
SGMII without clock
1000Base-T
1000Mbps only
1000Mbps only
10/100/1000Mbps
Notes:
1. This part supports the 1000 Base-T with SerDes interface by default. It can operate in 10/100/1000
Base-T with SGMII interface by reconfiguration of the PHY within the SFP.
2. This part uses the SFP’s Rx-Los pin for link indication and 1000 Base-T auto-negotiation should be
disabling on the host system. It can operate in 10/100/1000 Base-T with SGMII interface by
reconfiguration of the PHY within the SFP.
3. This part supports the 10/100/1000 Base-T with SGMII interface by default.
Absolute Maximum Ratings
Parameter
Storage Temperature
Supply Voltage
Symbol
Ts
VCC
Min.
−40
0
Typ.
Max.
85
5
Unit
ºC
V
Note
Symbol
TA
VCC
Min.
0
3.135
Typ.
Max.
70
3.465
Unit
ºC
V
Note
Symbol
ICC
Min.
Typ.
350
Max.
400
Unit
mA
Note
VD,TX
ZTX
VDISH
VDISL
0.5
80
2.0
0
2.4
120
VCC+0.3
0.8
V
Ohm
V
V
1
VD,RX
ZRX
tr,Rx/ tf,Rx
0.35
80
2
120
V
Ohm
ps
3
Recommended Operating Conditions
Parameter
Ambient Operating Temperature
Supply Voltage
Electrical Characteristics
(TA=0 ºC to 70 ºC, VCC=3.135V to 3.465V)
Parameter
Supply Current
Transmitter
Data Input Differential Voltage
Differential Input Impedance
Transmitter Disable Input-High
Transmitter Disable Input-Low
Receiver
Data Output Differential Voltage
Differential Output Impedance
Data Output Rise/Fall Time
100
100
180
4
Dec. 18. 2006 Rev. 1.01
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LCP-1250RJ3SR-S
Notes:
1).
Internally AC coupled and terminated to 100-Ohm differential load.
2).
Pull up to VCC with a 4.7K – 10K Ohm resistor on host Board
3).
Internally AC coupled, but requires a 100-Ohm differential termination at MAC side.
4).
These are unfiltered 20%~80% values
SFP Transceiver Electrical Pad Layout
Dec. 18. 2006 Rev. 1.01
DELTA ELECTRONICS, INC.
Page 3 of 8
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LCP-1250RJ3SR-S
Pin Function Definitions
Pin Num. Name
1
VeeT
2
TX_Fault
Function
Transmitter Ground
Transmitter Fault Indication
3
TX_Disable
Transmitter Disable
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MOD-DEF2
MOD-DEF1
MOD-DEF0
Rate Select
LOS
VeeR
VeeR
VeeR
RDRD+
VeeR
VccR
VccT
VeeT
TD+
TDVeeT
Module Definition 2
Module Definition 1
Module Definition 0
Not Connect
Loss of Signal
Receiver Ground
Receiver Ground
Receiver Ground
Inverse Received Data Out
Received Data Out
Receiver Ground
Receiver Power
Transmitter Power
Transmitter Ground
Transmitter Data In
Inverse Transmitter Data In
Transmitter Ground
Plug Seq. Notes
1
Note 5
3
Note 1 - Function not available
Note 2 - Module disables on high or
3
open
3
Note 3 - Two-wire serial ID interface
3
Note 3 - Two-wire serial ID interface
3
Note 3 - grounded in module
3
Function not available
3
Note 4 – Function not available
1
Note 5
1
Note 5
1
Note 5
3
Note 6
3
Note 6
1
Note 5
2
Note 7 - 3.3V ± 5%
2
Note 7 - 3.3V ± 5%
1
Note 5
3
Note 8
3
Note 8
1
Note 5
Plug Seq.: Pin engagement sequence during hot plugging.
Notes:
1)
TX_Fault is not supported and tied to ground.
2)
TX_Disable is an input that is used to reset the chip of Gigabit Ethernet PHY inside the copper SFP.
It is pulled up within the
module with a 4.7 – 10 K Ω resistor.
Low (0 – 0.8V):
Transmitter on
(>0.8, < 2.0V):
Undefined
High (2.0 – 3.465V): Transmitter Disabled
Open:
3)
Transmitter Disabled
These are the module definition pins.
voltage shall be VccT or VccR.
They should be pulled up with a 4.7K – 10KΩ resistor on the host board.
MOD-DEF 0 is grounded in the module to indicate that the module is present.
The pull-up
MOD-DEF 1 and
MOD-DEF 2 are the clock and data lines of the two-wire serial interface, respectively.
4)
LOS (Loss of Signal) is not available and tied to ground.
5)
VeeR and VeeT are internally connected within the copper SFP.
6)
RD+ and RD- are the received differential outputs, and they are AC-coupled 100Ω differential lines that should be terminated with
100Ω (differential) at user’s SERDES.
The AC coupling is done inside the copper SFP and thus not required on the host board.
The differential voltage swing will be between 250mV and 625 mV, while properly terminated.
7)
VccR and VccT are the receiver and transmitter power supplies, and they are internally connected within the copper SFP.
The
power rail is defined as 3.3V ±5% at the SFP connector pin.
8)
TD+ and TD- are the transmitted differential inputs, and they are terminated with 100Ω differential load inside the module.
The
Dec. 18. 2006 Rev. 1.01
DELTA ELECTRONICS, INC.
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LCP-1250RJ3SR-S
AC coupling is done inside the module, and thus not required on the host board.
Recommend Circuit Schematic
Dec. 18. 2006 Rev. 1.01
DELTA ELECTRONICS, INC.
Page 5 of 8
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LCP-1250RJ3SR-S
Made in CHINA
FS
Package Outline Drawing for Metal Housing
Dec. 18. 2006 Rev. 1.01
DELTA ELECTRONICS, INC.
Page 6 of 8
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LCP-1250RJ3SR-S
LCP-1250RJ3SR-S EEPROM Serial ID Memory Contents (Two-Wire Address 0xA0)
LCP-1250RJ3SR-S provides 128byte EEPROM, which can be accessed via the 2-wire serial communication
protocol per SFP MSA with a device address of 0xA0. It is designed of the Atmel AT24C01A EEPROM.
Address
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Hex ASCII Address Hex ASCII Address Hex ASCII Address Hex ASCII Address Hex ASCII Address Hex ASCII
03
25
20
50
33
3
75
SN
100
00
125
00
04
26
20
51
53
S
76
SN
101
00
126
00
00
27
20
52
52
R
77
SN
102
00
127
00
00
28
20
53
2D
78
SN
103
00
00
29
20
54
53
S
79
SN
104
00
00
30
20
55
20
80
SN
105
00
08
31
20
56
30
0
81
SN
106
00
00
32
20
57
30
0
82
SN
107
00
00
33
20
58
30
0
83
SN
108
00
00
34
20
59
30
0
84
DC Note 3
109
00
00
35
20
60
00
85
DC
110
00
01
36
00
61
00
86
DC
111
00
0D
37
00
62
00
87
DC
112
00
00
38
00
63
CS1 Note 1
88
DC
113
00
00
39
00
64
00
89
DC
114
00
00
40
4C
L
65
12
90
DC
115
00
00
41
43
C
66
00
91
DC
116
00
00
42
50
P
67
00
92
00
117
00
64
43
2D
68
SN Note 2
93
00
118
00
00
44
31
1
69
SN
94
00
119
00
44
D
45
32
2
70
SN
95
CS2 Note 4
120
00
45
E
46
35
5
71
SN
96
00
121
00
4C
L
47
30
0
72
SN
97
00
122
00
54
T
48
52
R
73
SN
98
00
123
00
41
A
49
4A
J
74
SN
99
00
124
00
Notes:
1)
Byte 63: Check sum of bytes 0-62.
2)
Byte 68-83 (SN): Serial number.
3)
Byte 84-91 (DC): Date code.
4)
Byte 95 (CS2): Check sum of bytes 64-94.
5)
Byte 128--255 had been set hex. 00.
LCP-1250RJ3SR-S Internal PHY Register (Two-Wire Address 0xAC)
LCP-1250RJ3SR-S is internally designed of physical layer IC (Marvell 88E1111), which can be programmed
via two-wire interface with the device address 0xAC. For details of PHY IC registers in 88E1111, see
Marvell document “Alaska Ultra 88E1111 Integrated Gigabit Ethernet Transceiver”.
Electromagnetic Emission
FCC Class A, CE Class A, VCCI Class A, C-Tick
Dec. 18. 2006 Rev. 1.01
DELTA ELECTRONICS, INC.
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LCP-1250RJ3SR-S
Related Product
1. LCP-1250RJ3SR, SFP Copper Transceiver, IEEE 802.3z/Gigabit Ethernet, standard CAT 5 UTP
2. GBIC-1250RJ3SR, GBIC Transceiver, 1250Mb/s, data link up to 100 m on standard CAT 5 UTP.
3. LCP-1250RJ3SR-L, SFP Copper Transceiver with Rx-Los Indicator, IEEE 802.3z/Gigabit Ethernet,
standard CAT 5 UTP
References
1. “Small Form-factor Pluggable (SFP) Transceiver MultiSource Agreement (MSA)”, September 14, 2000
2. “IEEE Std 802.3, 2002 Edition”. IEEE Standards Department, 2002.
3. “AT24C01A/02/04/08/16 2-Wire Serial CMOS EEPROM”, Atmel Corporation. www.atmel.com
4. “Alaska Ultra 88E1111 Integrated 10/100/1000 Gigabit Ethernet Transceiver”,
Marvell Corporation. www.marvell.com
5. “Serial-GMII Specification Revision 1.8”, Cisco System Corporation. Www.cisco.com,
Dec. 18. 2006 Rev. 1.01
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