EM198810 Datasheet INTEGRATED CIRCUIT Elan Design DATA SHEET EM198810 2.4 GHz ISM Band Transceiver/Framer IC Preliminary Data Sheet ELAN MICROELECTRONICS CORP. No.12, Innovation 1st RD., Science-based Industrial Park Hsin Chu, Taiwan, R.O.C. TEL: (03) 5639977 FAX: (03) 5782037(SL) 5630118 (SA2) This spec is subject to change without any notice 1 / 18 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design CONTENTS 1. Features 2. Block Diagram 3. Pins/pads name and pins/pads location 3.1 3.2 3.3 3.4 4. Pins name Package outline Pads name and location Order information Digital Base Band Interface 4.1 4.2 SPI Command Format Register Information 4.2.1 Package type define and FIFO point set 4.2.2 Digital Interface 4.2.3 Typical Register Values 4.2.4 State Diagram 5. 6. 7. Electrical Characteristics Application Reference Design Soldering This spec is subject to change without any notice 2 / 18 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design 2.4 GHZ ISM BAND TRANSCEIVER/FRAMER IC 1. FEATURES The EM198810 is a CMOS integrated circuit that performs all functions from the antenna to the microcontroller for transmission and reception of a 2.4GHz digital data. This transceiver IC integrates most of the functions required for data transmission into a single integrated circuit. Additionally, the programmability implemented reduces significantly external components count, board space requirements and external adjustments. Key Features: - Combines 2.4 GHz GFSK RF transceiver with 8-bit data framer function - Eliminates need for external software or hardware FIFO; offloads MCU for other tasks - Simple microprocessor interface – 4 wires for SPI, plus 3 wires for RST/buffer control - Each transmit, receive buffer is 64 bytes deep - Long packets are possible if buffers are read/written before overflow/underflow occurs - Always 1Mbps over-the-air symbol rate, regardless of MCU speed or architecture - Preamble can be 1 to 8 bytes - Supports 1, 2, 3, or 4 word address (up to 64 bits) - Various Payload data formats to eliminate DC offset, enhance receive clock recovery and BER - Programmable data whitening - Supports Forward Error Correction (FEC): none, 1/3, or 2/3 - Supports 16-bit CRC - Baseband output clock available - Power management for minimizing current consumption - 5x5mm QFN package with minimum RF parasitic - Lead-free packaging and dice is available on request Applications - Wireless devices that need quick time-to-market - Simple and fast wireless data networks - Cordless headsets and Cellular Phones - Wireless streaming audio - Wireless voice and VOIP - Wireless Skype earphone - Home and factory automation - Wireless security and access control - Battery Powered wireless devices This spec is subject to change without any notice 3 / 18 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design 1.1 Description The Elan EM198810 IC is a low-cost, fully integrated CMOS radio frequency (RF) transceiver block, combined with a 64-byte buffered framer block. The RF transceiver block is a self-contained, fasthopping GFSK data modem, optimised for use in the widely available 2.4 GHz ISM band. It contains transmit, receive, VCO and PLL functions, including an on-chip channel filter and resonator, thus minimizing the need for external components. The receiver utilizes extensive digital processing for excellent overall performance, even in the presence of interference and transmitter impairments. Transmit power is digitally controlled. The low-IF receiver architecture results in sensitivity to -80dBm or better, with impressive selectivity. In normal applications, the EM198810 is connected to a low cost microcontroller(ex:EM78P451S). In normal application The on-chip framer processes and stores the RF data in the background, unloading this critical timing function from the MCU. This lowers MCU speed requirements, expedites product development time, and frees the MCU for implementing additional product features. The framer register settings determine the over-the-air formatting characteristics. Many configurations are possible, depending on the user’s specific needs. Raw transmit data is easily sent over-the-air as a complete frame of data, with preamble, address, payload, and CRC. Receiving data is just the opposite, using the preamble to train the receiver clock recovery, then the address is checked, then the data is reverse formatted for receive, followed by CRC. All of this is done in hardware to ease the programming and overhead requirements of the baseband MCU. For longer battery life, power consumption is minimized by automatic enabling of the various transmit, receive, PLL, and PA sections, depending on the instantaneous state of the chip. A sleep mode is also provided for ultra low current consumption. This product is available in 32-lead 5x5 mm JEDEC standard QFN package, featuring an exposed pad on the bottom for best RF characteristics. Lead-free RoHS compliant packaging is available on request. This spec is subject to change without any notice 4 / 18 24.Dec.2006 This spec is subject to change without any notice ANT TX MOD_trim TR Switch 5 / 18 GFSK Receiver 2.4GHZ RF Synthesizer (APLL) Analog PLL CLK 2.4GHZ GFSK Transmitter +1.8V RF Vdd LDO_Vout Clock Recov. freq. control TX Data Low Dropout Voltage Reg. LDO_Vdd Digital State Machine and Register Block Oscillator / Buffer Vdd_io Data Framing Buffer and Logic Vdd INTEGRATED CIRCUIT XTALI XTALO BRCLK RXCLK RESET_n PKT_FLAG FIFO_FLAG SPI_MOSI SPI_MISO SPI_CLK SPI_SS SPI Bus EM198810 Datasheet Elan Design 2. Block diagram - Fig. 1 – 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design 3. Pins names and pins location 3.1 Pins names SYMBOL Type PIN PWR PWR -GND 50ΩRF PWR --PWR PWR ---O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PKT_FLAG RXCLK O O 15 16 FIFO_FLAG VDD GND SPI_SS SPI_MOSI SPI_CLK RESET_n O PWR GND I I I I 17 18 19 20 21 22 23 SPI_MISO VDD_IO LDO_VDD LDO_OUT LOD_TUNE GND VDD XTALO XTALI GND O PWR PWR PWR -GND PWR AO AI GND 24 25 26 27 28 29 30 31 32 VDD VDD NC GND ANT VDD NC NC VDD VDD NC NC NC BRCLK Exposed pad DESCRIPTION Power supply voltage. DO NOT CONNECT. Reserved for factory test. Ground connection. RF input/output. Power supply voltage. DO NOT CONNECT. Reserved for factory test. Power supply voltage. DO NOT CONNECT. Reserved for factory test. Outputs 1MHz TX symbol clock, 12MHz APLL, or crystal clock. See register definitions for details. Transmit/Receive packet process flag. Receiver symbol timing clock recovery output. Fixed at 1MHz fundamental rate. FIFO full/empty flag. Power supply voltage. Ground connection. Enable line for the SPI bus. Active low. Data input for the SPI bus. Clock line for the SPI bus. When RESET_n is low, most of the chip shuts down to conserve power. When raised high, RESET_n is used to turn on the chip,restoring all registers to their default value. Data output for the SPI bus. Vdd for the digital i/o pins. Nominally +3.3 VDC. Unregulated input to the on-chip LDO volt. regulator. +1.8V output of the on-chip LDO voltage regulator. Fine-tune for the on-chip LDO voltage regulator. Ground connection. Power supply voltage. Output of the crystal oscillator gain block. Input to the crystal oscillator gain block. Ground connection. - Table 1 – This spec is subject to change without any notice 6 / 18 24.Dec.2006 RESET_n SPI_CLK SPI_MOSI SPI_SS GND VDD FIFO_FLAG 23 22 21 20 19 18 17 Elan Design SPI_MISO INTEGRATED CIRCUIT 24 EM198810 Datasheet VDD_IO 25 16 RXCLK LDO_VDD 26 15 PKT_FLAG LDO_VOUT 27 14 BRCLK LDO_TUNE 28 13 NC GND 29 12 NC VDD 30 11 NC XTALO 31 10 VDD XTALI 32 9 VDD 3 4 5 6 7 8 NC GND ANT VDD NC NC 2 VDD 1 1 VDD EM198810 - Figure 2 – 3.2 Package Outline QFN32 Lead Exposed Pad Package, 5x5 mm Pkg. 0.5mm Pitch (JEDEC) MO-220-A This spec is subject to change without any notice 7 / 18 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design 3.3 Pads name and location SYMBOL PAD no PLL_VDD(A) RF_VSS(A) VCO_GDD(A) nc RF_VSS(A) ANTb(A) RF_VSS(A) ANT(A) RF_VSS(A) RF_VDD(A) Injp(A) Injp(A) IF_VDD(A) VCO_VDD(A) AMS_AVDD(A) MONIp(A) MONIn(A) TP_BG_IV/TP_VTUNE(A) BRCLK(D) BPKTCTL(D) RXDATA(D) RXCLK(D) testse(D) BXTLEN(D) TEST1(D) VDD_DIG(D) VSS_DIG(D) BnDEN(D) TEST2(D) BDDATA(D) BDCLK(D) BnPWR(D) BDATA1(D) spi_select(D) VDD_IO(D) ckpha(D) LDO_VDD(A) LDO_OUT_VDD(A) LDO_TUNE(A) AMS_DVSS(A) AMS_DVDD(A) XTALO(A) XTALI(A) VCO_VSS(A) Center pad position X;Y in microns 35.837 ; 1622.464 35.836 ; 1498.956 35.837 ; 1378.956 35.387 ; 1257.956 35.383 ; 1018.956 35.837 ; 897.956 35.837 ; 778.957 35.789 ; 657.956 35.835 ; 583.952 35.837 ; 418.957 35.837 ; 178.096 222.918 ; 35.006 341.926 ; 35.006 462.016 ; 35.006 581.926 ; 35.006 702.926 ; 35.006 1464.189 ; 35.005 1584.188 ; 35.006 1820.067 ; 34.006 1940.067 ; 34.006 2081.185 ; 219.891 2081.185 ; 339.891 2081.185 ; 459.891 2081.185 ; 579.891 2081.185 ; 699.891 2081.185 ; 821.027 2081.185 ; 941.027 2081.185 ; 1059.839 2081.185 ; 1179.893 2081.185 ; 1299.893 2081.185 ; 1420.890 2081.185 ; 1539.891 2081.185 ; 1659.889 1885.495 ; 1804.847 1762.415 ; 1804.847 1641.438 ; 1804.847 1445.424 ; 1804.847 1318.773 ; 1803.847 1199.684 ; 1803.847 1075.434 ; 1803.847 955.348 ; 1803.847 833.526 ; 1803.946 671.538 ; 1803.946 550.438 ; 1803.847 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 - Table 2 - 3.4 Order information Type number Name EM198810W QFN32 EM198810H Bare die This spec is subject to change without any notice Package Description Plastic, quad flat package; no leads; 32 terminals; body 5 x 5 x 0.8 mm available 8 / 18 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design 4 Digital Base Band Interface 4.1 SPI Command Format The SPI interface is used to program the IC via the 4 pins SPI_CLK, SPI_SS, SPI_MOSI and SPI_MISO. The SPI_MOSI and SPI_CLK pins are used to load data into an internal shift register. The SPI_MOSI and SPI_CLK pins are use to send data to microcontroller. The data are loaded into the shift register and sent to microcontroller on the rising edge of the clock SPI_CLK and latched on the rising edge of the SPI_SS signal. When the SPI_SS pin is high, the data stored in the shift register is retained even if a SPI_CLK is applied. When the SPI_SS pin is low the data can be rewritten and resent. Inputs timing of the SPI_CLK, SPI_SS, SPI_MOSI and SPI_MISOD are shown in the Fig.2. Format 1 CKPHA = 0: SPI_CLK SPI_SS SPI_MOSI SPI_MISO R/W A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 S7 S6 S5 S4 S3 S2 S1 S0 Format 2 CKPHA = 1: SPI_CLK SPI_SS SPI_MOSI R/W A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SPI_MISO S7 S5 S3 S2 S1 S0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 S6 S4 - Fig. 3 – 4.2 Register Information 4.2.1 Package type define and FIFO point set preamble SYNC trailer payload CRC Automatically set FIFO write_point=0 when RX received SYNC Automatically set FIFO read_point=0 when RX received SYNC or after transmit SYNC when TX - Figure 4 – * Preamble: 1 ~ 8 bytes programmable * SYNC: 32/48/64 bits programmable as device syncword * Trailer: 4~16 bits programmable * Payload: TX/RX data, there are 4 data types: raw data, 8_10 bits, Manchester, interleave with FEC option * CRC: 16 bit CRC is option Note: For transmit, it is needed to clear FIFO write point before application write in data via access reg82[15]. This spec is subject to change without any notice 9 / 18 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design 4.2.2 Digital Interface It is very simple interface with application, consisting of SPI interface plus two handshake signals (Table 2). The EM198810 SPI can only support slave mode. Pin SPI_CLK SPI_SS SPI_MOSI SPI_MISO PKT_FLAG FIFO_FLAG RESET_n Description SPI clock input SPI slave select input SPI data in SPI data out Packet TX/RX flag FIFO full/empty Reset input, active low - Table 3 - 4.2.3 Typical Register Values The following register values (Table 3) are recommended for the Elan Microelectronics details define refer to registers definitions Reg. address Read/Write 0 2 4 5 9 14 16 18 19 20 21 22 23 24 25 26 48 51 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default value (Hexadecimal) 0000 00C1 0688 0041 0003 6617 0000 FC00 0014 8103 0962 2602 2602 30C0 3814 5304 1800 4000 - Table 4 - Recommend value (12MHz crystal frequency) (Hexadecimal) CD51 0061 3CD0 00A1 3003 6697 F000 E000 2114 819C 6962 0402 0802 B080 7819 6704 5800 A000 For more detail description about digital base band interface, please refer to application note AN198810-1. For the latest register value recommendations, please contact Elan Microelectronics technical group. This spec is subject to change without any notice 10 / 18 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design 4.2.4 State Diagram off sleep RESET_n = 1 power on SPI_SS=1 reg48[2]=1 & SPI_SS=1 register initialization wake up idle reg7[8]=1 reg7[7]=1 tx_start rx_start wait_txsyn wait_rxsyn reg50[15:8]us tx_done reg51[15:8]us tx_pa_on tx packet done or reg7[8]=0 rx_data rx packet done or reg7[7]=0 reg50[7:0]us rx_done tx_data - Figure 5 - This spec is subject to change without any notice 11 / 18 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design 5.Electrical Characteristics 5.1 Absolute Maximum Rating Parameter Symbol Min. Operating Temp. Storage Temp. VDD_IO Supply Voltage VDD Supply Voltage Applied Voltages to Other Pins Input RF Level Output Load mismatch (Z0=50 ohm) TOP Rating Typ. Unit Max. -40 -55 +85 ℃ TSTORAGE +125 ℃ VDDIO_MAX +3.7 VDC VDD_MAX +2.5 VDC VOTHER -0.3 +3.7 VDC PIN +10 dBm VSWROUT 10:1 VSWR - Table 5 Note: 1.Absoute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics section below. 2.These devices are electro-static sensitive. Devices should be transported and stored in antistatic containers. Equipment and personnel contacting the devices need to be properly grounded. Cover workbenches with grounded conductive mats. 5.2 Characteristics The following specifications are guaranteed for TA=25℃, VDD=1.80±0.18VDC, unless otherwise noted: Parameter Current Consumption Current Consumption - TX Current Consumption - RX Current Consumption – DEEP IDLE Current Consumption – SLEEP Digital Inputs Logic input high Logic input low Input Capacitance Input Leakage Current Digital Outputs Logic output high Logic output low Output Capacitance Output Leakage Current Rise/Fall Time Clock Signals BRCLK output frequency Symbol Specification Min. Typ. Max. IDD_TX IDD_RX Unit Test Condition and Notes IDD_D_IDLE 26 25 1.9 mA mA mA IDD_SLP 3.5 uA VIH VIL C_IN 0.8VDD_io 0 VDD_io 0.8 10 10 V V pF uA 0.8VDD_io VDD_io 0.4 10 10 5 V V pF uA nS I_LEAK_IN VOH VOL C_OUT I_LEAK_OUT T_RISE_OUT FBRCLK 1, 12, or xtal Freq. SPI_CLK rise, fall time Tr_spi SPI_CLK frequency range Overall Transceiver Operating Frequency Range FSPI 0 F_OP 2402 This spec is subject to change without any notice RF Synthesizer and VCO: OFF (see Reg. 21) MHz Depends on Register settings. 200 12 nS Always either: 1 MHz Tx clock, 12 MHz APLL clock (Tx, Rx, and Idle), or the buffered 12 MHz crystal oscillator frequency. Requirement for error-free register reading, writing. MHz 2482 12 / 18 POUT = nominal output power MHz 24.Dec.2006 EM198810 Datasheet Antenna port mismatch (Z0=50Ω) INTEGRATED CIRCUIT VSWR_I <2:1 VSWR Receive mode. Meas. using 50 VSWR_O <2:1 VSWR Transmit mode. Meas. using 50 Receive Section: @ BER≦0.1% Receiver sensitivity Maximum useable signal -20 Input 3rd order IIP3 -14 intercept point Data (Symbol) rate TS Min. Carrier/Interference ratio: @ BER≦0.1% Co-Channel Interference CI_cochannel Adjacent Ch. Interference, CI_1 1MHz offset Adjacent Ch. Interference, CI_2 2MHz offset -85 ohm balun. ohm balun. -80 -11 1 uS -60 dBm desired signal. -60 dBm desired signal. -30 dB CI_3 -40 dB -60 dBm desired signal. Interference at 2 MHz below desired signal. -67 dBm desired signal. CI_image -23 -9 dB CI_image_11 -34 -20 dB Out-of-Band Blocking 9 -1.5 dBm Meas. At antenna pin. dBm dBm dB dB Adjacent Ch. Interference, > 3MHz offset Image Frequency Interference Adjacent interference to Image (1MHz) Elan Design OBB_1 -10 dBm OBB_2 -27 dBm OBB_3 -27 dBm OBB_4 -10 dBm Transmit Section: Reg. 9, bits 15-8 set to 00000000 RF Output Power PAV +2 Modulation Characteristics 280 314 Peak FM 00001111 △f1avg Demodulation. pattern 01010101 230 △f2max pattern ISI, % Eye Open 80 △f2avg/△ f1avg Zero Crossing Error ZCERR -125 In-Band Spurious Emission +/- 550kHz IBS_1 2MHz offset IBS_2 >3MHz offset IBS_3 Out-of-Band Spurious Emission Operation OBS_O_1 <-60 OBS_O_2 -45 OBS_O_3 OBS_O_4 RF VCO and PLL Section Typical PLL lock range TX, RX Frequency Tolerance Channel (Step) Size SSB Phase Noise This spec is subject to change without any notice 11 0 FLOCK -60 dBm desired signal. Image freq. is always 2 MHz higher than desired signal. -67 dBm desired signal. Always 3 MHz higher than desired signal. 30 MHz to 2000 Meas. with MHz ACX 2000 MHz to 2400 BF2520 ceramic MHz 2500 MHz to 3000 filter on ant. pin. MHz 3000 MHz to 12.75 Desired sig.-70dBm. GHz dBm Power Level 0 350 KHz KHz For at least 99.9% of all ∆f2max % meas. 1010 data sequence referenced to 00001111 data sequence +125 nS +/- 1/8 of Symbol Period -20 -40 -60 dBc dBm dBm -36 -30 dBm 30 MHz ~ 1 GHz dBm 1 GHz ~ 12.75 GHz, <-60 -47 <-65 -47 dBm 1.8 GHz ~ 1.9 GHz dBm 5.15 GHz ~ 5.3 GHz 2340 2560 -1 -95 -115 13 / 18 excludes desired signal. MHz ppm Same as XTAL pins frequency tolerance MHz dBc/Hz 550KHz offset dBc/Hz 2MHz offset 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Crystal oscillator freq. range (Reference Frequency) Crystal oscillator digital trim range, typ. RF PLL Settling Time Out-of-Band Spur. Emissions 12 -12 Max. Load Capacitance MHz Designed for 12 MHz crystal reference freq. +12 ppm uS dBm 30 MHz ~ 1 THOP OBS_1 75 <-75 150 -57 OBS_2 -68 -47 LDO Voltage Regulator Section Dropout Voltage Vdo Quiescent current Iq Max_Cout Elan Design GHz dBm 1 GHz ~ 12.75 GHz TBD 6 V uA 1.0 uF DLE state, Synthesizer and VCO ON. Measured during Receive state No-load current consumed by LDO reg. Ensures stability of the high speed LDO V.R. - Table 6 - This spec is subject to change without any notice 14 / 18 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design 6. Application Circuit Typical Application * Quartz crystal 5.0x3.2 mm TXC P/N: 7B12000028 Note 1: Jumper CKPHA pin 28 t0 +1.8V or GND to set SPI clock phase as desired. C6 Y1 2 3 1 4 12pF +1.8V 12 MHz xtal R2 C7 2.2k C8 100nF R1 12pF Note 1 680k NC SPI_CLK PKT_FLAG 15 BRCLK 14 13 9 NC NC 23 RESET_n 22 SPI_CLK 21 SPI_MOSI 20 SPI_SS 19 +1.8V VDD VDD 8 GND NC NC 7 EM198810 VDD 12 A1 Printed "F" antenna SPI_SS NC 6 2 ANT 11 5 SPI_MOSI VDD Z=50 ohm 25 RESET_n 10 1 VDD_IO 27 26 LDO_VDD LDO_TUNE VDD 4 GND SPI_MISO SPI_MISO 18 FIFO_FLAG 17 FIFO_FLAG RXCLK 3 24 GND 16 2.2uF 2 LDO_VOUT 28 29 GND 30 VDD 31 32 C2 C1 100nF VDD XTALO 1 XTALI 33 Die +1.8V U1 C5 100nF Power +3.3V +1.8V MCU interface Note: Different crystals or layout changes may require different R/C values. +1.8V PKT_FLAG C3 100nF clk. out. (optional) C4 10nF Simple, low-power (0dBm) 2.4GHz RF Transceiver with Framing and Data buffers - Figure 6 - BOM list Comment 10pF 12pF 10nF 100nF 2.2uF 0 ohm 2.2k 680k 12MHz EM198810 CON1x14 Description Capacitor Capacitor Capacitor Capacitor Capacitor Resistor Resistor Resistor Crystal IC Connector This spec is subject to change without any notice Designator C8 C9 C6 C1 C3 C5 C7 C2 R4 R2 R1 Y1 U1 P1 - Table 7 - 15 / 18 Quantity 1 1 1 4 1 1 1 1 1 1 1 Footprint SMD-0603 SMD-0603 SMD-0603 SMD-0603 SMD-0603 SMD-0603 SMD-0603 SMD-0603 OSC 5x3.2 QFN 32 5x5 HDR1x14 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design PCB layout Top layer Bottom layer - Figure 7 - Wireless Personal Area Network Solution SPI BUS VOLTAGE REG. (Low Dropout) 2.4GHz GFSK TRANSMITTER SPI T/R SW EM198810 DIGITAL STATE MACHINE DATD FRAMING BUFFER & & REGISTER BLOCK LOGIC EM78P451S MICROCONTROLLER GND I/O 2.4GHz GFSK RECEIVER CLOCK RECOV. & XTAL VDD I/O Elan Wireless personal area network Total Solution - Fig. 8 – This spec is subject to change without any notice 16 / 18 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design 7. SOLDERING Reflow soldering requires paste to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing, throughput times vary between 100 and 300 seconds depending on heating method. Recommendation: Follow IPC/JEDEC J-STD-020B Condition: Average ramp-up rate (183℃ to peak): 3℃/sec. max. Preheat: 100 ~ 150℃ 60 ~ 120 sec. Temperature maintained above 183℃: 60 ~ 150sec. Time within 5℃ of actual peak temperature: 10 ~ 30sec. Peak temperature: 240+0/-5℃ Ramp-down rate: 6℃/sec. max. Time 25℃ to peak temperature: 6 minutes max. Cycle interval: 5 minutes IR Reflow Standard : IPC/JEDEC J-STD-020B Peak: 240+0/-5℃ Slope: Max. 3℃/sec (183℃ to peak) Ramp down rate Max. 6℃/sec. 183℃ Preheat: 100 ~ 150℃ 10~30 sec. 25℃ 60 ~ 150 sec. 60 ~ 120 sec. Time: sec. - Fig. 9 - This spec is subject to change without any notice 17 / 18 24.Dec.2006 EM198810 Datasheet INTEGRATED CIRCUIT Elan Design DATA SHEET STATUS Data Sheet Status Objective specification Product Status Definitions Development This data sheet contains data from the objective specification for product development. Elan Microelectronics reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Elan Microelectronics reserves the right to change the specification without notice in order to improve the design and supply the best possible product. This data sheet contains data from the production specification. Elan Microelectronics reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Preliminary specification Qualification Product specification Production DISCLAIMERS Life support policy.—These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Elan Microelectronics customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Elan Microelectronics for any damages resulting from such application. Right to make changes.—Elan Microelectronics reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Elan Microelectronics assumes no responsibility or liability for these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. ELAN MICROELECTRONICS CORPORATION Hong Kong: Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, TAIWAN 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Elan (HK) Microelectronics Corporation, Ltd. Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 This spec is subject to change without any notice USA: Flat A, 19F., World Tech Centre, 95 How Ming Street, Kwun Tong Kowloon, HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 [email protected] Elan Information Technology Group (U.S.A.) 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8225 Fax: +1 408 366-8220 Shanghai: Elan Microelectronics Shanghai, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 21 5080-3866 Fax: +86 21 5080-4600 18 / 18 24.Dec.2006