EM77930 USB + BB Controller Product Specification DOC. VERSION 1.0 ELAN MICROELECTRONICS CORP. August 2007 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright © 2007 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Headquarters: Hong Kong: USA: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Elan (HK) Microelectronics Corporation, Ltd. Flat A, 19F., World Tech Centre 95 How Ming Street, Kwun Tong Kowloon, HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 [email protected] Elan Information Technology Group (USA) Shenzhen: Shanghai: Elan Microelectronics Shenzhen, Ltd. Elan Microelectronics Shanghai, Ltd. 3F, SSMEC Bldg., Gaoxin S. Ave. I Shenzhen Hi-tech Industrial Park (South Area), Shenzhen CHINA 518057 Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 #23, Zone 115, Lane 572, Bibo Rd. Zhangjiang Hi-Tech Park Shanghai, CHINA 201203 Tel: +86 21 5080-3866 Fax: +86 21 5080-4600 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8225 Fax: +1 408 366-8220 Contents Contents 1 2 3 4 5 6 7 General Description.....................................................................................................1 Features ........................................................................................................................1 2.1 Core...................................................................................................................... 1 2.2 Oscillators/System Clocks ................................................................................... 2 2.3 Input and Output (I/O) Pins.................................................................................. 2 2.4 Timers and Counters ........................................................................................... 2 2.5 Interrupt Sources and Features........................................................................... 2 2.6 Baseband ............................................................................................................. 3 2.7 Universal Serial Bus (USB) ................................................................................. 4 2.8 Pulse Width Modulation (PWM)........................................................................... 4 2.9 Built-in Voltage Regulator .................................................................................... 4 Pin Assignment ............................................................................................................5 Pin Description.............................................................................................................6 Block Diagram..............................................................................................................7 Memory .........................................................................................................................8 6.1 Program Memory ................................................................................................. 8 6.2 RAM–Register...................................................................................................... 9 Function Description.................................................................................................29 7.1 Special Purpose Registers ................................................................................ 29 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.1.8 7.1.9 7.1.10 7.1.11 7.1.12 7.1.13 7.1.14 7.1.15 7.1.16 7.1.17 7.1.18 7.1.19 7.1.20 Accumulator – ACC .......................................................................................... 29 Indirect Addressing Contents – IAC0 and IAC1 ............................................... 29 Program Counter HPC and LPC ...................................................................... 29 Status Register –SR ......................................................................................... 29 RAM Bank Selector – RAMBS0 and RAMBS1 ................................................ 30 ROM Page Selector – ROMPS ........................................................................ 30 Indirect Addressing Pointers – IAP0 and IAP1 ................................................. 30 Indirect Address Pointer Direction Control Register – IAPDR.......................... 31 Table Look-up Pointers – LTBL and HTBL ...................................................... 31 Stack Pointer – STKPTR .................................................................................. 31 Repeat Counter – RPTC .................................................................................. 31 Real Time Clock Counter – RTCC.................................................................... 31 Interrupt Flag Register – INTF.......................................................................... 31 Key Wake-up Flag Register – KWUAIF and KWUBIF ..................................... 32 I/O Port Registers – PTA ~ PTF........................................................................ 32 16-bit Free Run Counter (FRC) – LFRC, HFRC and LFRCB .......................... 32 PWM Duty – DT0L/DT0H ................................................................................. 32 PWM Period – PRD0L/PRD0H......................................................................... 32 PWM Duty Latch – DL0L/DL0H........................................................................ 32 BB Address Register – RFAAR ........................................................................ 32 Product Specification (V1.0) 08.20.2007 • iii Contents 7.1.21 BB Data Buffer Register – RFDB ..................................................................... 32 7.1.22 BB Data Read/Write Control Register – RFACR .............................................. 33 7.1.23 BB Interrupt Flag Register – RFINTF ............................................................... 33 7.2 Dual Port Register.............................................................................................. 33 7.3 System Status, Control and Configuration Registers........................................ 33 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.3.12 7.4 8 USB Status, Control and Configuration Registers ............................................ 38 7.5 Code Option (ROM-0x2FFF) ............................................................................. 38 Base Band (BB)..........................................................................................................39 8.1 BB: Standard Interface to the RFW102 Series.................................................. 39 8.1.1 8.1.2 8.1.3 8.1.4 8.2 Features............................................................................................................ 39 Description........................................................................................................ 40 I/O and Package Description............................................................................ 41 BB Architecture ................................................................................................. 42 BB Description ................................................................................................... 43 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 8.2.10 8.2.11 8.2.12 8.2.13 8.2.14 8.2.15 iv • Peripherals Enable Control – PRIE .................................................................. 33 Interrupts Enable Control – INTE ..................................................................... 34 Key Wake-up Enable Control – KWUAIE and KWUBIE................................... 34 External Interrupts Edge Control – EINTED..................................................... 35 I/O Control Registers – IOCA~IOCF ................................................................ 35 Pull-up Resistance Control Registers for Ports – PUCA~PUCF ...................... 35 Open Drain Control Registers of Port B – ODCB............................................. 35 Timer Clock Counter Controller – TCCC .......................................................... 36 Free Run Counter Controller – FRCC .............................................................. 36 Watchdog Timer Controller – WDTC ................................................................ 37 PWM Control Register – PWMCR.................................................................... 38 BB Interrupt Control Register – RFINTE .......................................................... 38 Reset ................................................................................................................ 43 Power Saving Modes........................................................................................ 43 8.2.2.1 Power-Down Mode ............................................................................ 43 8.2.2.2 Idle Mode ........................................................................................... 43 Preamble Correlation........................................................................................ 44 Refresh Bit ........................................................................................................ 44 Bit Structure ...................................................................................................... 45 CRC .................................................................................................................. 46 RX FIFO............................................................................................................ 46 TX FIFO ............................................................................................................ 47 Interrupt Driver.................................................................................................. 48 Packet Size....................................................................................................... 49 NET_ID and NODE_ID Filters .......................................................................... 49 Carrier-Sense ................................................................................................... 50 8.2.12.1 RFWaves Carrier-Sense Algorithm ................................................... 50 Receiver Reference Capacitor Discharge ........................................................ 52 Changing the BB Configuration ........................................................................ 52 Input Synchronizer............................................................................................ 52 Product Specification (V1.0) 08.20.2007 Contents 8.3 Register Description........................................................................................... 53 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.3.9 8.3.10 8.3.11 8.3.12 8.3.13 8.3.14 8.3.15 8.3.16 8.4 Interrupt Registers ............................................................................................. 63 8.4.1 8.4.2 Interrupt Enable Register (IER) ........................................................................ 63 Interrupt Identification Register (IIR)................................................................. 64 8.5 List of BB Register Mapping .............................................................................. 65 8.6 MCU BB Control Registers ................................................................................ 66 8.6.1 8.6.2 9 Bit Length Register (BLR)................................................................................. 53 Preamble Low Register (PRE-L) ...................................................................... 53 Preamble High Register (PRE-H)..................................................................... 53 Packet Parameter Register (PPR).................................................................... 53 System Control Register 1 (SCR1)................................................................... 55 System Control Register 2 (SCR2)................................................................... 55 System Control Register 3 (SCR3)................................................................... 56 System Control Register 4 (SCR4)................................................................... 58 Transmit FIFO Status Register (TFSR) ............................................................ 58 Receive FIFO Status Register (RFSR)............................................................. 58 Location Control Register (LCR) ...................................................................... 59 Node Identity Register (BIR)............................................................................. 60 Net Identity Register (NIR) ............................................................................... 60 System Status Register (SSR) ......................................................................... 60 Packet Size Register (PSR) ............................................................................. 62 Carrier Sense Register (CSR) .......................................................................... 62 Control Registers List ....................................................................................... 66 BB Control Example ......................................................................................... 67 Universal Serial Bus (USB).......................................................................................69 9.1 Block Diagram.................................................................................................... 69 9.2 USB FIFO Allocation .......................................................................................... 69 9.3 Pin Description ................................................................................................... 70 9.4 Timing Diagram of MCU Interface ..................................................................... 71 9.5 USB Device Register Summary ........................................................................ 72 9.5.1 9.5.2 9.5.3 9.5.4 9.5.5 9.5.6 9.5.7 9.5.8 9.5.9 9.5.10 9.5.11 9.5.12 9.5.13 General Control Register (GCNTR).................................................................. 73 Endpoint n Control Register (EP1/2/3CNTR) ................................................... 74 Endpoint Interrupt Event Register (EPINTR).................................................... 74 Endpoint Interrupt Event Enable Register (EPINTE)........................................ 76 State Interrupt Event Register (STAINTR)........................................................ 76 State Interrupt Event Enable Register (STAINTE)............................................ 76 Function Address Register (FAR) ..................................................................... 77 Endpoint 0 RX Token Register (EP0RXTR) ..................................................... 77 Endpoint 0 RX Command/Status Register (EP0RXCSR) ................................ 77 Endpoint 0 TX Command/Status Register (EP0TXCSR) ................................. 78 Endpoint 0 RX Count Register (EP0RXCTR)................................................... 79 Endpoint0 TX Count Register (EP0TXCTR)..................................................... 79 Endpoint 0 RX Data Register (EP0RXDAR)..................................................... 80 Product Specification (V1.0) 08.20.2007 •v Contents 9.5.14 9.5.15 9.5.16 9.5.17 9.5.18 9.5.19 9.5.20 9.5.21 10 Endpoint 0 TX Data Register (EP0TXDAR) ..................................................... 80 Endpoint n Command/Status Register (EPnCSR) ........................................... 80 Endpoint n Count Register (EPnCTR).............................................................. 82 Endpoint n Data Register (EPnDAR)................................................................ 82 USB Device SOF Event Register (HINTR)....................................................... 82 USB Device SOF Event Enable Register (HINTE)........................................... 82 Frame Number Low-Byte Register (FNLR) ...................................................... 82 Frame Number High-Byte Register (FNHR)..................................................... 82 Pulse Width Modulation (PWM)................................................................................83 10.1 Overview ............................................................................................................ 83 10.2 PWM Control Registers ..................................................................................... 84 11 10.3 PWM Programming Procedures/Steps.............................................................. 85 Interrupts.....................................................................................................................86 12 11.1 Introduction ........................................................................................................ 86 Circuitry of Input and Output Pins...........................................................................88 13 12.1 Introduction ........................................................................................................ 88 Timer/Counter System ..............................................................................................88 13.1 Introduction ........................................................................................................ 88 13.2 Time Clock Counter (TCC) ................................................................................ 88 13.2.1 Block Diagram of TCC ...................................................................................... 89 13.2.2 TCC Control Registers ..................................................................................... 89 13.2.3 TCC Programming Procedures/Steps .............................................................. 90 13.3 Free Run Counter .............................................................................................. 90 13.3.1 Block Diagram of FRC...................................................................................... 90 13.3.2 FRC Control Registers ..................................................................................... 91 13.3.3 FRC Programming Procedures/Steps .............................................................. 91 14 Reset and Wake Up....................................................................................................92 14.1 Reset .................................................................................................................. 92 14.2 The Status of RST, T, and P of STATUS Register ............................................. 92 14.3 System Set-up (SSU) Time................................................................................ 92 15 14.4 Wake-up Procedure on Power-on Reset........................................................... 93 Oscillators...................................................................................................................94 15.1 Introduction ........................................................................................................ 94 15.2 Clock Signal Distribution.................................................................................... 94 16 15.3 PLL Oscillator..................................................................................................... 94 Low-Power Mode .......................................................................................................95 16.1 Introduction ........................................................................................................ 95 16.2 Green Mode ....................................................................................................... 95 16.3 Sleep Mode ........................................................................................................ 96 vi • Product Specification (V1.0) 08.20.2007 Contents 17 Instruction Description .............................................................................................96 18 16.1 Instruction Set Summary ................................................................................... 96 Electrical Specification .............................................................................................99 18.1 Absolute Maximum Ratings ............................................................................... 99 18.2 DC Electrical Characteristic ............................................................................... 99 18.3 Voltage Detector Electrical Characteristic ....................................................... 100 18.4 AC Electrical Characteristic ............................................................................. 100 18.4.1 MCU................................................................................................................ 100 18.4.2 BB ................................................................................................................... 101 19 20 Application Circuit ...................................................................................................102 Pad Description........................................................................................................103 APPENDIX A B Package Type ...........................................................................................................105 Package Information ...............................................................................................105 Product Specification (V1.0) 08.20.2007 • vii Contents Specification Revision History Doc. Version 1.0 viii • Revision Description Initial released version Date 2007/08/20 Product Specification (V1.0) 08.20.2007 EM77930 USB+BB Controller 1 General Description The EM77930 from ELAN Technology is a low-cost and high performance 8-bit CMOS advance RISC architecture microcontroller device. It has an on-chip 1-Mbps RF driver Baseband (BB), Universal Serial Bus (USB), one Pulse Width Modulation (PWM) with 16-bit resolution, an 8-bit Timer Clock Counter (TCC) and a 16-bit Free Run Timer, Key Wake-up function (KWU), Power-on Reset (POR), Watchdog Timer (WDT), and power saving Sleep Mode. All these features combine to ensure applications require the least external components, hence, not only reduce system cost, but also have the advantage of low power consumption and enhanced device reliability. The 44-pin EM77930 is available in a very cost-effective ROM version. It is also suitable for wireless base-band and USB device production. 2 Features 2.1 Core Operating Voltage Range: 2.2V ~ 3.6V DC Operating Temperature Range: 0°C ~ 70°C Operating Frequency Range: DC ~ 48MHz (1 clock/cycle) 6MHz external clock source 6/12/24/48 MHz Core & BB clock 6/48MHz internal USB clock (Low/Full speed) 12K x 16 bits of on-chip Program ROM 1216 x 8 bits of on-chip Register (SRAM) plus USB indirect addressing RAM Watchdog Timer (WDT) 16-level stacks for both CALL and interrupt subroutine Internal Power-on Reset (POR) function. All single cycle (1 clock) instruction except for conditional branches which are two or three cycles Direct, indirect and relative addressing modes Low power, high speed CMOS technology Power consumption: < 4 mA @ 3.3V, 6 MHz < 1 μA standby current Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) •1 EM77930 USB+BB Controller 2.2 Oscillators/System Clocks Three oscillator options: ● Crystal/Resonate oscillator of high frequency ● PLL oscillator: 6MHz, 12 MHz, 24 MHz, and 48 MHz (External crystal should be 6 MHz) ● Internal RC oscillator (32kHz) Three modes of system clocks: ● Sleep mode ● Green mode ● Normal mode Internal RC oscillator for Power-on Reset (POR) and Watchdog Timer (WDT) 2.3 Input and Output (I/O) Pins Max. of 30 I/O pins Pull-up resistor options Key Wake-up function Open drain output options 2.4 Timers and Counters Programmable 8-bit real Time Clock/Counter (TCC) with prescaler and overflow interrupt 16-bit Free Run Counter (FRC) with overflow interrupt 2.5 Interrupt Sources and Features Hardware priority check Different interrupt vectors Interrupts: ● Key Wake up ● External pin interrupt ● 16-bit Free Run Counter Overflow ● TCC (time-base) overflow ● One complete period of Pulse Width Modulation (PWM) ● Base band (BB) function interrupts 2• CSD: carrier sense detection Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller ● TX_AE: TX_FIFO almost full RX_AF: RX_FIFO almost full TX_ EMPTY: finish a transmitting a package RX_OF: RX_FIFO overflow LINK_DIS: zero counter capacitor discharge mechanism LOCK_OUT: finish receiving a package LOCK_IN: start receiving a package USB function interrupts: Endpoint 0 Interrupt Event: ¾ INT0RX: EP0 USB RX Event ¾ INT0TX: EP0 USB TX Event ¾ INT0IN: EP0 USB IN Token Event Endpoint X Interrupt Event: ¾ INT1: EP1 Interrupt ¾ INT2: EP2 Interrupt ¾ INT3: EP3 Interrupt Device State Interrupt Event: ¾ RSTINT: USB Bus Reset Event Detect ¾ IDLEINT: USB Bus Suspend Detect ¾ RUEINT: Enable USB Bus Resume Detect ¾ SOFINT: Start of Frame Interrupt 2.6 Baseband Serial to Parallel conversion of RFW102 interface Input FIFO (RX_FIFO) Output FIFO (TX_FIFO) Preamble Correlation Packet Address Filter (Network and unique) Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) •3 EM77930 USB+BB Controller CRC calculation Inter-RFWAVES networks Carrier-sense Discharge of RFW-102 reference capacitor Compensate for clock drifts between the transmitting EM77930 and the receiving EM77930 up to 1000ppm. Hence, the EM77930 requires low performance crystal Interrupt Driver 2.7 Universal Serial Bus (USB) USB Specification Compliance ● Conforms to USB specification, version 1.1 ● Conforms to USB Human Interface Device (HID) Specification, version 1.1. 5V supplied from PC USB interface 2.8 Pulse Width Modulation (PWM) One Pulse Width Modulation (PWM) with 16-bit resolution 2.9 Built-in Voltage Regulator Internal 3.3V regulator is used to be the power source of the MCU and the regulated output pin to provide a pull-up source for the external USB resistor on the downstream D- pin. 4• Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 3 Pin Assignment PD3 39 PD4 PF0 40 PD5 PF1 41 PD6 PF2 42 PD7 PF3 43 VDD PA0 44 38 37 36 35 34 PA1 1 33 PD2 PA2 2 32 PD1 PA3 3 31 PD0 /RST 4 30 OSCO2 PA4 5 29 OSCI PA5 6 28 VSS PA6 7 27 PLCC PA7/PWM0 8 26 PC4/INT1 VSS 9 25 PC3/INT0 D+ 10 24 RFIO/PC6 D- 11 23 TXRX/PC7 EM77930 15 16 17 18 19 20 21 PB1 PB2 PB3 PB4 PB5 PB6 PB7 22 RF_ACT 14 PB0 VDD_5V 13 VDD 12 Fig. 3 Pad and Pins Configuration of EM77930 Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) •5 EM77930 USB+BB Controller 4 Pin Description The Table below shows the corresponding relationship between the pad and pins of EM77930 Pin No. 1~3 4 PTA1~3 /RST Type Smitt Trigger Pull High /50KΩ Open Drain I/O − √ − − √ − − Reset Pins 4~7 of Port A Function Description Pins 0~3 of Port A (default) 5~8 PTA4~6 I/O − √ − 11 PWM0/PA7 I/O − √ − − − Ground Pin Pin 7 of Port A PWM0 output 9 VSS − − 10 UPRT_D+ − − − − USB upstream differential data plus 11 UPRT_D- − − − − USB upstream differential data minus 12 VDD_5V − − − − 5V Power supply for digital circuit and the embedded USB. 13 VDD − − − − I/O − √ √ O − − − BB/RF Active O − − − Transceiver modes control √ − Transceiver to/from RF modem 14~21 22 23 KWU0~7 PB0~7 RF_ACT TXRX 3.3v input. (no use regulator) 3.3v stable output. (use regulator) Pins 0~7 of Port B (default). Key Wake up 0~7 24 RFIO I/O − 25 EINT0/ PC3 I/O − √ − 26 EINT1/ PC4 I/O − √ − 27 PLLC − − − − External capacitor for PLL circuit 28 VSS − − − − Ground Pin 29 OSCI I − − − Input of crystal oscillator O − − − Selected PLL Clock Output I/O − √ − Pins 0~7 of Port D − − − − 3.3v input. PF0 ~PF3 I/O − √ − Pins 0 ~ 3 of Port F PA0 I/O − √ − Pin 0 of Port A 30 31~ 38 39 40~43 44 6• Symbol OSCO2 PD0~7 VDD External interrupt Pin 0 Pin 3 of Port C External interrupt Pin 1 Pin 4 of Port C Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 5 Block Diagram ROM MCU RAM I/O Port USB Device OSCO RF Module BB PWM PLL Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) Timer •7 EM77930 USB+BB Controller 6 Memory 6.1 Program Memory The EM77930 has a 14-bit program counter (PC). The program memory space, which is partitioned into two pages can address up to 12K. The first page has 8K and the second page has 4K in length. Fig. 6-1 depicts the profile of the program memory and stack. The initial Address is 0x0000. The table of the interrupt-vectors starts from 0x10 to 0xA8 with every other eight-address space. LPC HPC A13 A12 A11 A10 A9 A8 INT CALL A7~A0 Stack 0 RET RETL Stack 1 RETI PS0 Address Page 0 0000 ~ 1 FFF 0 1 2000 ~ 2 FFF 1 Addr Vector 0000 Reset 0010 Key Wake-up 0020 TCCOF 0028 FRCOF ACC2 SR2 RAMBS02 ROMPS2 Stack 1E ACC1 SR1 RAMBS01 ROMPS1 Stack 1F ACC0 SR0 RAMBS00 ROMPS0 Fig. 6-1 Configuration of Program Memory (ROM) for EM77930 8• Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 6.2 RAM–Register A total of 1218 accessible bytes of data memory are available for the EM77930. By function, they are classified into general purpose registers, system control / configuration registers, specification purpose registers, USB control/status registers, baseband (BB) control/status registers, timer/counter registers, and I/O port status/control registers. All of the above registers except I/O ports and their related control registers are implemented as static RAM. The RAM configurations are shown in Fig. 6-2. 00 System , Configuration, Clock , IOport Registers 30 31 General purpose registers 3F 40 80 Peripherals, and Interrupts Control registers 9A 9B Dual Port Register 7F 000 General purpose Registers Of Bank 0 FF 001 180 General purpose Registers Of Bank 1 1CB 00 00 EndPoint0 RXBuffer EndPoint1 Buffer 3F 3F 00 00 EndPoint0 TXBuffer EndPoint2 Buffer 3F 1CC USB Status Interrupts Control registers 1FF 3F 00 280 General purpose Registers Of Bank 2 100 011 010 380 General purpose Registers Of Bank 3 480 General purpose Registers Of Bank 4 101 580 General purpose Registers Of Bank 5 EndPoint3 Buffer 3F 2FF 3FF 4FF 5FF Fig. 6-2 Configuration of Data Memory (RAM) for EM77930 Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) •9 EM77930 USB+BB Controller The table is a summary of all registers except general purpose registers. Addr Name Reset Type Bit 7 Bit 6 Bit 5 IAC07 IAC06 IAC05 IAC04 IAC03 R/W R/W R/W R/W 0 0 0 0 Full Name Bit Name 0x00 IAC0 Read/Write (R/W) Power-on 10 • ROMPS R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 P P P P P Most Significant Byte of Programming Counter PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Read/Write (R/W) R R R R R R R R Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Jump to the corresponding interrupt vector or continue to execute next instruction Least Significant Byte of Programming Counter Bit Name PCF PCE PCD PCC PCB PCA PC9 PC8 Read/Write (R/W) R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Jump to the corresponding interrupt vector or continue to execute next instruction Status Register - - RST T P Z DC C Read/Write (R/W) - - R/W R/W R/W R/W R/W R/W Power-on - - 0 1 1 U U U /RESET and WDT - - P T T P P P Wake-up from Int - - P T T P P P RAM Bank Select 0 Bit Name - - - - - RBS02 RBS01 RBS00 Read/Write (R/W) - - - - - R/W R/W R/W Power-on - - - - - 0 0 0 /RESET and WDT - - - - - 0 0 0 Wake-up from Int - - - - - P P P Bit Name - - - - - - - RPS0 Read/Write (R/W) - - - - - - - R/W Power-on - - - - - - - 0 Full Name 0x05 R/W P Full Name RAMBS0 IAC00 0 Bit Name 0x04 IAC01 P Full Name SR IAC02 0 Wake-up from Int 0x03 Bit 0 P Full Name LPC Bit 1 Wake-up from Int Wake-up from Int 0x02 Bit 2 /RESET and WDT Bit Name HPC Bit 3 Indirect Addressing Register contents Full Name 0x01 Bit 4 ROM Page Select /RESET and WDT - - - - - - - 0 Wake-up from Int - - - - - - - P Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller Addr Name Reset Type Bit 7 Bit 6 Bit 5 Full Name Bit Name 0x06 IAP0 Read/Write (R/W) RAMBS1 IAP05 IAP04 IAP03 IAP02 IAP01 IAP00 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P RAM Bank Select 1 Bit Name - - - - - RBS12 RBS11 RBS10 Read/Write (R/W) - - - - - R/W R/W R/W Power-on - - - - - 0 0 0 /RESET and WDT - - - - - 0 0 0 Wake-up from Int - - - - - P P P IAP17 IAP16 IAP15 IAP14 IAP13 IAP12 IAP11 IAP10 R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Read/Write (R/W) Bit Name IAC1 Indirect Addressing Pointer 1 Indirect Addressing Contents 1 IAC17 IAC16 IAC15 IAC14 IAC13 IAC12 IAC11 IAC10 R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Read/Write (R/W) Full Name 0x0A IAPDR Indirect Address Pointer Direction Control Register Bit Name - - Read/Write (R/W) - - Power-on - - /RESET and WDT - - Wake-up from Int - - Full Name 0x0B LTBL Bit 0 IAP06 Full Name 0x09 Bit 1 Power-on Bit Name IAP1 Bit 2 IAP07 Full Name 0x08 Bit 3 Indirect Addressing Pointer 0 Full Name 0x07 Bit 4 - - IAP1_D IAP0_D IAP1_D_E IAP0_D_E - - R/W R/W R/W R/W - - 0 0 0 0 - - 0 0 0 0 - - P P P P Least Significant Byte of Table Lookup Bit Name TBL7 TBL6 TBL5 TBL4 TBL3 TBL2 TBL1 TBL0 Read/Write (R/W) R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Power-on /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 11 EM77930 USB+BB Controller Addr Name Reset Type Bit 7 Bit 6 Bit 5 Full Name Bit Name 0x06 IAP0 Read/Write (R/W) Power-on RAMBS1 IAP05 IAP04 IAP03 IAP02 IAP01 IAP00 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Bit Name - - - - - RBS12 RBS11 RBS10 Read/Write (R/W) - - - - - R/W R/W R/W Power-on - - - - - 0 0 0 /RESET and WDT - - - - - 0 0 0 Wake-up from Int - - - - - P P P RAM Bank Select 1 Indirect Addressing Pointer 1 IAP17 IAP16 IAP15 IAP14 IAP13 IAP12 IAP11 IAP10 R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Read/Write (R/W) Bit Name IAC1 Indirect Addressing Contents 1 IAC17 IAC16 IAC15 IAC14 IAC13 IAC12 IAC11 IAC10 R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Read/Write (R/W) Full Name 0x0A IAPDR Indirect Address Pointer Direction Control Register Bit Name - - - - IAP1_D Read/Write (R/W) - - - - R/W R/W R/W R/W Power-on - - - - 0 0 0 0 /RESET and WDT - - - - 0 0 0 0 Wake-up from Int - - - - P P P P Bit Name TBL7 TBL6 TBL5 TBL4 TBL3 TBL2 TBL1 TBL0 Read/Write (R/W) R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Full Name 0x0B 12 • LTBL Bit 0 IAP06 Full Name 0x09 Bit 1 /RESET and WDT Bit Name IAP1 Bit 2 IAP07 Full Name 0x08 Bit 3 Indirect Addressing Pointer 0 Full Name 0x07 Bit 4 IAP0_D IAP1_D_E IAP0_D_E Least Significant Byte of Table Lookup Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller Addr Name Reset Type Bit 7 Bit 6 Full Name 0x0C 0x0D HTBL STKPTR Bit 5 NC TBLD TBLC TBLB TBLA TBL9 TBL8 Read/Write (R/W) R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Full Name Stack Pointer Bit Name STKPT7 STKPT6 STKPT5 STKPT4 STKPT3 STKPT2 STKPT1 STKPT0 Read/Write (R/W) R R R R R R R R Power-on 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-up from Int P P P P P P P P Repeat Pointer RPTC7 RPTC6 RPTC5 RPTC4 RPTC3 RPTC2 RPTC1 RPTC0 R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Bit Name - - - - - - - - Read/Write (R/W) - - - - - - - - Power-on - - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - Read/Write (R/W) Bit Name TCC No Connection Read/Write (R/W) Time Clock/Counter TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0 R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int 0 0 0 0 0 0 0 0 Full Name 0x11 INTF Bit 0 TBLE Full Name 0x10 Bit 1 TBLF Full Name 0x0F Bit 2 Bit Name Bit Name RPTC Bit 3 Most Significant Byte of Table Lookup Full Name 0x0E Bit 4 Interrupt Flag Bit Name - - - PWM0IF EINT1F EINT0F TCCOF FRCOF Read/Write (R/W) - - - R/W R/W R/W R/W R/W Power-on - - - 0 0 0 0 0 /RESET and WDT - - - 0 0 0 0 0 Wake-up from Int - - - P P P P P Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 13 EM77930 USB+BB Controller Addr Name Reset Type Bit 7 Bit 6 Full Name Bit Name 0x12 0x13 KWUAIF KWUBIF PA - - PB 14 • PD Bit 0 - - KWU3IF KWU2IF KWU1IF KWU0IF - - - - R/W R/W R/W R/W - - - 0 0 0 0 /RESET and WDT - - - - 0 0 0 0 Wake-up from Int - - - - 0 0 0 0 Full Name Port B Key Wake-up Interrupt Flag Bit Name KWU7IF KWU6IF KWU5IF KWU4IF KWU3IF KWU2IF KWU1IF KWU0IF Read/Write (R/W) R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int 0 0 0 0 0 0 0 0 General Purpose I/O port, Port A Bit Name PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Read/Write (R/W) R/W R/W R/W R/W R/W R/W R/W R/W Power-on U U U U U U U U /RESET and WDT U U U U U U U U Wake-up from Int P P P P P P P P Bit Name PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Read/Write (R/W) R/W R/W R/W R/W R/W R/W R/W R/W Power-on U U U U U U U U /RESET and WDT U U U U U U U U Wake-up from Int P P P P P P P P - - General Purpose I/O port, Port B General Purpose I/O port, Port C - - - PTC4 PTC3 - Read/Write (R/W) - - - R/W R/W - - - Power-on - - - U U - - - /RESET and WDT - - - U U - - - Wake-up from Int - - - P P - - - Full Name 0x17 Bit 1 - Bit Name PC Bit 2 Power-on Full Name 0x16 Bit 3 Read/Write (R/W) Full Name 0x15 Bit 4 Port A Key Wake-up Interrupt Flag Full Name 0x14 Bit 5 General Purpose I/O port, Port D Bit Name PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Read/Write (R/W) R/W R/W R/W R/W R/W R/W R/W R/W Power-on U U U U U U U U /RESET and WDT U U U U U U U U Wake-up from Int P P P P P P P P Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller Addr Name Reset Type Bit 7 Bit 6 Bit 5 Full Name 0x18 NC PF - - - - - - Read/Write (R/W) - - - - - - - - Power-on - - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - General Purpose I/O port, Port F Bit Name - - - - PTF3 PTF2 PTF1 PTF0 Read/Write (R/W) - - - - R/W R/W R/W R/W Power-on - - - - U U U U /RESET and WDT - - - - U U U U Wake-up from Int - - - - P P P P Least Significant Byte of the 16-bit Free Run Counter FRC7 FRC6 FRC5 FRC4 FRC3 FRC2 FRC1 FRC0 Read/Write (R/W) R R R R R R R R Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int 0 0 0 0 0 0 0 0 Bit Name HFRC Most Significant Byte of 16-bit Free Run Counter FRCF FRCE FRCD FRCC FRCB FRCA FRC9 FRC8 R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int 0 0 0 0 0 0 0 0 Read/Write (R/W) Full Name Bit Name 0x1C LFRCB Least Significant Byte Buffer of the 16-bit Free Run Counter FRCB7 FRCB6 FRCB5 FRCB4 FRCB3 FRCB2 FRCB1 FRCB0 R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int 0 0 0 0 0 0 0 0 Bit Name - - - - - - - - Read/Write (R/W) - - - - - - - - Power-on - - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - Read/Write (R/W) Full Name 0x1D NC Bit 0 - Full Name 0x1B Bit 1 - Bit Name LFRC Bit 2 Bit Name Full Name 0x1A Bit 3 No Connection Full Name 0x19 Bit 4 No Connection Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 15 EM77930 USB+BB Controller Addr Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Full Name 0x1E NC NC - - - - - - - - - - - - - - - - Power-on - - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - - - - No Connection - - - - - - - - - - - - Power-on - - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - LSB Converting Value of ADC Bit Name - - - - - - - - Read/Write (R/W) - - - - - - - - Power-on - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - Bit Name DT0L Duty of PWM-Low Byte DT07 DT06 DT05 DT04 DT03 DT02 DT01 DT00 Read/Write (R/W) R R R R R R R R Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Full Name Bit Name 0x22 DT0H Duty of PWM-High Byte DT0F DT0E DT0D DT0C DT0B DT0A DT09 DT08 Read/Write (R/W) R R R R R R R R Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Full Name Bit Name 0x23 16 • PRD0L - Read/Write (R/W) Full Name 0x21 Bit 0 Read/Write (R/W) Full Name 0x20 Bit 1 Bit Name Bit Name NC Bit 2 No Connection Full Name 0x1F Bit 3 Read/Write (R/W) Period of PWM - Low Byte PRD07 PRD06 PRD05 PRD04 PRD03 PRD02 PRD01 PRD00 R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller Addr Name Reset Type Bit 7 Bit 6 Bit 5 Full Name Bit Name 0x24 PRD0H DL0L DL0H NC NC PRD0D PRD0C PRD0B PRD0A PRD09 PRD08 R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Duty Latch of PWM-Low Byte Bit Name DL07 DL06 DL05 DL04 DL03 DL02 DL01 DL00 Read/Write (R/W) R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Duty Latch of PWM-High Byte Bit Name DL0F DL0E DL0D DL0C DL0B DL0A DL019 DL08 Read/Write (R/W) R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P No Connection Bit Name - - - - - - - - Read/Write (R/W) - - - - - - - - Power-on - - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - No Connection Bit Name - - - - - - - - Read/Write (R/W) - - - - - - - - Power-on - - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - - - - Full Name Bit Name 0x29 NC Bit 0 PRD0E Full Name 0x28 Bit 1 R/W Full Name 0x27 Bit 2 PRD0F Read/Write (R/W) Full Name 0x26 Bit 3 Period of PWM- High Byte Full Name 0x25 Bit 4 No Connection - - - - - Read/Write (R/W) - - - - - - - - Power-on - - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 17 EM77930 USB+BB Controller Addr Name Reset Type Bit 7 Bit 6 Bit 5 Full Name 0x2A NC NC RFAAR - - - - - - - - - - - - - - - Power-on - - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - - - - No Connection - - - - - - - - - - - - - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - No Connection Bit Name - - - - - - - - Read/Write (R/W) - - - - - - - - Power-on - - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - BB Address Register Bit Name - - - AAR4 AAR3 AAAR2 AAR1 AAR0 Read/Write (R/W) - - - R/W R/W R/W R/W R/W Power-on - - - 0 0 0 0 0 /RESET and WDT - - - 0 0 0 0 0 Wake-up from Int - - - P P P P P BB Data Buffer RFDB7 RFDB6 RFDB5 RFDB4 RFDB3 RFDB2 RFDB1 RFDB0 R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Read/Write (R/W) Full Name Bit Name 0x2F 18 • RFACR - Power-on Bit Name RFDB - Read/Write (R/W) Full Name 0x2E Bit 0 - Full Name 0x2D Bit 1 Read/Write (R/W) Full Name 0x2C Bit 2 Bit Name Bit Name NC Bit 3 No Connection Full Name 0x2B Bit 4 BB Data Read/Write Control Register - - - - - RRST RFRD RFWR Read/Write (R/W) - - - - - R/W R/W R/W Power-on - - - - - 0 1 1 /RESET and WDT - - - - - 0 1 1 Wake-up from Int - - - - - P P P Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller Addr Name Reset Type Bit 7 Bit 6 Bit 5 Full Name Bit Name 0x30 RFINTF Read/Write (R/W) DPR 0x7F CSDF PRIE INTE R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Read/Write (R/W) Dual Port Registers (64 in total) DPR7 DPR6 DPR5 DPR4 DPR3 DPR2 DPR1 DPR0 R/W R/W R/W R/W R/W R/W R/W R/W Power-on X X X X X X X X /RESET and WDT X X X X X X X X Wake-up from Int P P P P P P P P Peripheral Function Enable Bit Name - USBE WME - - PWME TCCE FRCE Read/Write (R/W) - R/W R/W - - R/W R/W R/W Power-on - 0 0 - - 0 0 0 /RESET and WDT - 0 0 - - 0 0 0 Wake-up from Int - P P - - P P P Interrupt Enable Control Register Bit Name GIE - - PWM0IE EINT1E EINT0E TCCOE FRCOE Read/Write (R/W) R/W - - R/W R/W R/W R/W R/W Power-on 0 - - 0 0 0 0 0 /RESET and WDT 0 - - 0 0 0 0 0 Wake-up from Int P - - P P P P P Full Name 0x82 NC No Connection Bit Name - - - - - - - - Read/Write (R/W) - - - - - - - - Power-on - - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - - - - Full Name Bit Name 0x83 NC Bit 0 R/W Full Name 0x81 Bit 1 TX_AEF RX_AFF TX_EMPTYF RX_OFF LINK_ DISF LOCK_OUTF LOCK_ INF Full Name 0x80 Bit 2 R/W Bit Name ~ Bit 3 BB Interrupt Flag Register Full Name 0x40 Bit 4 No Connection - - - - - Read/Write (R/W) - - - - - - - - Power-on - - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 19 EM77930 USB+BB Controller Addr Name Reset Type Bit 7 Bit 6 Full Name Bit Name 0x84 EINTED Bit 5 SYNB0 - - - R/W R/W - - - R/W R/W Power-on 0 0 0 - - - 0 0 /RESET and WDT 0 0 0 - - - 0 0 Wake-up from Int P P P - - - P P - - - - - - IOCC - - - - - - - - - - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - I/O Control of Port A IOCA7 IOCA6 IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 R/W R/W R/W R/W R/W R/W R/W R/W Power-on 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-up from Int P P P P P P P P Read/Write (R/W) I/O Control of Port B IOCB7 IOCB5 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 R/W R/W R/W R/W R/W R/W R/W R/W Power-on 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-up from Int P P P P P P P P Read/Write (R/W) I/O Control of Port C Bit Name - - - IOCC4 IOCC3 - - - Read/Write (R/W) - - - R/W R/W - - - Power-on - - - 1 1 - - - /RESET and WDT - - - 1 1 - - - Wake-up from Int - - - P P - - - Full Name Bit Name 0x89 20 • IOCD - Power-on Full Name 0x88 - Read/Write (R/W) Bit Name IOCB EINT1ED EINT0ED No Connection Full Name 0x87 Bit 0 SYNB1 Bit Name IOCA Bit 1 R/W Full Name 0x86 Bit 2 SYNB2 Read/Write (R/W) Bit Name SPIC Bit 3 External Interrupt Edge Control Full Name 0x85 Bit 4 I/O Control of Port D IOCD7 IOCD6 IOCD5 IOCD4 IOCD3 IOCD2 IOCD1 IOCD0 R/W R/W R/W R/W R/W R/W R/W R/W Power-on 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-up from Int P P P P P P P P Read/Write (R/W) Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller Addr Name Reset Type Bit 7 Bit 6 Bit 5 Full Name 0x8A NC IOCF - - - - - - Read/Write (R/W) - - - - - - - - Power-on - - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - I/O Control of Port F Bit Name - - - - IOCF3 IOCF2 IOCF1 IOCF0 Read/Write (R/W) - - - - R/W R/W R/W R/W Power-on - - - - 1 1 1 1 /RESET and WDT - - - - 1 1 1 1 Wake-up from Int - - - - P P P P Read/Write (R/W) Pull-up control of Port A PUCA7 PUCA6 PUCA5 PUCA4 PUCA3 PUCA2 PUCA1 PUCA0 R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Bit Name PUCB Pull-up control of Port B PUCB7 PUCB6 PUCB5 PUCB4 PUCB3 PUCB2 PUCB1 PUCB0 R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Read/Write (R/W) Full Name 0x8E PUCC Pull-up control of Port C Bit Name - - - PUCC4 PUCC3 Read/Write (R/W) - - - R/W R/W Power-on - - - 0 0 /RESET and WDT - - - 0 0 Wake-up from Int - - - P P PUCD7 PUCD6 PUCD5 PUCD4 PUCD3 PUCD2 PUCD1 PUCD0 R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Full Name Bit Name 0x8F PUCD Bit 0 - Full Name 0x8D Bit 1 - Bit Name PUCA Bit 2 Bit Name Full Name 0x8C Bit 3 No Connection Full Name 0x8B Bit 4 Read/Write (R/W) Pull-up control of Port D Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 21 EM77930 USB+BB Controller Addr Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Full Name 0x90 NC PUCF - - - - - - - Read/Write (R/W) - - - - - - - - Power-on - - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - Pull-up Control of Port F Bit Name - - - - PUCF3 PUCF2 PUCF1 PUCF0 Read/Write (R/W) - - - - R/W R/W R/W R/W Power-on - - - - 0 0 0 0 /RESET and WDT - - - - 0 0 0 0 Wake-up from Int - - - - P P P P Open Drain Control of Port B OPCB7 OPCB6 OPCB5 OPCB4 OPCB3 OPCB2 OPCB1 OPCB0 R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P 0 0 0 Read/Write (R/W) Full Name Bit Name 0x93 TCCC Time Clock/Counter Control - - FRCC - 22 • PS2 PS1 PS0 - - - - R/W R/W R/W R/W - - - - 0 0 0 0 /RESET and WDT - - - - 0 0 0 0 Wake-up from Int - - - - P P P P Free Run Counter Control/OSCO2 Output Control OSCO2 OSCO2 SL1 SL0 R/W R/W R/W R/W R/W R/W R/W - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - P P P P P P P Bit Name - OSC02E Read/Write (R/W) - Power-on /RESET and WDT Wake-up from Int Bit Name WDTC TCCS0 Power-on Full Name 0x95 - Read/Write (R/W) Full Name 0x94 Bit 0 - Bit Name ODCB Bit 1 Bit Name Full Name 0x92 Bit 2 No Connection Full Name 0x91 Bit 3 Read/Write (R/W) Power-on PPSCL2 PPSCL1 PPSCL0 FRCCS Watchdog Timer Control GREEN - - WDTCE - RAT2 RAT1 RAT0 R/W - - R/W - R/W R/W R/W 0 - - 0 - 0 0 0 /RESET and WDT 0 - - 0 - 0 0 0 Wake-up from Int 0 - - P - P P P Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller Addr Name Reset Type Bit 7 Bit 6 Bit 5 Full Name 0x96 NC NC PWMCR Bit 0 - - - - - - - Read/Write (R/W) - - - - - - - - Power-on - - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - No Connection Bit Name - - - - - - Read/Write (R/W) - - - - - - Power-on - - - - - - /RESET and WDT - - - - - - Wake-up from Int - - - - - - PWM Control Register Bit Name - - - - - S_PWM0 - - Read/Write (R/W) - - - - - R/W - - Power-on - - - - - 0 - - /RESET and WDT - - - - - 0 - - Wake-up from Int - - - - - P - - Bit Name RFINTE Bit 1 - Full Name 0x99 Bit 2 Bit Name Full Name 0x98 Bit 3 No Connection Full Name 0x97 Bit 4 Read/Write (R/W) BB Interrupt Enable Control Register CSDE TX_AEE RX_AFE TX_ EMPTYE RX_OFE LINK_ DISE LOCK_OUTE LOCK_ INE R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Reserved 0x1CC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PLUG URST Full Name 0x1CD GCNTR USB General Control Register Bit Name - - - - Read/Write (R/W) - - - - R/W R/W R/W R/W Power-on - - - - 0 0 0 0 /RESET and WDT - - - - 0 0 0 0 Wake-up from Int - - - - P P P P Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) RESUME SUSPEND • 23 EM77930 USB+BB Controller Addr Name Reset Type Bit 7 Bit 6 Bit 5 Full Name 0x1CE EP1CNTR Bit Name - - EP1EN Read/Write (R/W) - - R/W Power-on - - 0 - - - EP1DIR EP1TP1 EP1TP0 R/W R/W R/W 1 0 0 - 0 - - 1 0 0 - P - - P P P End Point 2 Control Register Bit Name - - EP2EN - - EP2DIR EP2TP1 EP2TP0 Read/Write (R/W) - - R/W - - R/W R/W R/W Power-on - - 0 - - 1 0 0 /RESET and WDT - - 0 - - 1 0 0 Wake-up from Int - - P - - P P P End Point 3 Control Register Bit Name - - EP3EN - - EP3DIR EP3TP1 EP3TP0 Read/Write (R/W) - - R/W - - R/W R/W R/W Power-on - - 0 - - 1 0 0 /RESET and WDT - - 0 - - 1 0 0 Wake-up from Int - - P - - P P P Endpoint Interrupt Event Status Register - - INT3 INT2 INT1 INT0IN INT0TX INT0RX Read/Write (R/W) - - R/W R/W R/W R/W R/W R Power-on - - 0 0 0 1 0 0 /RESET and WDT - - 0 0 0 1 0 0 Wake-up from Int - - P P P P P P Endpoint Interrupt Event Enable Control Register Bit Name - - INT3E INT2E INT1E Read/Write (R/W) - - R/W R/W R/W R/W R/W R/W Power-on - - 0 0 0 0 0 0 INT0INE INT0TXE INT0RXE /RESET and WDT - - 0 0 0 0 0 0 Wake-up from Int - - P P P P P P Full Name 24 • - - Full Name 0x1D3 STAINTR Bit 0 - Bit Name 0x1D2 EPINTE Bit 1 Wake-up from Int Full Name 0x1D1 EPINTR Bit 2 /RESET and WDT Full Name 0x1D0 EP3CNTR Bit 3 End Point 1 Control Register Full Name 0x1CF EP2CNTR Bit 4 State Interrupt Event Flag Register Bit Name - - - - FRWPINT RUEINT IDLEINT RSTINT Read/Write (R/W) - - - - R/W R/W R/W R/W Power-on - - - - 0 0 0 0 /RESET and WDT - - - - 0 0 0 0 Wake-up from Int - - - - P P P P Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller Addr Name Reset Type Bit 7 Bit 6 Full Name 0x1D4 STAINTE Bit 5 0x1D7 EP0RXCSR Bit 0 - - - Read/Write (R/W) - - - - R/W R/W R/W R/W Power-on - - - - 0 0 0 0 FRWPINTE RUEINTE IDLEINTE RSTINTE /RESET and WDT - - - - 0 0 0 0 Wake-up from Int - - - - P P P P Function Address Bit Name - Read/Write (R/W) - R/W R/W R/W R/W R/W R/W R/W Power-on - 0 0 0 0 0 0 0 /RESET and WDT - 0 0 0 0 0 0 0 Wake-up from Int - P P P P P P P FADDR6 FADDR5 FADDR4 FADDR3 FADDR2 FADDR1 FADDR0 Endpoint 0 RX Token Bit Name - - - - - Read/Write (R/W) - - - - - R/W R/W R/W Power-on - - - - - 0 0 0 /RESET and WDT - - - - - 0 0 0 Wake-up from Int - - - - - P P P USETUPOW USETUP UOUT Full Name Endpoint 0 RX Command/Status Bit Name CDTOG0RX ERRSTS0RX STALLSTS0RX ACKSTS0RX DTOGERR0RX DTOG0RX SESTALL0RX RXEN0RX Read/Write (R/W) W R R R R R R/W R/W Power-on 0 0 0 0 0 0 1 1 /RESET and WDT 0 0 0 0 0 0 1 1 Wake-up from Int P P P P P P P P Bit Name 0x1D9 EP1CSR Bit 1 - Full Name 0x1D8 EP0TXCSR Bit 2 Bit Name Full Name 0x1D6 EP0RXTR Bit 3 State Interrupt Event Enable Control Register Full Name 0x1D5 FAR Bit 4 Endpoint 0 TX Command/Status CDTOG0TX ERRSTS0TX STALLSTS0TX ACKSTS0TX - DTOG0TX SESTALL0TX TXEN0TX Read/Write (R/W) W R R R - R R/W R/W Power-on 0 0 0 0 - 1 1 0 /RESET and WDT 0 0 0 0 - 1 1 0 Wake-up from Int P P P P - P P P Full Name Endpoint 1 Command/Status Bit Name CDTOG1 ERRSTS1 STALLSTS1 ACKSTS1 DTOGERR1 DTOG1 SESTALL1 RXTXEN1 Read/Write (R/W) W R R R R R R/W R/W Power-on 0 0 0 0 0 0 1 0 /RESET and WDT 0 0 0 0 0 0 1 0 Wake-up from Int P P P P P P P P Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 25 EM77930 USB+BB Controller Addr Name Reset Type Bit 7 Bit 6 Bit 5 Full Name Bit Name 0x1DA EP2CSR CDTOG2 ERRSTS2 STALLSTS2 ACKSTS2 DTOGERR2 DTOG2 EP0RXCTR EP0TXCTR EP1CTR R R R R/W R/W Power-on 0 0 0 0 0 0 1 0 /RESET and WDT 0 0 0 0 0 0 1 0 Wake-up from Int P P P P P P P P Endpoint 3 Command/Status CDTOG3 ERRSTS3 STALLSTS3 ACKSTS3 DTOGERR3 DTOG3 26 • SESTALL3 RXTXEN3 Read/Write (R/W) W R R R R R R/W R/W Power-on 0 0 0 0 0 0 1 0 /RESET and WDT 0 0 0 0 0 0 1 0 Wake-up from Int P P P P P P P P Endpoint 0 RX Count Bit Name - EP0RXCT6 EP0RXCT5 EP0RXCT4 EP0RXCT3 EP0RXCT2 EP0RXCT1 EP0RXCT0 Read/Write (R/W) - R R R R R R R Power-on - 0 0 0 0 0 0 0 /RESET and WDT - 0 0 0 0 0 0 0 Wake-up from Int - P P P P P P P Endpoint 0 TX Count Bit Name - EP0TXCT6 EP0TXCT5 EP0TXCT4 EP0TXCT3 EP0TXCT2 EP0TXCT1 EP0TXCT0 Read/Write (R/W) - R R R R/W R/W R/W R/W Power-on - 0 0 0 0 0 0 0 /RESET and WDT - 0 0 0 0 0 0 0 Wake-up from Int - P P P P P P P Endpoint 1 Count Bit Name - EP1CT6 EP1CT5 EP1CT4 EP1CT3 EP1CT2 EP1CT1 EP1CT0 Read/Write (R/W) - R/W R/W R/W R/W R/W R/W R/W Power-on - 0 0 0 0 0 0 0 /RESET and WDT - 0 0 0 0 0 0 0 Wake-up from Int - P P P P P P P Full Name 0x1DF EP2CTR SESTALL2 RXTXEN2 R Full Name 0x1DE Bit 0 R Full Name 0x1DD Bit 1 W Full Name 0x1DC Bit 2 Read/Write (R/W) Bit Name EP3CSR Bit 3 Endpoint 2 Command/Status Full Name 0x1DB Bit 4 Endpoint 2 Count Bit Name - Read/Write (R/W) - EP2CT6 EP2CT5 EP2CT4 EP2CT3 R/W R/W R/W R/W EPCT2 R/W EP2CT1 EP2CT0 R/W R/W Power-on - 0 0 0 0 0 0 0 /RESET and WDT - 0 0 0 0 0 0 0 Wake-up from Int - P P P P P P P Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller Addr Name Reset Type Bit 7 Bit 6 Bit 5 Full Name 0x1E0 EP3CTR 0x1E1 Bit 3 Bit 2 Bit 1 Bit 0 Endpoint 3 Count Bit Name - EP3CT6 EP3CT5 EP3CT4 EP3CT3 EP3CT2 EP3CT1 EP3CT0 Read/Write (R/W) - R/W R/W R/W R/W R/W R/W R/W Power-on - 0 0 0 0 0 0 0 /RESET and WDT - 0 0 0 0 0 0 0 Wake-up from Int - P P P P P P P Full Name Endpoint 0 RX Data Bit Name EP0RX7 EP0RX6 EP0RX5 EP0RX4 EP0RX3 EP0RX2 EP0RX1 EP0RX0 EP0RXD Read/Write (R/W) AR Power-on R R R R R R R R 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Full Name Bit Name 0x1E2 Bit 4 EP0TXD AR Endpoint 0 TX Data EP0TX7 EP0TX6 EP0TX5 EP0TX4 EP0TX3 EP0TX2 EP0TX1 EP0TX0 Read/Write (R/W) W W W W W W W W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Full Name Bit Name 0x1E3 EP1DAR Read/Write (R/W) Endpoint 1 Data EP1D7 EP1D6 EP1D5 EP1D4 EP1D3 EP1D2 EP1D1 EP1D0 R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Full Name Bit Name 0x1E4 EP2DAR Read/Write (R/W) Power-on Endpoint 2 Data EP2D7 EP2D6 EP2D5 EP2D4 EP2D3 EP2D2 EP2D1 EP2D0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Full Name Bit Name 0x1E5 EP3DAR Endpoint 3 Data EP3D7 EP3D6 EP3D5 EP3D4 EP3D3 EP3D2 EP3D1 EP3D0 R/W R/W R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Read/Write (R/W) Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 27 EM77930 USB+BB Controller Addr Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Full Name 0x1E6 HGSR - - - - - - - Read/Write (R/W) - - - - - - - - Power-on - - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - Hub Interrupt Event Flag Register Bit Name - SOFINT - - - - - - Read/Write (R/W) - R/W - - - - - - Power-on - 0 - - - - - - /RESET and WDT - 0 - - - - - - Wake-up from Int - P - - - - - - Hub Interrupt Event Enable Control Register Bit Name - SOFINTE - - - - - - Read/Write (R/W) - R/W - - - - - - Power-on - 0 - - - - - - /RESET and WDT - 0 - - - - - - Wake-up from Int - P - - - - - - - - - - Bit Name Reserved - - - - - - - - - - - - - - - - - - /RESET and WDT - - - - - - - - Wake-up from Int - - - - - - - - Least Significant Byte of the Frame Number FN7 FN6 FN5 FN4 FN3 FN2 FN1 FN0 Read/Write (R/W) R R R R R R R R Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Int P P P P P P P P Full Name 28 • - Power-on Bit Name 0x1FF FNHR - Read/Write (R/W) Full Name 0x1FE FNLR Bit 0 - Full Name 0x1E9 ~ 0x1FD Bit 1 Bit Name Full Name 0x1E8 HINTE Bit 2 Reserved Full Name 0x1E7 HINTR Bit 3 Most Significant Byte of the Frame Number Bit Name - - - - - FNA FN9 FN8 Read/Write (R/W) - - - - - R R R Power-on - - - - - 0 0 0 /RESET and WDT - - - - - 0 0 0 Wake-up from Int - - - - - P P P Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 7 Function Description 7.1 Special Purpose Registers The special purpose registers are function-oriented registers used by the CPU to access memory, record execution results, and carry out the desired operation. The functions of the registers related to the core are described in the following subsections 7.1.1 Accumulator – ACC Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator, which is not an addressable register. 7.1.2 Indirect Addressing Contents – IAC0 (0x00) and IAC1 (0x09) The contents of R0 and R9 are implemented as indirect addressing pointers if any instruction uses R6 and R8 as registers. 7.1.3 Program Counter HPC (0x01) and LPC (0x02) The Program Counter (PC) is composed of registers HPC and LPC. The PC and the hardware stacks are 14 bits wide. The structure is depicted in Fig. 6-1. Generates 12K × 16 on-chip ROM addresses to the corresponding program memory (ROM). All the bits of PC are set to "0"s as a reset condition occurs. "RET" ("RETL k", "RETI") instruction loads the program counter with the contents at the top of the stack. "MOV R2, A" allows the loading of an address from the "A" register to the lower 8 bits of the PC, and the high byte (A8~A14) of the PC remain unchanged. "ADD R2, A" & "TBL" allows a corresponding address / offset to be added to the current PC. 7.1.4 Status Register –SR (0x03) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - RST T P Z DC C Bit 0 (C): Carry flag. This bit indicates that a carry out of ALU occurred during the last arithmetic operation. This bit is also affected during bit test, branch instruction and during bit shifts. Bit 1 (DC): Auxiliary carry flag. This bit is set during ADD and ADC operations to indicate that a carry occurred between Bit 3 and Bit 4. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 29 EM77930 USB+BB Controller Bit 2 (Z): Zero flag. Set to "1" if the result of the last arithmetic, data or logic operation is zero. Bit 3 (P): Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 4 (T): Time-out bit. Set to 1 by the "SLEP" command and the "WDTC" command, or during power up and reset to 0 by WDT timeout. Bit 5 (RST): Set if the CPU wakes up by keying on the wake-up pins. Reset if the chip wakes up through other ways. Bits 6 and 7 are reserved. 7.1.5 RAM Bank Selector – RAMBS0 (0x04) and RAMBS1 (0x07) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - RAMBSX2 RAMBSX1 RAMBSX0 As depicted in Fig. 6-2, there are six available banks in the MCU. Each of them has 128 registers and can be accessed by defining the bits, RAMBSX0 ~ RAMBSX2, as shown below. RAMBSX (0x04/0x07) Bank 000 0 001 1 010 2 011 3 100 4 101 5 7.1.6 ROM Page Selector – ROMPS (0x05) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - - - RPS0 As depicted in Fig. 6-1, there are two available pages in MCU. The first page has 8K*16 ROM size and the second page has 4K×16 ROM size. Both of them can be accessed by defining the bits, RPS0, as shown below. RPS0 Page (Address) 0 0 (0x0000~0x1FFF) 1 1 (0x2000~0x2FFF) 7.1.7 Indirect Addressing Pointers – IAP0 (0x06), and IAP1 (0x08) Both R6 and R8 are not physically implemented registers. They are useful as indirect addressing pointers. Any instruction using R6/R4 and R8/R7 as registers actually access data pointed by R0 and R9 individually. 30 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 7.1.8 Indirect Address Pointer Direction Control Register – IAPDR (0x0A) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 - - - - IAP1_D Bit 2 Bit 1 Bit 0 IAP0_D IAP1_D_E IAP0_D_E Bit 0/1 (IAP0_D_E/IAP1_D_E) Indirect addressing Pointer 0/1 direction function enable bit. 0: Disable 1: Enable Bit 2/3 (IAP0_D/IAP1_D) Indirect addressing pointer0/1 direction control bit. 0: Minus direction 1: Plus direction 7.1.9 Table Look-up Pointers – LTBL (0x0B), and HTBL (0x0C) The maximum length of a table is 64K, and can be accessed through registers LTBL and HTBL. HTBL is the high byte of the pointer, whereas LTBL is the low byte. 7.1.10 Stack Pointer – STKPTR (0x0D) Register RD indicates how many stacks the current free run program uses. It is a read only register. 7.1.11 Repeat Counter – RPTC (0x0E) The RE register is used to set how many times the “RPT” instruction is going to read the table. 7.1.12 Real Time Clock Counter – RTCC (0x10) TCC counter. 7.1.13 Interrupt Flag Register – INTF (0x11) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - PWM0IF EINT1F EINT0F TCCOF FRCOF Bit 0 (FRCOF): FRC Overflow interrupt. Set as the contents of the FRC counter change from 0xFFFF to 0x0000, reset by software. Bit 1 (TCCOF): TCC Overflow interrupt. Set as the contents of the TCC counter change from 0xFF to 0x00, reset by software. Bits 2 ~ 3 (EINT0F & EINTIF): External input pin interrupt flag. Interrupt occurs at the defined edge of the external input pin, reset by software. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 31 EM77930 USB+BB Controller Bit 4 (PWM0IF): PWM interrupt flag. Interrupt occurs when TMRX is equal to PRDX, reset by software. Bits 5 ~ 7 reserved Each bit can function independently regardless whether its related interrupt mask bit is enabled or not. Each bit can function independently no matter its related interrupt mask bit is enabled or not. 7.1.14 Key Wake-up Flag Register – KWUAIF (0x12) and KWUBIF (0x13) KWUAIF: Port A Key Wake-up Interrupt Flag Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - KWUBIF KWUAIF KWU9IF KWU8IF KWUBIF: Port B Key Wake-up Interrupt Flag Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 KWU7IF KWU6IF KWU5IF KWU4IF KWU3IF KWU2IF KWU1IF KWU0IF 7.1.15 I/O Port Registers – PTA ~ PTF (0x14 ~ 0x19) PTX can be operated as any other general purpose registers by related instructions. That is, PTX is an 8-bit, bi-directional, general purpose port. Its corresponding IO control bit determines the data direction of a PTX pin. 7.1.16 16-bit Free Run Counter (FRC) – LFRC (0x1A) HFRC (0x1B) and LFRCB (0x1C) R1A is a 16-bit FRC low byte; R1B is high byte; R1C is a low byte buffer. 7.1.17 PWM Duty – DT0L (0x21)/DT0H (0x22) R22:R21 16-bit PWM0 output duty cycle. 7.1.18 PWM Period – PRD0L (0x23)/PRD0H (0x24) R24:R23 16-bit PWM output period cycle. 7.1.19 PWM Duty Latch – DL0L (0x25)/DL0H (0x26) R26:R25 16-bit PWM output duty cycle buffer. 7.1.20 BB Address Register – RFAAR (0x2D) Register R2D indicates BB indirect RAM address. 7.1.21 BB Data Buffer Register – RFDB (0x2E) Register R2E indicates BB indirect RAM data. 32 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 7.1.22 BB Data Read/Write Control Register – RFACR (0x2F) Register R2F indicates WM RAM access control. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - RRST RFRD RFWR Bit 0 (RFWR): Write BB register Bit 1 (RFRD): Read BB register Bit 2 (RRST): BB S/W reset Bit 3~Bit 7: reserved 7.1.23 BB Interrupt Flag Register – RFINTF (0x30) Bit 7 Bit 6 Bit 5 CSDF TX_AEF Bit 4 Bit 3 Bit 2 RX_AFF TX_ EMPTYF RX_OFF LINK_ DISF Bit 0 (LOCK_INF): Bit 1 Bit 0 LOCK_OUTF LOCK_ INF This bit reflects the LOCK IN flag interrupt. Bit 1 (LOCK_OUTF): This bit reflects the LOCK OUT flag interrupt. Bit 2 (LINK_DISF): This interrupt is invoked by the zero counter capacitor discharge mechanism. This bit reflects the RX FIFO full flag interrupt. Bit 3 (RX_OFF): Bit 4 (TX_EMPTYF): This bit reflects the TX EMPTY flag interrupt. Bit 5 (RX_AFF): This bit reflects the RX FIFO almost full flag interrupt. Bit 6 (TX_AEF): This bit reflects the TX FIFO almost empty flag interrupt. Bit 7 (CSDF): This flag indicates that a carrier-sense interrupt has occurred. 7.2 Dual Port Register (0x40 ~ 0x7F) R 40 ~ R7F are dual port register. 7.3 System Status, Control and Configuration Registers These registers are function-oriented registers used by the CPU to record, enable or disable the peripheral modules, interrupts, and the operation clock modes. 7.3.1 Peripherals Enable Control – PRIE (0x80) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - USBE BBE - - PWM0E TCCE FRCE Bit 0 (FRCE): Free Run Counter 0 (FRC0) Enable bit Bit 1 (TCCE): Timer Clock/Counter (TCC) Enable bit Bit 2 (PWM0E): PWM0 function enable bit Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 33 EM77930 USB+BB Controller Bit 5 (BBE): Base band (BB) Enable bit Bit 6 (USBE): Universal Serial Bus (USB) Enable bit Bits 3, 4, 7: Reserved 0: disable function 1: enable function 7.3.2 Interrupts Enable Control – INTE (0x81) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE - - PWM0IE EINT1E EINT0E TCCOE FRCOE Bit 0 (FRC0OE): Free Run Counter (FRC) Overflow interrupt enable bit. Bit 1 (TCCOE): TCC (TCC) Overflow interrupt enable bit. Bit 2 (EINT0E): External pin (EINT0) interrupt enable bit. Bit 3 (EINT1E): External pin (EINT1) interrupt enable bit. Bit 4 (PWM0IE): PWM0 period complete enable bit. Bits 5, 6: Reserved 0: disable function interrupt 1: enable function interrupt Global interrupt control bit. Global interrupt is enabled by the ENI Bit 7 (GIE): and RETI instructions and is disabled by the DISI instruction. 0: Global interrupt disable 1: Global interrupt enable 7.3.3 Key Wake-up Enable Control – KWUAIE (0x82) and KWUBIE (0x83) KWUAIE: Port A Key Wake-up Interrupt Enable Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - KWUBE KWUAE KWU9E KWU8E Bit 0 ~Bit 3 (KWU8E ~ KWUBE): Enable or disable the PTA0 ~ PTA3 Key Wake-up function. 0: disable key wake-up function 1: enable key wake-up function KWUBIE: Port B Key Wake-up Interrupt Enable Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 KWU7E KWU6E KWU5E KWU4E KWU3E KWU2E KWU1E KWU0E Bit 0 ~Bit 7 (KWU0 ~ KWU7): Enable or disable the PTB0 ~ PTB7 Key Wake-up function. 0: disable key wake-up function 1: enable key wake-up function 34 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 7.3.4 Bit 7 External Interrupts Edge Control – EINTED (0x84) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EINT1ED EINT0ED Bit 0 (EINT0ED): Define which edge as an interrupt source for EINT0. Bit 1 (EINT1ED): Define which edge as an interrupt source for EINT1. 0: Falling Edge 1: Rising Edge Bit 2 ~ Bit 7: reserved 7.3.5 I/O Control Registers – IOCA~IOCF (0x86~0x8B) OCX is used to determine the data direction of its corresponding I/O port bit. 0: configure a selected I/O pin as output 1: configure a selected I/O pin as input The only four least significant bits of Port F and the only five least significant bits of Port C are available 7.3.6 Pull-up Resistance Control Registers for Ports – PUCA~PUCF (0x8C ~ 0x91) Each bit of PUCX is used to control the pull-up resistors attached to its corresponding pin respectively. The theoretical value of the resistor is 50 KΩ. However, due to process variation, ±35% variation in resistance must be taken into consideration. PUCX: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PUCX7 PUCX6 PUCX5 PUCX4 PUCX3 PUCX2 PUCX1 PUCX0 0: Pull-up Resistors disconnected 1: Pull-up Resistors attached 7.3.7 Open Drain Control Registers of Port B – ODCB (0x92) ODCB: Open drain control of Port B. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OPCB7 OPCB6 OPCB5 OPCB4 OPCB3 OPCB2 OPCB1 OPCB0 0: Open drain disable 1: Open drain enable Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 35 EM77930 USB+BB Controller 7.3.8 Timer Clock Counter Controller – TCCC (0x93) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - TCCS0 PSR2 PSR1 PSR0 Bits 0 ~ 2 (PSR0 ~ PSR2): Prescaler for TCC. PSR2 PSR1 PSR0 Clock Rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Bit 3 (TCCS0): Clock Source Select TCCS0 Clock Source 0 Selected PLL Clock Source 1 Selected IRC Clock Source Bits 4 ~ 7: Reserved 7.3.9 Free Run Counter Controller – FRCC (0x94) Bit 7 - Bit 6 Bit 5 Bit 4 Bit 3 OSCO2E OSCO2SL1 OSCO2SL0 PPSCL2 Bit 2 Bit 1 Bit 0 PPSCL1 PPSCL0 FRCCS Bit 0 (FRCCS): Clock Source Select. FRCCS Clock Source 0 Selected PLL Clock Source 1 Selected IRC Clock Source Bit 1 ~ 3 (PSR0 ~ PSR2): Prescaler for the OSCO2 clock output. 36 • PPSCL2 PPSCL1 PPSCL0 Clock Rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller Bit 4 and Bit 5 (OSCO2SL0 and OSCO1SL1): System Clock Frequency Select Control Bits OSCO2SL0 OSCO2SL1 Output Frequency (MHz) 0 0 6 0 1 12 1 0 24 1 1 48 Bit 6 (OSCO2E): Enable the OSCO2 output. 0: OSCO2 disabled, output low; 1: OSCO2 enabled. Bit 7 is reserved. 7.3.10 Watchdog Timer Controller – WDTC (0x95) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GREEN - - WDTCE - RAT2 RAT1 RAT0 Bit 0 ~ 2 (RAT0 ~ RAT2): Prescaler of WDT. RAT2 RAT1 RAT0 Clock Rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Bit 4 (WDTCE): Enable the WDT Counter 0: WDT disabled 1: WDT enabled Bits 7 (GREEN): for power saving purposes, the system clock can be changed to external RC mode. 0: Normal Mode 1: Green Mode Bit 3, 5 and 6 are reserved. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 37 EM77930 USB+BB Controller 7.3.11 PWM Control Register – PWMCR (0x98) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - S_PWM0 - - Bit 2 (S_PWM0): Selected PWM0 output enable. 0: disable PWM output 1: enable PWM output Bits 0, 1 and 3 ~ 7 are reserved. 7.3.12 BB Interrupt Control Register – RFINTE (0x99) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CSDE TX_AEE RX_AFE TX_ EMPTYE RX_OFE LINK_ DISE LOCK_OUTE LOCK_ INE Bit 0 (LOCK_INE): LOCK IN interrupt enable bit. Bit 1 (LOCK_OUTE): LOCK OUT interrupt enable bit. Bit 2 (LINK_DISE): LINK_DIS interrupt enable bit. Bit 3 (RX_OFE): The RX FIFO full interrupt enable bit. Bit 4 (TX_EMPTYE): The TX EMPTY interrupt enable bit. Bit 5 (RX_AFE): The RX FIFO almost full interrupt enable bit. Bit 6 (TX_AEE): The TX FIFO almost empty interrupt enable bit. Bit 7 (CSDE): The carrier-sense interrupt enable bit. 0: disable function interrupt 1: enable function interrupt 7.4 USB Status, Control and Configuration Registers These registers are function-oriented registers used by the USB to record, enable or disable the peripheral modules, interrupts, and the operation clock modes. See Section 9.5. 7.5 Code Option Code Option (ROM-0x2FFF) Register SCLK is located on the very last bit of EM77930’s 12K program ROM. These values will be fetched first to be the system initial values during power-on. SCLKC: System Clock Control Register 38 • SCLKC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0x2FFF - - - SCLKC 15 14 13 12 11 10 9 8 0x2FFF - - - - - - - - USBCLK RFCLK1 RFCLK0 SCLK1 Bit 0 SCLK0 Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller Bit 0 ~ Bit 1 (SCLK0 ~ SCLK1): System Clock Frequency Select Control Bits SCLK1 SCLK0 System Clock (MHz) 0 0 6 0 1 12 1 0 24 1 1 48 Bits 2~3 (RFCLK0~RFCLK1): Wireless Modem Clock Frequency Select Control Bits RFCLK1 RFCLK0 System Clock (MHz) 0 0 6 0 1 12 1 0 24 1 1 48 USB 48MHz PLL Clock Source Control Bit Bit 4 (USBCLK): 0: Disable 48 MHz oscillation from PLL. 1: Enable 48 MHz oscillation from PLL for USB during power-on. Reserved Bits 5 ~ 15: 8 SCLK [1:0] RFCLK [1:0] USB_ CLK WDT_ CON.GREEN SYS CLK 00 00 0 0 6 (Bypass) 00/01/10/11 01/10/11 0 0 6/12/24/48 12/24/48 48 01/10/11 00/01/10/11 0 0 12/24/48 6/12/24/48 48 00/01/10/11 00/01/10/11 1 0 6/12/24/48 6/12/24/48 48 00/01/10/11 00/01/10/11 0/1 1 IRC - - RF CLK USB CLK 6 (Bypass) 6 (Bypass) Base Band (BB) 8.1 BB: Standard Interface to the RFW102 Series 8.1.1 Features Parallel interface to RFW102 modem. Serial to Parallel conversion of RFW102 interface. Input FIFO (RX_FIFO). Output FIFO (TX_FIFO). Preamble Correlation. Packet Address Filter (Network and unique). Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 39 EM77930 USB+BB Controller CRC calculation Working Frequencies: 6-24MHz Power Saving modes: Idle mode, Power-down mode Inter-RFWAVES networks Carrier-sense Discharge of the RFW-102 reference capacitor Compensate for clock drifts between the transmitting EM77930 and the receiving EM77930 up to 1000ppm. Hence, the EM77930 requires low performance crystal. Interrupt Driver – connected to the EM77930’s internal interrupt and informs the EM77930 about BB events. 8.1.2 Description RFWAVES has developed a very low cost wireless modem (RFW102) for short range, cost-sensitive applications. The modem is a physical layer element (PHY) – allowing the transmission and reception of bits from one end to the other. In an RFWAVES application, the MCU is in charge of the MAC layer protocol. In order to reduce the real-time demands of the MCU handling the MAC protocol, the BB was developed. The BB enables the MCU an easy interface to RFW102 through a parallel interface, similar to memory access. It converts the fast serial input to 8-bit words, which are much easier for an 8-bit MCU to work with and requires a lower rate oscillator. It buffers the input through a TBD bytes FIFO, enabling the MCU to access the BB more efficiently. Instead of reading one byte per interrupt, the MCU can read up to 16 bytes in each interrupt. This reduces the MCU overhead in reading incoming words, insofar as stack stuffing and pipeline emptying are concerned, in cases where each incoming byte causes an interrupt. When using the FIFO, the MCU pays the same overhead for all the FIFO bytes as it paid for only one byte without a FIFO. Having a low-cost BB with a built-in state machine that can support basic wireless communication elements would present the following advantages: 40 • Shorter development time, hence shorter time to market. Save CPU power and other resources for other applications. Offer an easy, standard integrated solution. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 8.1.3 I/O and Package Description BB MCU RAM_ADDR [0~6] 7 DATA [0~7] 8 RAM_ADDR [0~6] DATA [0~7] RD_n RD_n WR_n WR_n CS_n CS_n RST RFW-102 Serial IO Data IO TX_RX TX_RX RF_Active RF_Active RST TX_AE RX_AF TX_EMPTY CS LOCK_IN LOCK_OUT TX_AE RX_AF TX_EMPTY CS LOCK_IN LOCK_OUT SHDWN SHDWN RF CLK RF CLK Fig. 8-1 Parallel Interface between the MCU and RFW-102 through BB Name Type Description I/O This bus comprises of eight TRI-STATE input/output lines. The bus provides bidirectional communication between the system and the MCU. Data, control words, and status information are transferred via the DATA [0-7] data bus. RD_n I When RD_n is low while the system is enabled, BB outputs one of its internal register values to DATA[0-7] according to RAM_ADDR[0-6]. WR_n I When WR_n is low while the system is enabled, BB enables writing to its internal registers. The register is determined by RAM_ADDR [0-6] and the value DATA[0-7]. RAM_ADDR[0-6] I These four input signals determine the register to which the MCU writes to or reads from. DATA [0-7] CS_n I Chip select input pin. When CS_n is low, the chip is selected; when high, the chip is disabled. This pin overrides all pins excluding RST. This enables communication between BB and the MCU. This pin functions as wake-up pin for power-down and idle modes. TX_AE Interrupt driver pins. TX_EMPTY LOCK_IN This pin goes high whenever any of the interrupt sources has an active high condition and is enabled via the IER. The purpose of this pin is to notify the MCU through its external interrupt pin that an event (such as empty TX_FIFO) has occurred. LOCK_OUT Goes low when IER register is read. RX_AF CS O Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 41 EM77930 USB+BB Controller Name Type Description Chip’s reset pin. RST I When this pin is set high, all registers and FIFOs are cleared to their initial values. All transceiver traffic is disabled and aborted. Reset is asynchronous to system clock. After power-up, a pulse in RST input should be applied (by POR). SHDWN I Shut Down BB RF_ACTIVE O This output pin controls the RFW102 working/shutdown mode. Its values are determined by SCR4(1). SERIAL_IO I/O Serial input or output according to TX_RX mode. It functions as serial interface for the RFW-102 (RFWAVES modem). When SERIAL_IO is input, it is a Schmitt-trigger input. This pin controls the RFW-102 operation mode. It should be connected to RFW-102 RX_TX input pin. When RX_TX is low, RFW-102 is in receiving mode. RX_TX O When RX_TX is high, RFW-102 is in transmitting mode. In most cases RX_TX output pin is determined by SCR2(0) register. SCR3(7) and the capacitor discharge mechanism has effects on this pin. RF_CLK I Clock for RF operation 8.1.4 BB Architecture Interrupt Handler INT Address Bus Data Bus Parallel Interface RX FIFO Control & Status Registers TX FIFO Address Filter Receiver Preamble Correlation Serial Input/ Output CRC Transmitter Fig. 8-2 BB Block Diagram 42 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 8.2 BB Description 8.2.1 Reset A reset is achieved by holding the RST pin high for at least TBD oscillator cycles. To ensure good power-up, a reset should be given to BB after power-up. 8.2.2 Power Saving Modes The BB is designed to work in similar working modes as a typical MCU. These modes enable the system to save power when the BB is not in use. 8.2.2.1 Power-Down Mode The MCU can halt all activity in the BB by stopping its clock. This enables the MCU to reduce the power consumption of the BB to a minimum. All registers and FIFOs retain their values when BB is in power-down mode. BB enters power-down mode by setting the bit TBD to “1”. This bit is set by MCU and cleared by BB. BB goes back to working mode by setting CS_n input pin to “0” for TBD msec. The wake-up time of the BB from power-down mode to fully operating mode is TBD msec. Since BB retains all the register values in power-down mode, special care should be given to the register values before it enters power-down. For example, the MCU should check that the BB is not in the middle of transmitting or receiving a packet. The RFACTIVE should be set low to shutdown the RFW-102, before entering power-down mode. 8.2.2.2 Idle Mode In idle mode, the BB internally blocks the clock input. The external clock is not stopped, but it is not routed to the internal logic. By doing this, the MCU achieves substantial power savings and yet the wake-up time is still relatively short. The power consumption is not minimal since the external clock is still active. All registers and FIFOs retain their values when BB is in idle mode. BB enters idle mode by setting bit TBD to “1”. This bit is set by MCU and cleared by BB. BB goes back to working mode by setting CS_n input pin to “0” for TBD μsec. Since BB retains all the register values in idle mode, special care should be given to the register values before BB enters idle mode. For example, the MCU should check that the BB is not in the middle of transmitting or receiving a packet. In addition, the RFACTIVE should be set low to shutdown the RFW-102. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 43 EM77930 USB+BB Controller 8.2.3 Preamble Correlation The transmitting BB sends the Preamble in order to synchronize the receiver to its transmission. BB transmits a fixed size Preamble of 16 bits. The received Preamble has a variable length of 16Ù9 bits, determined by SCR2 [5:7]. The receiver correlates the 16Ù9 bits from its PRE-L and PRE-H registers to the 16Ù9 bits in its input shift-register. If a correlation is found, then the BB receiver state machine is enabled. The purpose of the Preamble is to filter the module packets from white noise or other transmissions on the channel. NODE_ID and NET_ID filter are used to filter packets from other module networks. The Preamble is transmitted MSB to LSB (PRE-H first and then PRE-L). The value of the Preamble is determined according to PRE-L and PRE-H registers. The BB has the same Preamble when it is in transmitting mode (TX_RX=1) as when it is in receiving mode (TX_RX=0). The value of the PRE-L and PRE-H registers should be identical in the BB in all nodes in the network. 8.2.4 Refresh Bit When receiving a valid packet, the RFWaves modem (PHY layer) has to receive a “1” symbol each time a certain period has elapsed in order to maintain its sensitivity. T he time between adjacent “1” symbols is determined by the value of the reference capacitor. This constraint is transparent to the application layer since the BB adds a “1” symbol (refresh bit) if too many “0” symbols are transmitted consecutively. On the receiver side, these additional “1” symbols (refresh bits) are removed by the BB. This feature is transparent to the application layer. The application layer has only to initialize the maximum allowed number of consecutive x“00” bytes. The BB has the flexibility to add a refresh bit every 1 to 7 bytes. This is configured by RB(0:2) bits in PPR register. The value of RB (0:2) bits in PPR register determines the overhead the refresh bit has on the throughput of the link. The refresh bit does not add substantial overhead on the bit stream, since it is only added when the number of consecutive x”00” bytes exceeds a certain value. The data that is sent is application-dependent, so the application can be adjusted in order that there will be a negligible probability of this event happening. Typical RFWaves capacitor: C=1nF Normal discharge current = 200nA Each 10mV on the capacitor represent 1dB in receiving power. 44 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 200nA 1dB I = = C ⋅ V 1nF ⋅ 10mV 50 μ sec The capacitor is charged with each received “1” symbol. The receiver is allowed to lose 1dB before a new “1” is to be received. Thus, after each 50 consecutive “0” bits in 1Mbps (50μsec) a “1” symbol should be sent. In this case, setting RB [0:2] in PPR register to be 5 (“101”) would be sufficient (5 bytes = 40bits). When RB (0:2) bits are set to “000” a refresh bit is added to every transmitted byte, regardless of its content. This introduces a constant overhead of 12.5%. 8.2.5 Bit Structure The BB uses an oscillator ranging from 6Ù24 MHz. In order to determine the output and input bit rate, the BB must be configured to the number of clocks consisting each bit. This gives the applicator the control over the bit rate with certain restrictions. Each bit must have at least six clock cycles. The maximum bit rate is: 1Mbps The minimum bit rate is: 10Kbps (TBD) However it is recommended to work only at 1Mbps since reducing the bit rate does not change the energy of a transmitted bit. This means that reducing the bit-rate does not improve the bit error rate or the range between the transmitter and the receiver. Bit Length Register (BLR) determines the number of clock cycles per bit (bit period). BLR value is given a fixed offset of 6, since the minimum number of clock cycles in one bit is 6. Bit Rate = Oscillator / (BLR+6) The BB outputs (for the RFW-102) the bit structure shown below. Bit "1" Structure - Even Clock Number Clock Period Bit Period Bit "1" Structure - Odd Clock Number Clock Period Bit Period Fig. 8-3 Bit Structure of the BB output to the RFW-102 In the odd number of clocks example BLR=1. In the even number of clocks example BLR=2. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 45 EM77930 USB+BB Controller The number of clocks when the line is “1” is determined as follows: ⎡⎛ BLR + 6 ⎞ ⎤ Number of "1" s = FLOOR ⎢⎜ ⎟ − 1⎥ 2 ⎠ ⎢⎣⎝ ⎥⎦ In case of “0” bit, BB output “0” value for BLR+6 clock pulses. * FLOOR – Rounds towards zero. 8.2.6 CRC The BB adds additional CRC information to each packet in the transmitter module, in order to enable the protocol to detect errors. The CRC is a redundant code, which is calculated and added to each packet on the transmitter side. The CRC is also calculated on the receiver side. The CRC calculation results of the receiver and the CRC field in the received packet are compared in the receiver using the CRC module in the chip. If the CRC results are equal, then the receiver knows with reasonable probability that the packet was received correctly. If the CRC results are not equal then the receiver knows with probability 1 that the packet was received incorrectly. The CRC mode is configured in the PPR (3:4) register. Both the receiving node and the transmitting node in the network have to be in the same CRC mode. The BB can apply CRC in three different ways: 2 15 16-Bit CRC – using polynomial 1+X +X +X 2 16 8 8-Bit CRC – using polynomial 1+X+X +X No CRC. This gives each application the flexibility to choose the adequate amount of overhead it adds to each packet and the corresponding level of protection the CRC code has. If CRC is enabled, then the BB calculates the CRC of each incoming packet. It does not put the received CRC value in the RX_FIFO. It just puts the result of its calculation in the RX_FIFO as the last byte of the packet: 0x55 – CRC received correctly. 0xAA – CRC was received incorrectly. The status bit SSR (0) stores the result of the last received packet. 8.2.7 RX FIFO All received bytes are transferred to the RX_FIFO. The RX_FIFO stores the input data until the MCU reads the data from it. CRC and Preamble bytes are not transferred to the RX_FIFO. 46 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller The RX_FIFO is accessed just like all other read-only registers in the BB. The MCU cannot write to RX_FIFO - it can only read from it. RX_FIFO_SIZE is 16 bytes. The purpose of having an input FIFO in BB is to reduce the real-time burden from the MCU. The FIFO is used as a buffer, which theoretically enables the MCU to read the incoming data every RX_FIFO_SIZE * 8 bit/byte * 1μsec = 128μsec, and not every 1μsec in the case of serial input, or every 8μsec in the case where there is a serial to parallel converter. The actual buffer size for practical use is a bit smaller, since the MCU response time is taken into account. The MCU has three ways to learn about the RX_FIFO status: The RX FIFO Status Register (RFSR) contains the number of bytes in the RX_FIFO. BB INT pin. If configured appropriately, the INT pin will be “1” each time RX_FIFO is almost full. This invokes a MCU interrupt if the INT pin is connected to the MCU external interrupt pin. RX_FIFO Overflow Status Bit – bit RX_OF in SSR indicates when an overflow event has occurred. If a received byte is written to a full RX_FIFO, the last byte in the RX_FIFO is override and the RX_OF flag is raised. The RX_AF interrupt should invoke the MCU to read from the RX_FIFO. Using the almost full event gives the MCU 32μsec (4 bytes * 8μsec) to respond before it loses data, assuming a bit rate of 1Mbps. It uses most of the RX_FIFO size even if the response latency of the MCU is very short. Should the MCU not respond properly to the almost full event, and an input byte is written to the RX_FIFO when it was full, then this byte would overrun the last byte in the RX_FIFO, meaning the byte that immediately preceded it. LOCK_OUT interrupt should also trigger the MCU to read from the RX_FIFO. In case a packet has ended and the RX_AF interrupt was not invoked, the MCU should be triggered by the LOCK_OUT interrupt. 8.2.8 TX FIFO Transmitting data is done by writing it to the TX_FIFO. The interface to the TX_FIFO is similar to all the other write-only registers in BB. The purpose of the TX_FIFO is to reduce the real-time transmission process from the MCU. The TX_FIFO enables the MCU, theoretically, to write to the TX_FIFO every 128μsec and not every 8μsec, as is the case with a regular 8-bit shift register. The TX_FIFO Status Register (TFSR) indicates the number of bytes in the TX_FIFO. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 47 EM77930 USB+BB Controller The TX_FIFO can also invoke an MCU interrupt if TX_FIFO almost empty event occurs. Almost empty flag will rise when there are only four empty bytes in the TX_FIFO. It gives the MCU 32μsec response time to reload the TX_FIFO in case the transmitted packet is bigger than the TX_FIFO. In case the MCU writes to a full TX_FIFO, then this byte overruns the last byte in the TX_FIFO, meaning the byte that was written just before it. Writing to a full TX_FIFO sets the TX_OF flag in SSR. 8.2.9 Interrupt Driver The INT output pin is the summation of all interrupts source in the BB. Whenever an interrupt event has occurred and this interrupt is enabled (IER), the INT will go from low to high. The INT will remain high until the IIR register is read. The IIR register contains all the interrupt events that have occurred since the last read. It shows the event only for enabled interrupts. If an interrupt is disabled, even if the event that invoked this interrupt has occurred, the interrupt flag will be low. The IER register is used to enable/disable each of the interrupt. SCR4 (0) enables/disables all the interrupts. There are eight events in the BB that can cause the INT pin to go from low to high: 1. LOCK_IN – This interrupt indicates that the BB has started receiving a new packet. The Preamble has been identified. If the NET_ID and/or the NODE_ID are enabled, then they have been identified correctly. This event signals the beginning of an incoming packet. 2. LOCK OUT – BB has just finished receiving a packet. This means that if the BB is in fixed packet size mode, then it has finished receiving PSR bytes not including CRC bytes. If BB is not in fixed packet size mode, then it has just finished receiving a packet of size as indicated in the packet header. Although RX_STOP and setting TX_RX=1 (SCR2) terminate the receiving of the packet, they do not cause a LOCK_OUT event, since the MCU is already aware of it (the MCU initiated it). The LOCK_OUT interrupt tells the MCU when to get data out of the RX_FIFO. 3. LINK_DIS – This interrupt indicates that a “Zero counter” capacitor discharge event has occurred. If a consecutive number of zero bits (according to SCR3 (4:6)) have been received, this interrupt is set, even if zero count capacitor discharge is disabled (SCR3 (3) – EN_ZERO_DIS = ’0’). The actual capacitor discharge and its interrupt are two separate registers (IER (2) for the interrupt and SCR3 (3) for the discharge). 4. RX_OF – This interrupt indicates that a byte from an incoming packet was discarded, since the RX_FIFO was already full. The receiver module tried to write a byte to a full RX_FIFO. The MCU should know that the corresponding packet is corrupted, since it is lacking at least one byte. 48 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 5. TX_EMPTY – The BB has finished transmitting a packet. Meaning, the transmit shift register is empty and BB is now in RX mode (not TX mode). 6. RX_FIFO_AF – RX_FIFO is almost full. If the MCU does not want the RX_FIFO to overflow, then it should empty it. 7. TX_FIFO_AE – TX_FIFO is almost empty. If the MCU did not finish putting the transmitted packet in the TX_FIFO, then it should continue doing so now. 8. CS – CS status line has gone from “1” to “0” invokes the CS interrupt. This signals the MCU that an unidentified (NET_ID or NODE_ID or Preamble were not identified) packet has ended. If the MCU has a packet to transmit, and CS=”1” then the MCU waits for this event. All these events can be masked. If an event is masked, then even if that event occurs, it does not set the INT pin to “1”. The masking is done by register IER. The reason for masking is that in different applications or in different situation in the same application these events have different priorities. The MCU determines which of these events will invoke an MCU interrupt. Moreover all these events can be masked together by IE in IER register. If INT pin is set to “1”, the MCU learns which event has occurred by reading IIR register. INT goes “0” when the MCU reads from IIR register. 8.2.10 Packet Size There are two types of packet structure determined by PPR [5] (FIXED). Fixed Sized Packet – all packets have the same, fixed size. The packet size is determined in the PSR register. The packet size can be 2 Ù 255 bytes. Variable Sized Packet - the header of the incoming packet determines the packet size. One of the header bytes contains the packet size. Bits SIZE_LOC[0:1] in LCR register determines the location (offset) of the packet size inside each incoming packet header. The BB reads the packet size byte in the packet header according to LCR register. In both cases the packet size does not include the CRC addition or the Preamble. 8.2.11 NET_ID and NODE_ID Filters NET_ID and NODE_ID are two filters in the receiver. They filter incoming packets according to their network address and node address. The address field in each incoming packet is compared to NET_ID byte and NODE_ID byte. If one of the above comparisons fails, then the packet is discarded and the MCU will not be aware of it. NET_ID and NODE_ID are both one byte. Their values are stored in NIR and BIR registers accordingly. The byte to which they are compared is set by LCR register. Each of them can be enabled or disabled independently (PPR register). Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 49 EM77930 USB+BB Controller NET_ID is targeted to be a filter on the network address. It is supposed to be common for all nodes in the network. NODE_ID is targeted to be a filter on the specific node address. It is supposed to be unique to each node in the network. The purpose of these filters is to save MCU power and to reduce its load. In a multi-node network, a node can filter all packets that are not sent to it, while in multi-network environment, a node can filter packets from other RFWaves networks. In certain network a multicast ability inside the network is required. Even if NODE_ID filter is applied, Addresses ‘111111XX’ in NODE_ID filter are preserved for multicast transmissions. NODE_ID filter will not discard those four addresses in any case. 8.2.12 Carrier-Sense Carrier-sense protocols are protocols in which a node (station) listens to the common channel before it starts transmitting. The node tries to identify other transmissions in order to avoid collision that might block its own transmission. In a wider perspective, a network that applies carrier-sense protocol utilizes the channel bandwidth more efficiently. A more efficient network enables lower power consumption to each node, shorter delay and higher probability of reaching the destination of each packet. The BB uses one complimentary technique in order to achieve very wide-ranging carrier-sense abilities. It has an internal implementation of RFWaves Network Carrier-Sense algorithm. This enables it to avoid collision with other RFWaves stations on its network or from other networks in the area. While the Carrier-Sense status bit in SSR (CS) tells the MCU when not to transmit, the two interrupt CS and LINK_DIS gives the MCU a flag when to transmit. LINK_DIS will be invoked whenever any transmission has ended, while CS interrupt will be invoked only when an RFWaves transmission has ended. Some applications can use some of the above mechanisms though not all of them – according to its needs. 8.2.12.1 RFWaves Carrier-Sense Algorithm Assuming our bit rate is 1Mbps. According to the described bit structure (Section 8.2.5 Bit Structure), the time difference between two rising on DATA_IO must be an integer number of 1μsec. If we take into account the frequency deviation between the two BB oscillators, the time difference between two rising edges is 1μsec± . The depends on the frequency deviation between the two BB oscillators. The BB uses this quality in its carrier-sense algorithm. If an N (N = (CSR (0:3)*2)+2) number of “1” bits, where each is preceded by at least one “0” bit, are received with time difference of an integer number of 1μsec between two consecutive “1” bits, then the CS flag in SSR equals ‘1’. Basically, the BB counts “0” to “1” transits on DATA_IO input, where the time difference between two transits should be an integer number (≥2) to 1μsec. The number of consecutive “1” bits that conforms to this rule is counted in the following example (Figure 8-2) in ONE_CNT counter. ONE_CNT is incremented only if a “1” bit that comes after a “0” bit is received, where the time gap between the “1” bit and the 50 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller preceding “1” bit is as mentioned above. If the time difference between two consecutive “1” bits is out of the allowed deviation, the ONE_CNT is reset. ONE_CNT is also reset if the number of consecutive “0” exceeds (CSR (4:7)*2)+2, where CSR is the last “1” bit received is counted in ZERO_CNT. ZERO_CNT is reset each time “1” bit is received. Both M and N values are determined in CSR register (CSR (7:4) and CSR (3:0) accordingly). (0) O N E_C N T=0 ZER O _C NT=1 (2) O N E _C N T=1 ZER O _C NT=1 (3) O NE _C NT=2 ZE RO _CN T=0 (1) O N E _C N T=1 ZER O _C NT=0 (6) O NE _CN T=1 ZER O _C NT=0 (4) O NE _CN T=2 ZE RO _C N T=0 (5) O N E_C N T=2 ZER O _C N T=1 D A TA _IO S ignal 1usec 1usec 2 * 1usec Search W indow 1usec S earch W indow 1usec Search W indow Fig. 8-4 Carrier-Sense Example In the example shown in Figure 8-2, at time (1) a new “1” bit is received after a “0” bit was received. Thus, ONE_CNT equals 1 and ZERO_CNT is reset to 0. At time (2), a zero bit is received, so the ZERO_CNT is incremented. At time (3), a “1” is received after a “0” bit that was received before it. Thus ONE_CNT is incremented and ZERO_CNT is reset. At time (4) a “1” bit is received after a “1” bit, thus, there is no change in any counter. At time (6) a “1” bit is received out of the allowed window, so ONE_CNT is reset to 1. The CSR register is used to configure the carrier-sense algorithm sensitivity. The CSR register determines the number of “1” bits that are required in order to decide that a carrier exists. The CSR also determines the number of successive “0” bits that reset the carrier-sense state machine. In SSR register, bit CS notifies whether a carrier was identified. Carrier-sense can also be used as an interrupt. When CS in SSR goes from ‘1’ to ‘0’ i.e. the transmission has stopped, a CS interrupt is invoked (if enabled in IER). The purpose of this interrupt is to inform the MCU that the channel is free again. If the BB identifies a packet, the carrier-sense algorithm halts. When the BB is in RX mode and the LOCK flag in SSR is “0”, the CS mechanism is working. When the LOCK flag in SSR is “1”, the CS mechanism is not working, since the CS flag does not add any information because a Preamble was identified already. After a Preamble was identified the CS in SSR equals ‘1’. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 51 EM77930 USB+BB Controller 8.2.13 Receiver Reference Capacitor Discharge The BB implements two independent mechanisms for receiver capacitor discharge: At the end of each received packet. Zero counter. Mechanism 1 is enabled/disabled by bit EN_CAP_DISCH in SCR3. Mechanism 2 is enabled/disabled by bit EN_ZERO_DISCH in SCR3. The number of “0” bits that will cause a discharge in Mechanism 2 are determined by bits ZERO_DISCH_CNT [0:2]. For both mechanisms, the discharge time is determined by CAP_DIS_PERIOD in SCR3. Discharge is done by setting RX_TX pin to ‘1’ for a certain time and then setting it back to ‘0’. (*) More detailed explanations of the reference capacitor discharge algorithms and motivations can be found in the “RFW - Capacitor Discharge.pdf” document. 8.2.14 Changing the BB Configuration It is not recommended to change the BB configuration while it is in the middle of receiving or transmitting a packet. Thus, before writing to any of the BB control registers (such as BLR, PRE-L, PRE-H, PPR etc): Change the TX_RX mode to RX. Disable the Preamble search (SEARCH_EN in SCR2) Stop all RX receiving – RX_STOP. It is then safe to change the BB configuration. 8.2.15 Input Synchronizer Handling asynchronous inputs to the BB. Asynchronous Input Synchronized Input S R SET CLR Q S Q R SET CLR Q Q CLK 52 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 8.3 Register Description The registers in the BB are divided into three groups: Read-only registers which are mainly status registers. Write-only registers which are mainly control registers. Read and write registers. In case of an RST pulse, all registers are set to their default value. 8.3.1 Bit Length Register (BLR) This register is both a read and a write register. It determines the length of the bit in terms of clock cycles. The bit length will be (BLR+6) clocks, since the minimum length of a bit is 6 clocks. Default Value: 00 (0+6=6). 8.3.2 Preamble Low Register (PRE-L) This register is a write-only register. This register contains the 8 least significant bits of the Preamble. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PRE-L PR-7 PR-6 PR-5 PR-4 PR-3 PR-2 PR-1 PR-0 Default Value: 0xEB. 8.3.3 Preamble High Register (PRE-H) This register is a write-only register. This register contains the 8 most significant bits of the Preamble. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PRE-H PR-15 PR-14 PR-13 PR-12 PR-11 PR-10 PR-9 PR-8 Default Value: 0xFF. 8.3.4 Packet Parameter Register (PPR) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PPR NET ID_EN NODE ID_EN FIXED CRC1 CRC0 RB-2 RB-1 RB-0 This is a read and a write register. It contains the control bits of the transmitted and received packet structure. Default Value: 0x3A. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 53 EM77930 USB+BB Controller Bits 0-2 (RB-0~RB-2): Refresh Bits These bits determine the maximum number of successive “zero” bytes allowed before an added “one” bit is stuffed to the packet by the transmitter state machine. The reason for this feature is to keep the RFW-102 reference capacitor charged. Refresh Bit Bit 2 Bit 1 Bit 0 Refresh bit is added to every byte. 0 0 0 Refresh bit is added if 1 byte equals x”00”. 0 0 1 Refresh bit is added if 2 successive bytes equal x”00”. 0 1 0 Refresh bit is added if 3 successive bytes equal x”00”. 0 1 1 Refresh bit is added if 4 successive bytes equal x”00”. 1 0 0 Refresh bit is added if 5 successive bytes equal x”00”. 1 0 1 Refresh bit is added if 6 successive bytes equal x”00”. 1 1 0 Refresh bit is added if 7 successive bytes equal x”00”. 1 1 1 The value of the refresh bit is determined by the value of the reference capacitor. Bits 3, 4: CRC [0:1] These bits control the CRC operation for both transmit and receive mode: Bit 5: CRC Bit 4 Bit 3 No CRC 0 0 CRC8 0 1 CRC8 1 0 CRC16 1 1 Fixed This controls the packet mode. When high system packets are fixed size and the length is specified in the Packet Size Register (PSR). When Fixed is low, the packet size is variable. The size is specified in the header of the incoming or outgoing packets. The location of the packet size field is specified in the LCR register. Bit 6: NODE_ID_EN This is NODE_ID control bit. 0: Disables Node ID search 1: Enables Node ID search according to LCR, BIR Bit 7: NET_ID_EN This is NET_ID control bit. 0: Disables Net ID search 1: Enables Net ID search according to LCR, NIR 54 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 8.3.5 System Control Register 1 (SCR1) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 N/A N/A N/A N/A N/A N/A N/A N/A N/A This byte is reserved. Default Value: 0x00. 8.3.6 System Control Register 2 (SCR2) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCR2 PRE MASK 2 PRE MASK 1 PRE MASK 0 STOP RX TX FIFO RESET RX FIFO RESET SEAR CH EN TX_R X This register is a read and a write register. This register controls the system operation modes. Bit 0: TX_RX Controls the transceiver mode: receive mode or transmit mode When TX_RX is low – BB is in receive mode (default mode). The output pin RX_TX is set to ‘0’. BB searches for a Preamble. If Preamble is found, it handles the process of receiving a packet. If SCR3 (7) is set, then the BB goes to RX mode and the output pin RX_TX is in TX mode. The capacitor discharge can change the output pin RX_TX to TX mode even if we are in RX mode in the BB. In this case the output pin RX_TX will be in TX for a short duration and then return to RX mode. When TX_RX is high – BB is in transmit mode. The output pin RX_TX is set to ‘1’. The BB handles the process of transmitting a packet according to the data in the TX_FIFO. When it finishes transmitting the packet, it automatically goes back to receive mode. Bit 1: SEARCH_EN Preamble search enable bit. When 1: Enables the search for Preamble in receive mode. When 0: Disables the search for Preamble in receive mode, (used when user configures the system while in default receive mode). This bit’s default value is ‘0’. It must be set to ‘1’ in order to start receiving a packet. Bit 2: RX_FIFO_RESET This bit resets the RX_FIFO address pointers when set to Logic 1. This bit is set by the MCU and is cleared automatically by the BB. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 55 EM77930 USB+BB Controller Bit 3: TX_FIFO_RESET This bit resets the TX_FIFO address pointers when set to Logic 1. This bit is set by the MCU and is cleared automatically by the BB. Bit 4: STOP_RX This bit stops receiving the current command, resets the RX_FIFO counters and start new searches for a preamble. This bit is set by the MCU and is cleared automatically by the BB. Bits 5-7: PRE_MASK [0:2] These bits determine the mask on PRE-H in preamble correlation. Meaning, it determines the size of the Preamble in the receiver. The PRE-L is always used in the Preamble correlation. BB cuts off bit from PRE-H register, starting from the MSB. PRE PRE PRE MASK 0 MASK 1 MASK 2 0 0 0 16 0 0 1 15 0 1 0 14 0 1 1 13 1 0 0 12 1 0 1 11 1 1 0 10 1 1 1 9 Preamble Size Default Value: 0x60 8.3.7 System Control Register 3 (SCR3) This register is a read and a write register. Name Bit 7 SCR3 LOW MODE Bit 1: Bit 6 Bit 5 Bit 4 Bit 3 ZERO ZERO ZERO EN DISCH CNT 2 DISCH CNT 1 DISCH CNT 0 ZERO DISCH Bit 2 Bit 1 Bit 0 CAP DIS PERIOD EN CAP DISCH. - EN_CAP_DISCH Enables/disables capacitor discharge mechanism after each received packet: 0: Disables discharge 1: Enables discharge This bit overrides Bit 3 56 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller Bit 2: CAP_DIS_PERIOD Determines the capacitor discharge duration: 0: The pulse width is 36 clocks, (3 μsec at 12 MHz clock). 1: The pulse width is 72 clocks, (3 μsec at 24 MHz clock). Bit 3: EN_ZERO_DISCH Enables/disables zero counter mechanism for capacitor discharge: 0: Disables discharge 1: Enables discharge Bits 4-6: ZERO_DISCH_CNT [0:2] Determine the number of zero bits that will trigger a capacitor discharge by the zero counter mechanism. Bit 7: ZERO DISCH CNT 0 ZERO DISCH CNT 1 ZERO DISCH CNT 2 Number of Zeros 0 0 0 5 0 0 1 10 0 1 0 15 0 1 1 20 1 0 0 25 1 0 1 30 1 1 0 35 1 1 1 40 LOW_MODE Enables or disables low power mode for RFW-102: 0: Disables low mode (normal mode) 1: Enables low mode. BB is in RX mode, while RFW-102 is in TX mode. The user has to put the BB into RX mode and to disable RX and PREAMBLE search, before enabling LOW_MODE. This transfers the RFW-102 to TX mode using RX_TX pin, while the BB is still in RX mode. RFW-102 power consumption is lower in TX mode than in RX mode. BB can not remain in TX mode, if it is not transmitting. The low mode is the combination of both of the above. Default Value: 0x01 Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 57 EM77930 USB+BB Controller 8.3.8 System Control Register 4 (SCR4) This register is a read and a write register. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCR4 N/A N/A N/A N/A FIFO FLAGS WIN CONT RF_ACTIVE IE Bit 0: IE This flag enables all interrupts when set to ‘1’. When ‘0’, all interrupts are disabled. Bit 1: RF_ACTIVE This bit controls the RF_ACTIVE pin. When this bit is high, the RF Modem is active. Bit 2: WIN CONT This bit determines the size of the WINDOW in the Preamble search module. IF (BLR+6)>14 and WIN_CONT=1, then the preamble window size is 5. Bit 3: FIFO FLAGS Determines the RX_FIFO AF flag and TX_FIFO AE flag: IF FIFO FLAGS = 0 then AF = 12 and AE = 4. IF FIFO FLAGS = 1 then AF = 8 and AE = 8. Default Value: 0x00. 8.3.9 Transmit FIFO Status Register (TFSR) This register is a read-only register. It contains the number of bytes in the TX_FIFO. Default Value: 0x00 (TX_FIFO empty). 8.3.10 Receive FIFO Status Register (RFSR) This register is a read-only register. It contains the number of bytes in the RX_FIFO. Default Value: 0x00 (TR_FIFO empty). 58 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 8.3.11 Location Control Register (LCR) This is a read and a write register. Name LCR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - SIZE LOC 2 SIZE LOC 1 SIZE LOC 0 NET LOC1 NET LOC 0 NODE LOC 1 NODE LOC 0 Bits 0, 1: NODE_LOC [0:1] These bits determine the location of the NODE_ID parameter in the header (the location is specified in bytes excluding preamble). The location should be fixed for all of the different kinds of packets transferred by the system. NODE_ID must never be set to be smaller than NET_ID, if both filters are enabled. Location NODE LOC 1 NODE LOC 0 2 0 0 3 0 1 4 1 0 5 1 1 Bits 2, 3: NET_LOC [0:1] These bits determine the location of the NET_ID parameter in the header (the location is specified in bytes excluding preamble). The location should be fixed for all of the different kinds of packets transferred by the system. Bits 4-5: Location NET LOC 1 NET LOC 0 1 0 0 2 0 1 3 1 0 4 1 1 SIZE_LOC [0:2] These bits determine the location of the Packet Size parameter in the header (the location is specified in bytes excluding preamble). The location should be fixed for all of the different kinds of packets transferred by the system. Location Size LOC 2 Size LOC 1 Size LOC 0 2 0 0 0 3 0 0 1 4 0 1 0 5 0 1 1 6 1 0 0 7 1 0 1 8 1 1 0 9 1 1 1 Default Value: 0x00 Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 59 EM77930 USB+BB Controller 8.3.12 Node Identity Register (BIR) This is a read and a write register. When the Receiver State Machine builds the incoming packet, it compares the value in the BIR register to the received data at the location specified in LCR. If the received NODE_ID and the expected NODE_ID are not equal, the packet is discarded. Four multicast NODE_ID addresses are implemented “111111XX”. All packets whose 6 MSBs are “1” are not discarded. Default Value: 0x00 8.3.13 Net Identity Register (NIR) This is a read and a write register. When the Receiver State Machine builds the incoming packet, it compares the value in the NIR to the received data at the location specified in LCR. If received NET_ID and the expected NET_ID are not equal, the packet is discarded. Default Value: 0x00 8.3.14 System Status Register (SSR) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSR - TX_UF BIT_ERROR LOCK CS TX EMPTY LOCKED CRCERROR This register is a read-only register. It provides status information to the MCU concerning the communication line and the data transfer. Bits 1, 2, 3 can trigger the interrupt if enabled in the IER. Bits 0, 5 and 6 are set by H/W and cleared automatically after the MCU reads the register. Bits 1~4 are set and cleared by H/W Bit 0: CRC_ERROR This flag indicates a CRC Error in the packet. The CRC Block sets this flag at the end of each received packet according to the CRC calculation result. BB compares the calculated CRC and the received CRC. When these values differ, the flag goes high. The flag is cleared only after the MCU reads the SSR register. If the MCU does not read the SSR register, this flag remains “1”. 60 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller Bit 1: LOCKED This flag indicates that a packet is being received. Bit 1 is set to logic 1 whenever the system identifies a new incoming packet (triggers LOCK IN interrupt). The bit will reset to Logic 0 when the packet ends (triggers LOCK OUT interrupt) or when one of the IDs fails (NET or BYTE). This indicator is important whenever we want to switch to transmit mode because it can tell us that the line is busy and that in most cases the transmission will not succeed. The Lock triggers interrupt for every change in the bit status. Bit 2: TX_EMPTY This bit is the Transmitter Empty flag. When this bit is high, the system is available for loading the next packet for transmission and BB is in receive mode. When the flag is low, BB is in the middle of a packet transmission. When transmitting few successive packets, the MCU should wait to the end of a packet before it reloads the TX_FIFO with the next packet. Bit 3: CS Carrier Sense detection bit When this bit is high, the system has identified a structure of packet transmission in the air according to CSR. When low, no carrier has been detected. This bit is only valid in receive mode. The conditions for setting or clearing this flag are determined in the CS register. When LOCKED is high, then CS is meaningless. Bit 4: LOCK This signals whether a Preamble was identified or is still searching. When the flag is “0”, the receiver is searching for Preamble. When the flag is “1” a Preamble was identified. If a packet was discarded for any reason, the LOCK flag goes to 1. Bit 5: BIT_ERROR This flag indicates that there was some error in the received package. The packet was not received according to the expected timing specifications. The packet can still pass CRC verification. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 61 EM77930 USB+BB Controller Bit 6: TX_UF This flag is set whenever the MCU reads a byte from an empty TX_FIFO. This flag indicates abnormal end of packet transmission. The MCU transmitter’s state machine has expected to find a valid byte in the TX_FIFO according to the packet size, but it found an empty TX_FIFO. When this event occurs, the TX_EMPTY interrupt is invoked and TX_UF (underflow) flag is set to ‘1’. This flag is set by hardware and cleared by the MCU. It is cleared whenever the MCU reads the SSR register. Default Value: 0x04. 8.3.15 Packet Size Register (PSR) This is a read and a write register. It contains the Packet Size in byte units. When working in fixed size packets (see Control Bit-1), the size will be fixed for all types of packets. The size in PSR excludes 2 bytes of Preamble and 2, 1 or 0 bytes of CRC. Default Value: 0x00. 8.3.16 Carrier Sense Register (CSR) This is both a read and a write register. Name CSR Bits 0-3: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ZERO ZERO ZERO ZERO ONE ONE ONE ONE CNT.3 CNT.2 CNT.1 CNT.0 CNT.3 CNT.2 CNT.1 CNT.0 ONE_CNT [0:3] The number of successive “1” bits that set the carrier sense high. Bits 4-7: ZERO_CNT [0:3] The number of successive “0” bits that reset the carrier sense (CS=’0’). Default Value: 0x44 62 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 8.4 Interrupt Registers 8.4.1 Interrupt Enable Register (IER) This register is a write and a read register. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IER CS TX_AE RX AF TX EMPTY RX_OF LINK_D IS LOCK OUT LOCK IN Default Value: 0x00. For all flags in this register, 0: Disable 1: Enable Bit 0: LOCK_IN This flag enables/disables the LOCK IN interrupt. PREABLE + NODE_ID + NET_ID identified correctly triggers LOCK IN interrupt. Bit 1: LOCK_OUT This flag enables/disables the LOCK OUT interrupt. End of received packet triggers LOCK_OUT interrupt. Bit 2: LINK_DIS This flag enables/disables the LINK_DIS interrupt. The zero counter capacitor discharge triggers the LINK_DIS interrupt. Bit 3: RX_OF This flag enables/disables the RX_OF interrupt. End of received packet triggers RX_OF interrupt. Bit 4: TX_EMPTY This flag enables/disables the TX_EMPTY (Transmitter Empty) interrupt. TX_EMPTY interrupt tell the MCU that the transmitter has just finished transmitting a packet. BB goes to RX mode after finishing the transmission of a packet. Bit 5: RX_AF This flag enables/disables the RX_AF interrupt. The RX_AF interrupt is triggered when RX_FIFO AF flag goes from ‘0’ to ‘1’. Bit 6: TX_AE This flag enables/disables the TX_AE interrupt. The TX_AE interrupt is triggered when TX_FIFO AE flag goes from ‘0’ to ‘1’. Bit 7: CS This flag enables/disables the CS interrupt. CS flag in SSR negative edge triggers CS interrupt. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 63 EM77930 USB+BB Controller 8.4.2 Interrupt Identification Register (IIR) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IIR CS TXAE RX AF TXEMPTY RX_OF LINK_DIS LOCKOUT LOCKIN This is a read only register. When the MCU accesses the IIR, all interrupts freeze. While the MCU access is occurring, the system records the changes in the interrupts but waits until the MCU access is complete before updating the register. A flag is active only when the matching interrupt enable bit is set, and does not depend on the IE bit value. The flags are set by H/W and cleared after the MCU reads the register. Bit 0: This bit reflects the LOCK IN flag interrupt when enabled by IER. This bit reflects the LOCK IN flag interrupt when enabled by IER. LOCK_IN interrupt is invoke whenever a PREAMBLE+NET_ID+NODE_ID where recognized. If NET_ID is disabled, then a received PREAMBLE+ NODE_ID invokes the interrupt. If NODE_ID is disabled, then a received PREAMBLE+ NET_ID invokes the interrupt. If NET_ID and NODE_ID are disabled, then a received PREAMBLE invokes the interrupt. Bit 1: This bit reflects the LOCK OUT flag interrupt when enabled by IER. This bit reflects the LOCK OUT flag interrupt when enabled by IER. LOCK_OUT interrupt is invoked whenever RFW-D100 has finished receiving a packet. The end of the packet is determined according to the packet size. Bit 2: This bit reflects the LINK_DIS flag interrupt when enabled by IER. This interrupt is invoked by the zero counter capacitor discharge mechanism. 64 • Bit 3: This bit reflects the RX_OF flag interrupt when enabled by IER. Bit 4: This bit reflects the TX EMPTY flag interrupt when enabled by IER. Bit 5: This bit reflects the RX FIFO AF flag interrupt when enabled by IER. Bit 6: This bit reflects the TX FIFO AE flag interrupt when enabled by IER. Bit 7: CS – when CS flag goes from “1” to “0” an interrupt is invoked. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 8.5 List of BB Register Mapping Register Address Write 0 (00000) TX_FIFO Read RX_FIFO Default Values --- --- 1 (00001) PRE_L 0xFF 2 (00010) PRE_H 0xFF 3 (00011) FRC_L 0xFF 4 (00100) FRC_H 0xFF 5 (00101) SCR1 0x00 6 (00110) SCR2 0x60 7 (00111) SCR3 0x01 8 (01000) SCR4 0x00 9 (01001) LCR 0x00 10 (01010) BIR 0x00 11 (01011) NIR 0x00 12 (01100) PSR 0x00 13 (01101) PPR 0x3A 14 (01110) BLR 0x00 15 (01111) CSR 0x44 16 (10000) IER 0x00 17 (10001) --- IIR --- 18 (10010) --- SSR --- 0x04 19 (10011) --- TFR --- 0x00 20 (10100) --- RFR --- 0x00 Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 65 EM77930 USB+BB Controller 8.6 MCU BB Control Registers 8.6.1 Control Registers List RFAAR (0x2D): Register R2D indicates BB indirect RAM address. RFDB (0x2E): Register R2E indicates BB indirect RAM data. RFACR (0x2F): Register R2F indicates BB RAM access control. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - RRST RFRD RFWR Bit 3 Bit 2 Bit 1 Bit 0 RFINTF (0x30): BB interrupt flags Bit 7 Bit 6 Bit 5 Bit 4 CSDF TX_AEF RX_AFF TX_ EMPTYF RX_OFF LINK_ DISF LOCK_OUTF LOCK_ INF RFINTE (0x99): BB interrupt enable Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CSDE TX_AEE RX_AFE TX_ EMPTYE RX_OFE LINK_ DISE LOCK_OUTE LOCK_ INE PRIE (0x80): Peripherals enable control 66 • Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - USBE BBE - - PWM0E TCCE FRCE Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 8.6.2 BB Control Example ORG 0X0060 BC // TX_EMPTY INT address RFINTF, TX_EMPTYF // RF data send out, clear INT flag. RETI ORG 0X0100 START: BS NOP RFACR, RRST BC RFACR, RRST BS PRIE, BBE // BB power enable. MOV MOV A, #0x10 RFINTE, A // BB INT.TX_EMPTY enable. ENI // BB reset. // enable all INT. RF_TX_INITIAL: WRITE #SCR2, #8 // Reset TX_FIFO, RX mode. WRITE WRITE #BLR, #10 #PPR, #33 // Set bit rate. // Set package size to be fixed. // Refresh bit mode 1. CRC disabled WRITE #PSR, #6 // Set package size to 6. WRITE #PRE_H, #0xDC // Set preamble High byte #PRE_L, #0xA7 value. // Set preamble Low byte WRITE value. RF_SEND_DATA: WRITE #TX_FIFO, #0x01 WRITE #TX_FIFO, #0x02 WRITE #TX_FIFO, #0x03 WRITE WRITE #TX_FIFO, #0x04 #TX_FIFO, #0x05 WRITE #TX_FIFO, #0x06 // Write first byte of package to TX_FIFO. // Write last byte of package to TX_FIFO. READ WRITE #TFR, 0x60 #IER, #16 // Read TFR register data // enable TX_EMPTY INT WRITE #SCR4, #0x03 // enable all INT. WRITE #SCR2, #1 // move from RX to TX mode. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 67 EM77930 USB+BB Controller LOOP: JMP LOOP WRITE_DATA_TO_RF: BC NOP // BB register write SUB RFACR, RFWR NOP BS RET RFACR, RFWR READ_DATA_FROM_RF: NOP // BB register read SUB NOP NOP NOP BC RFACR, RFRD NOP NOP NOP NOP NOP MOV // Note the access time A, RFDB NOP NOP NOP BS RFACR, RFRD RET ; =============================================== WRITE MACRO #CON1, #CON2 MOV MOV A, #CON2 RFDB, A MOV A, #CON1 MOV CALL RFAAR, A WRITE_DATA_TO_RF // BB register write MACRO ENDM ; =============================================== READ MACRO #CON, REG // BB register read MACRO MOV A, #CON MOV RFAAR, A CALL MOV READ_DATA_FROM_RF REG, A ENDM 68 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 9 Universal Serial Bus (USB) 9.1 Block Diagram rst_n usbclk usben mcu_clk speed suspend tx_dp usbint Transceiver 10 rden tx_dm tx_oe_n rx_dp USB Device rx_dm rxd rdadr MCU 8 ubus wren 8 wradr dbus 8 8 Fig. 9-1 USB Function Block Diagram of the EM77930 9.2 USB FIFO Allocation End Point Number End Point Type FIFO Size 64 byte IN 0 Control 1 Interrupt / Bulk / Isochronous 64 byte IN / OUT 2 Interrupt / Bulk / Isochronous 64 byte IN / OUT 3 Interrupt / Bulk / Isochronous 64 byte IN / OUT Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) 64 byte OUT • 69 EM77930 USB+BB Controller 9.3 Pin Description Pin I/O Description usben I USB module enable usbclk I 48MHz clock for USB device rst_n I Reset Active low hardware reset signal to the USB. Speed speed O USB device speed 1: full speed device 0: low speed device Transceiver suspend suspend O Enable /disable transceiver when port suspend 1: Disable transceiver 0: Enable transceiver tx_dp O USB output data puls tx_dm O USB output data minus tx_oe_n O USB data output enable rx_dp I USB input data plus rx_dm I USB input data minus rxd I USB Input data mcuclk I Clock signal from mcu usbint[9:0] O rden I rdadr[7:0] I ubus[7:0] O wren I Interrrup output Active high signals generated by the USB to the MCU. Read enable The signal is asserted high for a read operation. Read address bus Read address generated by MCU for the USB register. selection. Data output Data bus output to MCU Write enable The signal is asserted high for a write operation Write address bus 70 • wradr[7:0] I dbus[7:0] I Write address generated by MCU for the USB register. selection Data input Data bus input to MCU Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 9.4 Timing Diagram of MCU Interface tcycle clk trs trh rden tras trah rdadr trdv ubus tws twh wren twas twah wradr twds twdh dbus Fig. 9-2 MCU Interface Timing Diagram Symbol Parameter Min Max MCU clock cycle time 20ns − trs Read enable setup time 3ns − trh Read enable hold time 0.1ns − tras Read address setup time 3ns − trah Read address hold time 0.1ns − trdv Read data valid time − 5ns tws Write enable setup time 3ns − twh Write enable hold time 0.1ns − tcycle twas Write address setup time 3ns − twah Write address hold time 0.1ns − twds Write data setup time 3ns − twdh Write data hold time 0.1ns − Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 71 EM77930 USB+BB Controller 9.5 USB Device Register Summary Register GCNTR ADDR Reset − 0x1CD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPD − − − RESUME SUSPEND PLUG URST P − − − P/H P/H P P/H EP1CNTR 0x1CE P/H/S − − EPEN − − EPDIR EPTYPE1 EPTYPE0 EP2CNTR 0x1CF P/H/S − − EPEN − − EPDIR EPTYPE1 EPTYPE0 EP3CNTR 0x1D0 P/H/S − − EPEN − − EPDIR EPTYPE1 EPTYPE0 EPINTR 0x1D1 P − − INT3 INT2 INT1 INT0IN INT0TX INT0RX EPINTE 0x1D2 P − − INT3E INT2E INT1E INT0INE INT0TXE INT0RXE − − − − − RUEINT IDLEINT RSTINT STAINTR 0x1D3 P − − − − − P/H P/H P − − − − RUEINTE IDLEINTE RSTINTE ADDR2 ADDR1 ADDR0 STAINTE 0x1D4 P − FAR 0x1D5 P − EP0RXTR 0x1D6 P − EP0RXCSR 0x1D7 P/H/S CDTOG ERRSTS STALLSTS ACKSTS EP0TXCSR 0x1D8 P/H/S CDTOG ERRSTS STALLSTS ACKSTS EP1CSR 0x1D9 P/H/S CDTOG1 ERRSTS1 STALLSTS1 ACKSTS1 EP2CSR 0x1DA P/H/S CDTOG2 ERRSTS2 STALLSTS2 EP3CSR 0x1DB P/H/S CDTOG3 ERRSTS3 X − EP0RXCT6 H/S − EP0RXCTR EP0TXCTR 0x1DC 0x1DD ADDR6 − ADDR5 ADDR4 − ADDR3 − − SETUPOW SETUP OUT DTOGERR DTOG SESTALL RXEN − DTOG SESTALL TXEN DTOGERR1 DTOG1 SESTALL1 RXTXEN1 ACKSTS2 DTOGERR2 DTOG2 SESTALL2 RXTXEN2 STALLSTS3 ACKSTS3 DTOGERR3 DTOG3 SESTALL3 RXTXEN3 EP0RXCT5 EP0RXCT4 EP0RXCT3 EP0RXCT2 EP0RXCT1 EP0RXCT0 EP0TXCT6 EP0TXCT5 EP0TXCT4 EP0TXCT3 EP0TXCT2 EP0TXCT1 EP0TXCT0 EP1CTR 0x1DE H/S − EP1CT6 EP1CT5 EP1CT4 EP1CT3 EPCT2 EPCT1 EPCT0 EP2CTR 0x1DF H/S − EP2CT6 EP2CT5 EP2CT4 EP2CT3 EPCT2 EPCT1 EPCT0 EP3CTR 0x1E0 H/S − EP3CT6 EP3CT5 EP3CT4 EP3CT3 EPCT2 EPCT1 EPCT0 EP0RXDAR 0x1E1 X DATA7 DATA 6 DATA 5 DATA 4 DATA 3 DATA 2 DATA 1 DATA 0 EP0TXDAR 0x1E2 X DATA7 DATA 6 DATA 5 DATA 4 DATA 3 DATA 2 DATA 1 DATA 0 EP1DAR 0x1E3 X DATA7 DATA 6 DATA 5 DATA 4 DATA 3 DATA 2 DATA 1 DATA 0 EP2DAR 0x1E4 X DATA7 DATA 6 DATA 5 DATA 4 DATA 3 DATA 2 DATA 1 DATA 0 EP3DAR 0x1E5 X DATA7 DATA 6 DATA 5 DATA 4 DATA 3 DATA 2 DATA 1 DATA 0 HINTR 0x1E7 X − SOFINT − − − − − − HINTE 0x1E8 X − SOFINTE − − − − − − FNLR 0x1FE X FNHR 0x1FF X FNLR7 − FNLR6 − Legend: “P” = Power-on reset 72 • FNLR5 − FNLR4 FNLR3 − − “H” = Hardware reset FNLR2 FNLR1 FNLR0 FNHR10 FNHR9 FNHR8 “S” = Software reset Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 9.5.1 Bit 0 General Control Register (GCNTR) Field RESET HW R/W0C SW R/W DF 0 Description Software Reset S/W sets this bit and will reset the whole USB compound device. All registers return to their default value and the USB compound device will be in the default state. H/W will clear this bit after the reset is completed. Connect USB device When set to 1 by S/W, 1 will be driven to the connecting pin, thus the pull-high resistance is connected to the USB bus, and the USB compound device is connected to the USB bus. 1 PLUG R R/W 0 When cleared to 0 by S/W, 0 will be driven to the connecting pin, thus the pull-high resistance is not connected to the USB bus, and the USB compound device is not connected to the USB bus. This bit will be reset by SW reset and USB reset. Suspend State Enable 2 SUSPEND R/W0C R/W 0 Set by SW to force the USB device to enter suspend state. SW is allowed to set this bit if the USB bus has been in the idle state for more than 3ms. The USB device will leave the suspend state if the SW clears this bit or the resume bit is set. This bit will be cleared by HW if the resume bit is set. This bit will be reset by SW reset and USB reset. Send Resume to USB Bus 3 RESUME 6-4 Reserved 7 SPD R/W0C R/W 0 R R/W 1 When set to 1, the USB device will send resume signal to the USB bus after the USB bus has been in the idle state for more than 5ms. The resume signal will be driven for 5ms. HW will clear this bit after completing resume sending. USB function speed setting 0: Low-speed device 1: Full-speed device Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 73 EM77930 USB+BB Controller 9.5.2 Endpoint n Control Register (EP1/2/3CNTR) Endpoint 1 Control Register (EP1CNTR) Endpoint 2 Control Register (EP2CNTR) Endpoint 3 Control Register (EP3CNTR) Bit Field HW SW DF Description Endpoint Type. These bits program the type of endpoint. Bit 1 Bit 0 1-0 EPTYPE R R/W 3 Type 0 0 0 1 Un-used Isochronous 1 0 Bulk 1 1 Interrupt Endpoint Direction 2 EPDIR R R/W 1 0=OUT 1=IN 4-3 Reserved 5 EPEN Endpoint Enable/Disable R R/W 0=Disable endpoint 0 1=Enable endpoint 7-6 9.5.3 Bit Reserved Endpoint Interrupt Event Register (EPINTR) Field HW SW DF Description EP0 USB RX Event 0 INT0RX R/W R 0 Set by HW when either SETUP transaction ends with ACK or OUT transaction ends with ACK or STALL. It is also set when SETUPOW (EP0RXTR Register) bit is set. Needs to check EP0RXCSR Register for details. When SW clears all the OUT, SETUP and SETUPOW bits in the EP0RXTR Register, this bit will be cleared automatically. EP0 USB TX Event Set by HW when IN transaction ends with ACK or STALL. 1 INT0TX R/W R/W0C 0 When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. 74 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller Bit Field HW SW DF Description EP0 USB IN Token Event Set by HW when a valid IN token is received. 2 INT0IN R/W R/W0C 0 When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. EP1 Interrupt 3 INT1 R/W R/W0C 0 Set by HW when IN transaction (Interrupt IN / Bulk IN / Isochronous IN) ends with ACK or STALL or OUT transaction (Bulk OUT / Isochronous OUT) ends with ACK or STALL. IN or OUT transaction is determined by Endpoint Type. When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. EP2 Interrupt 4 INT2 R/W R/W0C 0 Set by HW when IN transaction (Interrupt IN / Bulk IN / Isochronous IN) ends with ACK or STALL or OUT transaction (Bulk OUT / Isochronous OUT) ends with ACK or STALL. IN or OUT transaction is determined by Endpoint Type. When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. EP3 Interrupt 5 INT3 R/W R/W0C 0 Set by HW when IN transaction (Interrupt IN / Bulk IN / Isochronous IN) ends with ACK or STALL or OUT transaction (Bulk OUT / Isochronous OUT) ends with ACK or STALL. IN or OUT transaction is determined by Endpoint Type. When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. 6 Reserved 7 Reserved Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 75 EM77930 USB+BB Controller 9.5.4 Endpoint Interrupt Event Enable Register (EPINTE) Bit Field HW SW DF 0 INT0RXE R R/W 0 EP0 USB RX Event Enable 1 INT0TXE R R/W 0 EP0 USB TX Event Enable 2 INT0INE R R/W 0 EP0 USB IN Token Event Enable 3 INT1E R R/W 0 EP1 interrupt Enable 4 INT2E R R/W 0 EP2 interrupt Enable 5 INT3E R R/W 0 EP3 interrupt Enable 6 Reserved 7 Reserved 9.5.5 Bit Description State Interrupt Event Register (STAINTR) Field HW SW DF Description USB Bus Reset Event Detect 0 RSTINT R/W R/W0C 0 Set by HW when reset signal is detected on the USB bus. After a USB bus reset, all registers return to their default value and the USB device will be in the default state. When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. USB Bus Suspend Detect Set by HW when the USB bus is idle every 3ms. 1 IDLEINT R/W R/W0C 0 When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. USB Bus Resume Detect Set by HW when resume signal is detected. 2 RUEINT R/W R/W0C 0 When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. H/W write operation has a higher priority if H/W write and S/W write occur at the same time. 7-3 9.5.6 76 • Reserved State Interrupt Event Enable Register (STAINTE) Bit Field HW SW DF Description 0 RSTINTE R R/W 0 Enable USB Bus Reset Event Detect 1 IDLEINTE R R/W 0 Enable USB Bus Suspend 3ms Detect 2 RUEINTE R R/W 0 Enable USB Bus Resume Detect 7-3 Reserved Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 9.5.7 Function Address Register (FAR) Bit Field HW SW DF 6-0 ADDR R R/W 0 7 Reserved 9.5.8 Bit 0 1 Field OUT SETUP SETUPOW 7-3 Reserved Bit 0 1 USB Device Address Endpoint 0 RX Token Register (EP0RXTR) 2 9.5.9 Description HW SW DF Description 0 RX OUT Token Set by HW to indicate OUT token is received and transaction ends with ACK or STALL. When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. 0 RX SETUP Token Set by HW to indicate SETUP token is received and transaction ends with ACK. When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. 0 SETUP Overwrite Set by HW to indicate SETUP token is received when RX FIFO is not empty (regardless whether it is ended with error or ACK). When S/W writes a 0, it will clear this bit, when 1 is written, no change occurs. R/W R/W0C R/W R/W0C R/W R/W0C Endpoint 0 RX Command/Status Register (EP0RXCSR) Field RXEN SESTALL HW SW R/W0C R/W R/W R/W Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) DF Description 1 RX Enable Set by SW to enable rx USB data. USB data will be written to FIFO and ACK will be returned if the bit “SESTALL” is not set. Clear by HW to indicate transaction ends with ACK or STALL. If this bit is 0,USB data will be discarded and NAK will be returned. SETUP packets will be written to FIFO even this bit is not set and ACK will be returned always. This register will be reset by USB reset or SW reset. 1 Send STALL If set, STALL will be returned to the OUT transaction. SW is allowed to set or clear this bit. HW clears this bit when SETUP transaction ends with ACK. HW sets this bit when STALL is returned to any EP0 transaction. • 77 EM77930 USB+BB Controller Bit Field HW SW DF 2 DTOG R/W R 0 Description Data Toggle Bit Updated by HW to indicate the data toggle bit for current USB transaction. Data Toggle Error 3 DTOGERR R/W R 0 Set by HW to indicate toggle error occurs. Cleared when SW writes a 0 to clear the EP0 RX event interrupt status. ACK Status 4 ACKSTS R/W R 0 Set by HW when a transaction is completed with ACK handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). STALL Status 5 STALLSTS R/W R 0 Set by HW when a transaction is completed with STALL handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). Error Status 6 ERRSTS R/W R 0 7 CDTOG R/W0C W 0 Set by HW to indicate either USB PID error, CRC error, bit stuffing error or no data phase from USB host occur. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL) or when SETUPOW (EP0RXTR Register) is set. Clear Endpoint Toggle. When SW writes a 1 to this bit, it will clear the DTOG bit which is in the same register. 9.5.10 Endpoint 0 TX Command/Status Register (EP0TXCSR) Bit Field HW SW DF Description TX Enable 0 1 78 • TXEN SESTALL R/W0C R/W R/W R/W 0 1 Set by SW to enable Tx USB data. USB data Is ready in the FIFO and will be sent to USB bus if the bit “SESTALL” is not set. SW should write data then byte count the enabled Tx. Cleared by HW in two cases: Indicate IN transaction ends with ACK or STALL.. After SETUP transaction ends with ACK. This register will be reset by USB reset or SW reset. Send STALL If set, STALL will be returned to the IN transaction. SW is allowed to set or clear this bit. HW clears this bit when SETUP transaction ends with ACK. HW sets this bit when STALL is returned to any EP0 transaction. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller Bit Field HW SW DF 2 DTOG R/W R 1 3 Reserved Description Data Toggle Bit Updated by HW to indicate the data toggle bit for current USB transaction. ACK Status 4 ACKSTS R/W R 0 Set by HW when a transaction is completed with ACK handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). STALL Status 5 STALLSTS R/W R 0 Set by HW when a transaction is completed with STALL handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). Error Status 6 ERRSTS R/W R 0 7 CDTOG R/W0C W 0 Set by HW to indicate either USB PID error, CRC error, bit stuffing error or no data phase from USB host occur. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL) or when SETUPOW (EP0RXTR Register) is set. Clear endpoint Toggle. When SW writes a 1 to this bit, it will clear the DTOG bit which is in the same register. 9.5.11 Endpoint 0 RX Count Register (EP0RXCTR) Bit Field 0-6 EP0RXCT 7 Reserved HW R/W SW R DF Description 0 RX Byte Count When receive enable is set to 1, this field specifies the receive byte counts in the receive FIFO. This register will be reset by USB reset or SW reset. 9.5.12 Endpoint 0 TX Count Register (EP0TXCTR) Bit Field 0-6 EP0TXCT 7 Reserved HW R SW R/W Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) DF Description 0 TX Byte Count When transmit enable is set to 1, this field specifies the transmit byte counts in the transmit FIFO. HW always accesses the FIFO from address0. This register will be reset by USB reset or SW reset. • 79 EM77930 USB+BB Controller 9.5.13 Endpoint 0 RX Data Register (EP0RXDAR) Bit Field HW SW DF 0-7 DATA R/W R 0 Description RX Data Receive FIFO data will be read by SW through read this register. 9.5.14 Endpoint 0 TX Data Register (EP0TXDAR) Bit Field HW SW DF 0-7 DATA R W 0 Description TX Data SW writes data to this register will be written to transmit FIFO. 9.5.15 Endpoint n Command/Status Register (EPnCSR) Endpoint 1 command/status Register (EP1CSR) Endpoint 2 command/status Register (EP2CSR) Endpoint 3 command/status Register (EP3CSR) Bit 0 1 2 80 • Field RXTXEN SESTALL DTOG HW SW R/W0C R/W R/W R/W R/W R DF Description 0 RX Enable (Interrupt Out / Bulk Out / Isochronous Out) Set by SW to enable rx USB data. USB data will be written to FIFO and ACK will be returned if the bit “SESTALL” is not set. Cleared by HW to indicate transaction ends with ACK or STALL. If this bit is 0, the USB data will be discarded and NAK will be returned. TX Enable (Interrupt In/Bulk In /Isochronous IN) Set by SW to enable Tx USB data. USB data is ready in the FIFO and will be sent to the USB bus if the bit “SESTALL” is not set. SW should write data then byte count the enabled Tx. Cleared by HW when the IN transaction ends with ACK or STALL. If the transaction ends with ACK, the following USB transaction will be returned with NAK if the bit “SESTALL” is not set. The register will be reset by USB reset or SW reset. 1 Send STALL If set, STALL will be returned for the transaction. SW is allowed to set or clear this bit. Reserved (Isochronous IN or Isochronous OUT) 0 Data Toggle Bit (Interrupt IN / Interrupt OUT / Bulk IN / Bulk OUT) Updated by HW to indicate the data toggle bit for current USB transaction. Reserved (Isochronous IN or Isochronous OUT) Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller Bit Field HW SW DF Description Data Toggle Error (Interrupt OUT / Bulk OUT) 3 DTOGERR R/W R 0 Reserved (Interrupt In / Bulk In / Isochronous IN / Isochronous OUT) Set by HW to indicate toggle error occurs. Cleared when SW writes a 0 to clear the EPn OUT event interrupt status. ACK Status 4 ACKSTS R/W R 0 Set by HW when a transaction is completed with ACK handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). STALL Status 5 STALLSTS R/W R 0 Set by HW when a transaction is completed with STALL handshake. This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). Error Status 6 ERRSTS R/W R 0 Set by HW to indicate either USB PID error, CRC error, bit stuffing error, time out without handshake response from USB host (for IN transaction) or no data phase from USB host occur (OUT transaction). This bit will be updated automatically at the next valid transaction (ends with ACK or STALL). Clear endpoint Toggle. 7 CDTOG R/W0C W 0 When SW writes 1 to this bit, it will clear the DTOG bit which is in the same register. Reserved (Isochronous IN or Isochronous OUT) The following table lists the meaning of the Endpoint n command/status Register (EPnCSR) for different Endpoint-Type. Bit Interrupt IN Interrupt OUT 0 RXTXEN RXTXEN (TX Enable) (RX Enable) Bulk IN Bulk OUT Isochronous Isochronous IN OUT RXTXEN RXTXEN RXTXEN RXTXEN (TX Enable) (RX Enable) (TX Enable) (RX Enable) 1 SESTALL SESTALL SESTALL SESTALL Reserved Reserved 2 DTOG DTOG DTOG DTOG Reserved Reserved 3 Reserved DTOGERR Reserved DTOGERR Reserved Reserved 4 ACKSTS ACKSTS ACKSTS ACKSTS ACKSTS ACKSTS 5 STALLSTS STALLSTS STALLSTS STALLSTS STALLSTS STALLSTS 6 ERRSTS ERRSTS ERRSTS ERRSTS ERRSTS ERRSTS 7 CDTOG CDTOG CDTOG CDTOG Reserved Reserved Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 81 EM77930 USB+BB Controller 9.5.16 Endpoint n Count Register (EPnCTR) Endpoint 1 count Register (EP1CTR) Endpoint 2 count Register (EP2CTR) Endpoint 3 count Register (EP3CTR) Bit Field 0-7 EPnCT 7 Reserved HW SW R/W R/W DF Description 0 RX Byte Count (Bulk Out / Isochronous Out) When receive enable is set to 1, this field specifies the receive byte counts in the receive FIFO. TX Byte Count (Interrupt In / Bulk In / Isochronous In) When transmit enable is set to 1, this field specifies the transmit byte counts in the transmit FIFO. HW always accesses the FIFO from Address 0. This register will be reset by USB reset or SW reset. 9.5.17 Endpoint n Data Register (EPnDAR) Endpoint 1 Data Register (EP1DAR) Endpoint 2 Data Register (EP2DAR) Endpoint 3 Data Register (EP3DAR) Bit 0-7 Field DATA HW SW DF R or W R/W Description RX Data (Bulk Out / Isochronous Out) Receive FIFO data will be read by SW through reading this register. TX Data (Interrupt In / Bulk In / Isochronous In) SW writes data to this register will be written to transmit FIFO. 0 9.5.18 USB Device SOF Event Register (HINTR) Bit Field 0-5 Reserved 6 SOFINT 7 Reserved HW SW R/W R/W0C DF Description 0 Start of frame interrupt. Asserted after the receipt of a valid SOF. 9.5.19 USB Device SOF Event Enable Register (HINTE) Bit Field 0-5 Reserved 6 SOFINTE 7 Reserved HW SW DF R R/W 0 Description SOF Interrupt Event Enable. 9.5.20 Frame Number Low-Byte Register (FNLR) Bit Field HW SW DF 0-7 FNLR R/W R 0 Description Bits 0~7 of Frame Number (11 bits) 9.5.21 Frame Number High-Byte Register (FNHR) 82 • Bit Field HW SW DF 0-2 FNHR R/W R 0 3-7 Reserved Description Bits 8~10 of Frame Number (11 bits) Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 10 Pulse Width Modulation (PWM) 10.1 Overview The EM77930 has one PWM output with 16-bit resolution. Fig. 10-1 shows the functional block diagram. A PWM output has a period and a duty cycle, and it keeps the output high. The baud rate of the PWM is the inverse of the period. Fig. 10-2 depicts the relationships between a period and a duty cycle. DT0H PWM0IF DT0L DL0H Set as compare match PWM0E S_PWM0 Duty Compare Circuit PWM0IE Data Bus Q PWM0 DL0L R TMR0HB S Set as compare match TMR0LB Period Compare Circuit MUX PRD0H PRD0L PWM0E Fosc/2 Fig. 10-1 PWM Functional Block Diagram Period Period Duty Duty DUTY = TMR Period Duty PRD= TMR Fig. -2 PWM Output Timing Diagram Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 83 EM77930 USB+BB Controller 10.2 PWM Control Registers As the PWM mode is defined, the related registers of this operation are shown below: INTF (0x11): Interrupt flag Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - PWM0IF EINT1F EINT0F TCCOF FRCOF DT0L (0x21): Duty of PWM0 low byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DT07 DT06 DT05 DT04 DT03 DT02 DT01 DT00 DT0H (0x22): Duty of PWM0 high byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DT0F DT0E DT0D DT0C DT0B DT0A DT09 DT08 DL0L (0x25): Duty latch of PWM0 low byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DL07 DL06 DL05 DL04 DL03 DL02 DL01 DL00 DL0H (0x26): Duty latch of PWM0 high byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DL0F DL0E DL0D DL0C DL0B DL0A DL09 DL08 The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX to DLX while TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared. DTX can be loaded at any time. However, it cannot be latched into DLX until the current value of DLX is equal to TMRX. The following formula describes how to calculate the PWM duty cycle: Duty Cycle = (DTX+1) * (2/Fosc) PRD0L (0x23): Period of PWM0 low byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PRD07 PRD06 PRD05 PRD04 PRD03 PRD02 PRD01 PRD00 PRD0H (0x24): Period of PWM0 high byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PRD0F PRD0E PRD0D PRD0C PRD0B PRD0A PRD09 PRD08 The PWM period is defined by writing to PRDX. When TMRX is equal to PRDX, the following events occur on the next increment cycle: 84 • TMRX is cleared The PWMX pin is set to 1. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller The PWMX duty cycle is latched from DTPS to DUTY. NOTE The PWMX will not be set if the duty cycle is 0. The PWMXIF pin is set to 1. The following formula describes how to calculate the PWM period: PERIOD = (PRD +2) * (2/Fosc) The PWM function must be disabled before a new period is executed. In other words, bit PWMXE has to be reset in advance, if the contents of PRDX are reloaded. PRIE (0x80): Peripherals enable control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - USBE BBE - - PWM0E TCCE FRCE INTE (0x81): Interrupt enable control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE - - PWM0IE EINT1E EINT0E TCCOE FRCOE PWMCR (0x98): PWM control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - S_PWM0 - - 10.3 PWM Programming Procedures/Steps (1) Load PRDX with the PWMX period. (2) Load DTX with the PWMX Duty Cycle. (3) Enable interrupt function by setting PWMXIE in the INTE register, if required. (4) Set the PWM pin as output by setting PWMCR.S_PWMX. (5) Enable the PWM function by setting the PWMXE bit in the PRIE register. (6) Write the desired new duty to DTX before TMRX is equal to PRDX, then this new DTX will be latched into DLX if various duty cycle is required for next the PWMX operation. (7) Clear the PWMXE bit and write the desired new period to PRDX, then enable it again if various periods are required for the next PWMX operation. (8) Clear the PWMXIF before the next operation if interrupt PWMXIE is employed. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 85 EM77930 USB+BB Controller 11 Interrupts 11.1 Introduction The EM77930 has 17 interrupt sources. By priority, these interrupts are classified into three levels, namely; peripherals, baseband, and USB, and described as following: The interrupt status registers record the interrupt requests in the corresponding control bits in the interrupt control registers. The global interrupt (GIE) is enabled by the ENI instruction and is disabled by the DISI instruction. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine to avoid recursive interrupts. The flags in the Interrupt Status Register are set regardless of the status of their corresponding mask bits or the execution of DISI. Note that the logic AND of an interrupt flag and its corresponding interrupt control bit is 1 which makes the program counter point to the right interrupt vector. Refer to Fig. 11. The RETI instruction ends the interrupt routine and enables the global interrupt (the execution of ENI). Before the interrupt subroutine is executed, the contents of ACC, SR, RAMBS0 and ROMPS will be saved by the hardware. After the interrupt service routine is finished, ACC, SR, RAMBS0 and ROMPS will be pushed back. In the EM77930, individual interrupt sources have their own interrupt vectors, depicted in the following table: Mnemonic No Mask KWUAIF KWUBE KWUBIF EINT0E EINT0F EINT1E EINT1F 3 FRCOE Mask Status Register Bit Register Bit 0x82 3~0 0x12 3~0 0x83 All 013 All 1 0x10 Key Wake Up 1 0x18 External Interrupt 0x81 FRCOF 1 0x20 FRC Overflow 0x81 0 0x11 0 4 TCCOE TCCOF 1 0x28 TCC Overflow 0x81 1 0x11 1 5 PWM0IE PWM0IF 1 0x40 PWM period complete 0x81 4 0x11 4 6 CSDE CSDF 2 0x48 Carrier sense interrupt 0x99 7 0x30 7 7 TX_AEE TX_AEF 2 0x50 TX FIFO almost empty 0x99 6 0x30 6 8 RX_AFE RX_AFF 2 0x58 RX FIFO almost full 0x99 5 0x30 5 9 TX_EMPTY TX_EMPTYF 2 0x60 TX FIFO empty 0x99 4 0x30 4 10 RX_OFE RX_OFF 2 0x68 RX FIFO overflow 0x99 3 0x30 3 11 LINK_DIS LINK_DIS 2 0x70 LINK_DIS interrupt 0x99 2 0x30 2 2 86 • Function Status KWUAE 1 Priority Vector 2 3 0x11 2 3 Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller Mnemonic No Mask Priority Vector Function Status Mask Status Register Bit Register Bit 12 LOCK_OUTE LOCK_OUTF 2 0x78 Lock out interrupt 0x99 1 0x30 1 13 LOCK_INE LOCK_INF 2 0x80 Lock in interrupt 0x99 0 0x30 0 14 INT0RXE INT0RXF 3 EP0 USB RX Event 0x1D2 0 0x1D1 0 14 INT0TXE INT0TXF 3 EP0 USB TX Event 0x1D2 1 0x1D1 1 14 INT0INE INT0INF 3 EP0 USB IN Token Event 0x1D2 2 0x1D1 2 15 INT1E INT1F 3 EP1 Interrupt 0x1D2 3 0x1D1 3 15 INT2E INT2F 3 0x90 EP2 Interrupt 0x1D2 4 0x1D1 4 15 INT3E INT3F 3 EP3 Interrupt 0x1D2 5 0x1D1 5 16 RSTINTE RSTINTF 3 USB Bus Reset Event Detect 0x1D4 0 0x1D3 0 16 IDLEINTE IDLEINTF 3 USB Bus Suspend Event Detect 0x1D4 1 0x1D3 1 16 RUEINTE RUEINTF 3 0x98 USB Bus Resume Event Detect 0x1D4 2 0x1D3 2 Function Remote Wake-Up Interrupt 0x1D4 3 0x1D3 3 Start Of Frame Interrupt 0x1E8 6 0x1E7 6 16 FRWPINTE FRWPINTF 3 17 SOFINTE 3 SOFINTF 0x88 0XA8 The interrupt priority is another useful feature provided by this IC. The latest interrupt, which has the highest priority than the others, will override and hold the currently executed interrupt until the interrupt is finished. Otherwise, the latest interrupt will be in queue right after all its peers. Global INT Enable Function INT Enable Function INT Condition Occured Function Enable Function INT Vector Address Function INT Flag Fig. 11 Block Diagram of Interrupts Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 87 EM77930 USB+BB Controller 12 Circuitry of Input and Output Pins 12.1 Introduction The EM77930 has five parallel ports, namely: Port A, Port B, Port C, Port D and Port F which only two least significant bits are available. That is, there are 30 available I/O pins. A control bit defines the configuration of its corresponding pin. Refer to Fig. 3-1 for the Pin Assignment. The I/O registers, from Port A to Port F, are bidirectional tri-state I/O ports. The I/O ports can be defined as "input" or "output" pins by the I/O control registers (IOCA, IOCB, IOCC, IOCD and IOCF) under program control. The I/O registers and I/O control registers are both readable and writable. Note that the source is different between the reading path of input and output pin while reading the I/O port. 13 Timer/Counter System 13.1 Introduction The EM77930 provides two timer modules: 8-bit TCC (Timer Clock/Counter), and 16-bit FRC (Free Run Counter). The TCC clock source comes from one of the instruction cycle and low frequency oscillator (IRC). The FRC clock source is from either instruction cycle or low frequency oscillator (IRC). 13.2 Time Clock Counter (TCC) An 8-bit counter is available as prescaler for the TCC. The prescaler ratio is determined by the PS0~PS2 bits. When in TCC mode, the prescaler is cleared each time an instruction writes to the TCC. TCC is an 8-bit timer/counter. If the TCC signal source is from the system clock, TCC will be incremented by 1 in every instruction cycle (without prescaler). If the TCC signal source is from the IRC clock input, the TCC will be incremented by 1 on every falling edge or rising edge of the TCC pin. The prescaler counter (PRC) can be read from Address 0x0F. In other words, the combination of TCC and PRC can be used as a 16-bit counter without prescaler. 88 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 13.2.1 Block Diagram of TCC TCCS0 Fosc 0 M U X ERC Data Bus TCCE Sync with Internal Clock PRC (8- bit Counter) 1 TCC 2 clocks delay TCCOF PS0 PS1 PS2 8-1 MUX Fig. 13-1 Function Block Diagram of TCC 13.2.2 TCC Control Registers As the TCC mode is defined, the related registers involved in this operation are shown below: PRC (0x0F): Prescaler counter TCC (0x10): Timer clock/counter INTF (0x11): Interrupt flag Bit 7 Bit 76 Bit 75 Bit 74 Bit 73 Bit 72 Bit 71 Bit 70 - - - PWM0IF EINT1F EINT0F TCCOF FRCOF PRIE (0x80): Peripherals enable control Bit 7 Bit 76 Bit 75 Bit 74 Bit 73 Bit 72 Bit 71 Bit 70 - USBE BBE - - PWM0E TCCE FRCE INTE (0x81): Interrupt enable control Bit 7 Bit 76 Bit 75 Bit 74 Bit 73 Bit 72 Bit 71 Bit 70 GIE - - PWM0IE EINT1E EINT0E TCCOE FRCOE TCCC (0x93): Timer clock/counter control Bit 7 Bit 76 Bit 75 Bit 74 Bit 73 Bit 72 Bit 71 Bit 70 - - - - TCCS0 PS2 PS1 PS0 Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 89 EM77930 USB+BB Controller 13.2.3 TCC Programming Procedures/Steps (1) Load TCCC with the prescaler and TCC clock source. (2) Load the TCC with the TCC overflow period. (3) Enable the interrupt function by setting TCCOE in the INTE register, if required. (4) Enable the TCC function by setting the TCCE bit in the PRIE register. (5) Wait for either the interrupt flag to be set (TCCOF) or the TCC interrupt to occur. (6) The following formula describes how to calculate the TCC overflow period: 1 ⎛ ⎞ TCC Timer = (0 × 100 − TCC ) × Pr escaler ⎜ ⎟ ⎝ ClockSource ⎠ where Clock Source = Fosc or IRC 13.3 Free Run Counter Dual 8-bit counters, high byte register and low byte register, make up the 16-bit software programmable counter. The driving clock source is either the system clock divided by 2 or the low frequency oscillator. A read of the low byte register allows full control of the corresponding timer function. On the contrary, accessing a high byte register will inhibit the specific timer function until the corresponding low byte is read as well. 13.3.1 Block Diagram of FRC FRCE FRCCS Fosc 0 M U X ERC Sync with Internal Clock LFRF HFRC FRCOF 1 LFRFB Data Bus Fig. 13-2 Timer 1 Function Block Diagram 90 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 13.3.2 FRC Control Registers As the FRC mode is defined, the related registers involved in this operation are shown below: INTF (0x11): Interrupt flag. Bit 7 Bit 76 Bit 75 Bit 74 Bit 73 Bit 72 Bit 71 Bit 70 - - - PWM0IF EINT1F EINT0F TCCOF FRCOF LFRC (0x1A): Least significant byte of 16-bit free run counter. HFRC (0x1B): Most significant byte of 16-bit free run counter. LFRCB (0x1C): Least significant byte buffer of 16-bit free run counter. PRIE (0x80): Peripherals enable control Bit 7 Bit 76 Bit 75 Bit 74 Bit 73 Bit 72 Bit 71 Bit 70 - USBE BBE - - PWM0E TCCE FRCE INTE (0x81): Interrupt enable control Bit 7 Bit 76 Bit 75 Bit 74 Bit 73 Bit 72 Bit 71 Bit 70 GIE - - PWM0IE EINT1E EINT0E TCCOE FRCOE FRCC (0x94): Free run counter control. Bit 7 - Bit 76 Bit 75 Bit 74 Bit 73 OCSO2E OSCO2SL1 OSCO2SL0 PPSCL2 Bit 72 Bit 71 Bit 70 PPSCL1 PPSCL0 FRCCS 13.3.3 FRC Programming Procedures/Steps (1) Load the LFRCB with the FRC overflow period low byte. (2) Load the HFRC with the TCC overflow period high byte. Then the LFRC will automatically load with the LFRCB. (3) Enable the interrupt function by setting FRCOE in the INTE register, if required. (4) Enable FRC function by setting the FRCE bit in the PRIE register. (5) Wait for either the interrupt flag to be set (FRCOF) or the FRC interrupt to occur. (6) A low byte access on the 16-bit counter receives the count value at the instance of reading. However, the low byte contents will be transferred to the buffer, the LFRCB register, if a high byte is read first. The value in the LFRCB register remains unchanged until the corresponding low byte is read. (7) The following formula describes how to calculate the FRC overflow period: 1 ⎛ ⎞ FRC Timer = (0 ×100 − HFRC : LFRC )× ⎜ ⎟ ⎝ ClockSource ⎠ where Clock Source = Fosc or IRC Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 91 EM77930 USB+BB Controller 14 Reset and Wake Up 14.1 Reset The reset can be caused by one of the following: (1) Power-on reset (2) /RESET pin input "low", or (3) Watchdog timer time-out (if enabled) The device will remain in a reset condition for a period of 8-bit internal RC ripple counter (one oscillator start-up timer period) after the reset is detected. The initial Address is 000h. 14.2 The Status of RST, T, and P of STATUS Register A reset condition can be caused by the following events: (1) A power-on condition (external); (2) A high-low-high pulse on the /RESET pin (external); and (3) Watchdog timer time-out (internal). The values of bits RST, T and P, listed in Table 14.1 can be used to check how the processor wakes up. Table 14.1 Values of RST, T and P after a reset Condition RST T P Power on 0 1 1 WDTC instruction *P 1 *P WDT timeout *P 0 *P SLEP instruction *P *P 0 Wake-Up on pin change during Sleep mode 1 1 0 *P: Previous status before reset 14.3 System Set-up (SSU) Time In order to have a successful start up, System Set-up Time (SSU) is employed to guarantee a stable clock for IC operation. It is made up of two delay sources: (1) Internal RC Oscillation Set-up Delay (IRCOSUD): Internal RC oscillation shared with a watchdog timer divided by a 6-bit ripple counter. The RC delay controlled by bit IRCDE in the Code Option is optional. (2) Main Oscillation Set-up Delay (MOSUD): A 10-bit ripple counter is used to filter unstable main clocks at the beginning of power-on before the chip starts to run. This delay is performed right after IRCOSUD, if enabled. 92 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller OSC1 10-bit Ripple Counter 6-bit Ripple Counter SSU Internal RC Osc . RCSUTE Fig. 13 System Set-up Time 14.4 Wake-up Procedure on Power-on Reset Power-on Voltage Detector (POVD) will allow the VDD whose value is over the default threshold voltage (2.0 V for the EM77930) enter the IC, and the SSU delay starts. The following three cases may be taken into consideration: (1) /RESET pin goes high with VDD at the same time. In hardware, this pin and VDD are tied together. The internal reset will remain low until the SSU delay is over. (2) /RESET pin goes high during the SSU delay. It is similar to Case 1. The IC will start to operate as the SSU delay is over. /RESET pin goes high after the SSU delay. The EM77930 will start program execution immediately. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 93 EM77930 USB+BB Controller 15 Oscillators 15.1 Introduction The EM77930 provides three main oscillators: One high frequency crystal oscillator (connected to OSCI), internal RC, and four PLL (Phase Lock Loop) Outputs. Versatile combinations of oscillation are provided for wild applications. On-chip clock sources can be either dual clocks or single clock. 15.2 Clock Signal Distribution RF-BB USB 16 bit PWM BYP SYS_CLK 0/1=0 & RF_CLK 0/1=0 & USB_CLK=0 BYP 6 MHz PLL PD (Power Down) RF_CLK 0/1 SR.GREEN 6 12 24 48 SYS_NCLK MCU Kernel SYS_CLK 0/1 IRC CLK SYS_ICLK TCCC.TCCS0 WDT 8 bit TCC FRCC.FRCCS 16 bit FRC Fig. 14 Clock Tours 15.3 PLL Oscillator The Phase-locked loop (PLL) technology is employed to produce four different frequencies: 6 MHz, 12MHz, 24MHz and 48 MHz (external 6MHz crystal). 6 MHz is the system clock source and 48 MHz is USB device and Hub clock source only. PLL is enabled except when entering Green and Sleep mode. 94 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 16 Low-Power Mode 16.1 Introduction The EM77930 has two power-saving modes, green mode and sleep mode. Figure 16 shows the mode change diagram. Power On Normal WDTC[7].Green=0 SLEP INST. 1. Key Wake-up 2. WDT Time out 3. /Reset 1. WDTC[7].Green=1 2. WDT Time out 3. /Reset Key Wake up Green Sleep SLEP INST. Fig. 16 Three Mode State 16.2 Green Mode The “GREEN” bit of WDTC [7] register is the only control bit used for mode switching, between normal mode and green mode. Its initial value is “0”, normal mode. When “GREEN” bit is written with a 1, the MCU will switch to green mode from normal mode. In contrast, the MCU will go back to normal mode when the “GREEN” bit is written from 1 to 0. During green mode, the main oscillator will be turned off. The MCU and all the peripherals are driven by the external RC oscillator - IRC. Once RF peripheral is functional and then switched into green mode, the clock source for all the other peripherals, except PLL, will be provided by IRC. PLL will keep running as RF circuit’s clock source. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 95 EM77930 USB+BB Controller 16.3 Sleep Mode The execution of “SLEP” instruction will turn the whole chip into Sleep mode. The main clock will be shut down. The IRC oscillator is halted also if the watchdog function is disabled. All registers, memory and I/O port remain in their previous states during sleep mode. The overflow of the watchdog timer driven by IRC will generate a reset to resume normal operation. Key Wake up (KWU) interrupt and /RESET pin are other methods to exit sleep mode. It is essential to wait for stable Oscillation start up time before normal operation. The stabilizing time is SST. 17 Instruction Description 17.1 Instruction Set Summary Type Instruction Binary Mnemonic 96 • Status Affected Cycles 0000 0000 0000 0000 NOP No operation None 1 0000 0000 0000 0001 WDTC WDT ← 0 None 1 0000 0000 0000 0010 RET PC ← (Top of Stack) None 1 None 1 None 1 PC ← (Top of Stack); 0000 0000 0000 0011 RETI 0000 0000 0000 0100 SLEP 0000 0000 0000 0101 ENI Enable Interrupt None 1 0000 0000 0000 0110 DISI Disable Interrupt None 1 0000 0000 0000 0111 DAA Decimal Adjust A C 1 1010 0000 rrrr rrrr TBRDP r None 2 1010 0001 rrrr rrrr TBRD r None 2 1010 0010 rrrr rrrr TBRDM r None 2 0000 0000 0000 1010 TBRDP A None 2 0000 0000 0000 1011 TBRD A None 2 0000 0000 0000 1100 TBRDM A None 2 0011 1101 0000 0010 TBL C, DC, Z 1 1010 1011 kkkk kkkk RETL #k None 1 Enable Interrupt System Control Table Look up Operation WDT ← 0 Stop oscillator r ← ROM[(TABPT[15:1])] TABPT ← TABPT+1 r ← ROM[(TABPT[15:1])] r ← ROM[(TABPT[15:1])] TABPT ← TABPT-1 A ← ROM[(TABPT[15:1])] TABPT ← TABPT+1 A ← ROM[(TABPT[15:1])] A ← ROM[(TABPT[15:1])] TABPT ← TABPT-1 R2 ← R2+A A←k PC ← [Top of Stack] Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller Type Logic Compare Branch Instruction Binary Mnemonic Operation Status Affected Cycles 0000 0001 rrrr rrrr OR A, r A ← A .or. r Z 1 0000 0010 rrrr rrrr OR r, A r ← r .or. A Z 1 0000 0011 kkkk kkkk OR A, #k A ← A .or. k Z 1 0000 0100 Rrrr rrrr AND A, r A ← A .and. r Z 1 0000 0101 Rrrr rrrr AND r, A r ← r .and. A Z 1 0000 0110 kkkk kkkk AND A, #k A ← A .and. k Z 1 0000 0111 Rrrr rrrr XOR A, r A ← A .xor. r Z 1 0000 1000 rrrr rrrr XOR r, A r ← r .xor. A Z 1 0000 1001 A ← A .xor. k Z 1 0000 1010 rrrr rrrr COMA r A ← /r Z 1 0000 1011 rrrr rrrr COM r r ← /r Z 1 1011 00kk rrrr rrrr RRCA r, #k [C,r] rotate right k bits to [C,A] C 1 1011 01kk rrrr rrrr RRC r, #k [C,r] rotate right k bits to [C,r] C 1 1011 10kk rrrr rrrr RLCA r, #k [C,r] rotate left k bits to [C,A] C 1 1011 11kk rrrr rrrr RLC r, #k [C,r] rotate left k bits to [C,r] C 1 0101 10kk rrrr rrrr SHRA r, #k None 1 0101 11kk rrrr rrrr SHLA r, #k None 1 0001 0bbb rrrr rrrr xxaa aaaa If r(b)=0, jump to addr None 2/3* 0001 1bbb rrrr rrrr xxaa aaaa JBS aaaa aaaa r,b,addr If r(b)=1, jump to addr None 2/3* 0101 0010 xxaa aaaa rrrr rrrr DJZA aaaa aaaa r,addr A ←r-1, jump to addr if zero None 2/3* 0101 0011 xxaa aaaa DJZ r,addr r ←r-1, jump to addr if zero None 2/3* 0101 0100 xxaa aaaa JZA r,addr A←r+1, jump to addr if zero None 2/3* 0101 0101 xxaa aaaa JZ r,addr r ←r+1, jump to addr if zero None 2/3* kkkk kkkk XOR A, #k JBC aaaa aaaa r,b,addr rrrr rrrr aaaa aaaa rrrr rrrr aaaa aaaa rrrr rrrr aaaa aaaa [C,r] shift right k bits to A Insert C into high order bits [C,r] shift left k bits to A Insert C into low order bits Note: *Condition for successful instruction execution needs 2/3 cycles (jump to address). Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 97 EM77930 USB+BB Controller Type Process Arithmetic Move Instruction Binary Mnemonic Operation Status Affected Cycles 0010 0bbb rrrr rrrr BC r,b r(b) ← 0 None 1 0010 1bbb rrrr rrrr BS r,b r(b) ← 1 None 1 0011 0bbb rrrr rrrr BTG r,b r(b) ← /r(b) None 1 0011 1000 rrrr rrrr SWAP r r(0:3) ↔ r(4:7) None 1 0011 1001 rrrr rrrr SWAPA r None 1 1010 1100 rrrr rrrr ZCHK r Z 1 0000 0000 0000 1101 None 1 1010 1111 rrrr rrrr CLR r r←0 Z 1 0011 1100 rrrr rrrr ADD A,r A ← A+r C, DC, Z 1 0011 0011 0100 0100 0100 0100 0100 0101 0101 1101 1110 0010 0011 0100 1110 1111 0000 0001 rrrr kkkk rrrr rrrr kkkk rrrr rrrr rrrr rrrr rrrr kkkk rrrr rrrr kkkk rrrr rrrr rrrr rrrr ADD r,A ADD A,#k SUB A,r SUB r,A SUB A,#k INCA r INC r DECA r DEC r r ← r+A A ← A+k A ← r-A f ← r-A A ← k-A A ← r+1 r ← r+1 A ← r-1 r ← r-1 C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z 1 1 1 1 1 1 1 1 1 1010 1000 rrrr rrrr MOV A,r A←r Z 1 1010 1001 rrrr rrrr MOV r,A r ←A None 1 None 1 None 1 None 1 None 1 0110 RPT A(4:7) ← r(0:3) A(0:3) ← r(4:7) Z ← 0 if r < > 0 Single repeat CS times on next TBRD instruction r2 r2 r2 r2 r2 r2 r1 r1 r1 r1 r1 r1 MOVRR r1, r2 Register r1 ← Register r2 1010 0111 kkkk kkkk MOV A,#k 110a aaaa aaaa aaaa JMP addr A←k PC ← addr PC[13..16] unchange [Top of Stack] ← PC + 1 Branch 111a aaaa aaaa aaaa CALL addr PC ← addr PC [13..16] unchange Bank 1010 1110 0000 0kkk BANK #k R4(RAMBS0) ← k (0~6) None 1 Page 1010 1101 0000 000k PAGE #k R5(PAGES) ← k (0~1) None 1 98 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 18 Electrical Specification 18.1 Absolute Maximum Ratings Temperature Under Bias 0°C to 70°C Storage temperature Input voltage -65°C to 150°C -0.3V to +3.6V Output voltage -0.3V to +3.6V 18.2 DC Electrical Characteristic Ta=0°C ~ 70 °C, VDD=3.3V±5%, VSS=0V Symbol Parameter Condition Min Typ Max Unit DC − 48.0 MHz − − ±2 μA Port A ~ Port F 0.8xVDD − − V Port A ~ Port F VSS − 0.2xVSS V Input High Threshold /RST Voltage 2.0 − − V VILT Input Low Threshold /RST Voltage − − 0.8 V VIHX Clock Input High Voltage OSCI, OSCO 2.5 − − V VILX Clock Input Low Voltage OSCI, OSCO − − 1.0 V Output High Voltage: VOH1 PTA, PTC, PTD, IOH = -8.0 mA PTE, PTF 2.4 − − V Output High Voltage: VOH2 PTB; IOH = -8.0 mA RFIO 2.4 − − V Fxt Crystal: VDD ~ 2.75V One cycle with one clock IIL Input Leakage VIN = VDD, VSS Current for input pins VIH Input High Voltage VIL Input Low Voltage VIHT VOL1 Output Low Voltage: IOL = 8.0 mA PTA, PTC, PTD, PTE, PTF − − 0.4 V VOL2 Output Low Voltage: IOL = 8.0 mA (1) PTB; RFIO − − 0.4 V IPH Pull-high current − -6.5 − μA ISB All input and I/O pins at VDD, Power down current Output pin floating, WDT and all peripherals disabled. − − − μA ICC1 Operating supply current (VDD = 3.3V) /RESET = 'High', Fosc = 32kHz (RC type), Output pin floating, WDT and all peripherals disabled. − 10 − μA ICC3 Operating supply current (VDD = 3.3V) /RESET= 'High', Fosc = 6MHz (Crystal type), Output pin floating, and all peripherals disabled. − 6 − mA Pull-high active, input pin at VSS Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 99 EM77930 USB+BB Controller 18.3 Voltage Detector Electrical Characteristic Ta=25°C Symbol Parameter Condition Min Typ Max Unit Vdet Detect voltage − 1.8 2.0 2.2 V Vrel Release voltage − − Vdet × 1.05 − V Iss Current consumption − − 0.8 μA Vop Operating voltage − 0.7* − 3.5 V ΔVdet/ΔTa Vdet Temperature characteristic 0°C ≤Ta≤ 70°C − − -2 MV/°C VDD = 3V * When the voltage of VDD rises between Vop=0.7V and Vdet, the voltage detector output must be "Low". 18.4 AC Electrical Characteristic 18.4.1 MCU Ta=0°C ~ 70 °C, VDD=3.3 V±5%, VSS=0V) Symbol Parameter Conditions Min Typ Max Unit Dclk Input CLK duty cycle − 45 50 55 % Tins Instruction cycle time (CLKS="0") Crystal type RC type 125 500 − DC DC ns ns Ttcc TCC input period − (Tins+20)/N* − − ns Tdrh Device reset hold time Ta = 25°C 9 18 30 ms Trst /RESET pulse width Ta = 25°C 2000 − − ns Twdt Watchdog timer period Ta = 25°C 9 18 30 ms Tset Input pin setup time − − 0 − ms Thold Input pin hold time − − 20 − ms Tdelay Output pin delay time Cload=20pF − 50 − ms * N= selected prescaler ratio. 100 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 18.4.2 BB Ta=0°C ~ 70 °C, VDD=3.3 V±5%, VSS=0V Symbol 1/tOSC Parameter Oscillator frequency Min Max Unit 0.1 24 MHz 3*tOSC+ Δ − ns tOSC − ns tRDPW RD pulse width tCSRD CS low to RD low tADRD Address valid for RD low 0 − ns tRDDV RD low to Data valid − 3*tOSC+Δ ns tRHDT Data float after RD. − tOSC ns tDHAR Data hold after RD tRHDT Time between consecutive RD pulses tRDAN Address valid after RD low 0 − ns 2*tOSC − ns 3*tOSC+Δ − ns Δ>0 will be determined according to cell library simulation. The values above were determined according to behavioral simulations. They take into account only the BB digital state-machine. Thus, such values are for reference only. Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 101 EM77930 USB+BB Controller 19 Application Circuit EM77930 Fig. 18 USB Keyboard Circuit Keyboard Setting: Port A, Port C, Port D: Key Scan Column Port B: Key Scan Row Port F.1: Scroll Lock LED Port F.2: Caps Lock LED Port F.3: Num Lock LED 102 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller 20 Pad Description Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 103 EM77930 USB+BB Controller Pad Name & Pad Coordinates Table Structure Name: EM77930 Structure Name: Chip Size：3114 X 3116 Pin No. Pad Name X Y Pin no. Pad Name X Y 1 PA1 97.1 2844.874 23 TX_RX 3016.428 283.77 2 PA2 97.1 2632.001 24 RFIO 3016.428 473.951 3 PA3 97.1 2421.65 25 PC3 3016.428 659.981 4 RST 97.1 2207.793 26 PC4 3016.428 834.832 5 PA4 97.1 1996.14 27 PLLC 3016.428 1008.099 6 PA5 97.1 1783.585 28 GND: 3016.428 1677.167 7 PA6 97.1 1574.051 28 GND: 3016.428 1849.461 8 PA7 97.1 1359.377 29 OSCI 3016.428 2062.597 9 GND: 97.1 1147.191 30 OSCO2 3016.428 2543.513 9 GND: 97.1 915.239 31 PD0 3016.428 2714.764 10 UPRT_DP 100.508 637.237 32 PD1 3016.428 2891.764 11 UPRT_DM 100.508 442.737 33 PD2 2804.123 3017.411 12 VDD_5V 433.316 97.1 34 PD3 2613.123 3017.411 13 VUSB_33V 757.53 97.1 35 PD4 2424.929 3017.411 13 VDD: 961.252 97.1 36 PD5 2243.899 3017.411 13 VDD: 1149.099 97.1 37 PD6 2072.155 3017.411 14 PB0 1348.453 97.1 38 PD7 1913.055 3017.411 15 PB1 1532.693 97.1 39 VDD: 1709.377 3017.411 16 PB2 1719.98 97.1 39 VDD: 1197.71 3017.411 17 PB3 1907.234 97.1 40 PF0 1007.255 3017.411 18 PB4 2094.063 97.1 41 PF1 834.279 3017.411 19 PB5 2282.768 97.1 42 PF2 667.244 3017.411 20 PB6 2466.56 97.1 43 PF3 479.878 3017.411 21 PB7 2656.054 97.1 44 PA0 279.011 3017.411 22 RF_ACT 2844.284 97.1 104 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) EM77930 USB+BB Controller APPENDIX A Package Type ET NO Package Type Pin Count Package Size EM77930 LQFP48 48 7X7MM B Package Information Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice) • 105 EM77930 USB+BB Controller 106 • Product Specification (V1.0) 08.20.2007 (This specification is subject to change without further notice)