EM78815 8 Bit Microcontroller Product Specification DOC. VERSION 2.4 ELAN MICROELECTRONICS CORP. February 2006 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM Windows is a trademark of Microsoft Corporation ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation Copyright © 2006 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Headquarters: Hong Kong: USA: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Elan (HK) Microelectronics Corporation, Ltd. Elan Information Technology Group (U.S.A.) Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 [email protected] 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8225 Fax: +1 408 366-8220 Europe: Shenzhen: Shanghai: Elan Microelectronics Corp. (Europe) Elan Microelectronics Shenzhen, Ltd. Elan Microelectronics Shanghai, Ltd. Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 21 5080-3866 Fax: +86 21 5080-4600 Contents Contents 1 2 3 4 5 6 7 General Description .................................................................................................. 1 Features ..................................................................................................................... 1 2.1 CPU ....................................................................................................................1 2.2 Serial Transmitter/Receiver Interface..................................................................2 2.3 Current D/A .........................................................................................................2 2.4 Programmable Tone Generators.........................................................................2 2.5 CID......................................................................................................................2 2.6 Call Waiting .........................................................................................................3 2.7 External LCD controller (64×256 dot max for a pair of Master and Slave LCD Driver) ....3 2.8 Package Type .....................................................................................................3 Application................................................................................................................. 3 Pin Configuration ...................................................................................................... 4 Functional Block Diagram........................................................................................ 6 Pin Descriptions........................................................................................................ 7 6.1 Power Pin............................................................................................................7 6.2 Clock Pin.............................................................................................................7 6.3 External LCD Device Control Pin........................................................................7 6.4 FSK, CW .............................................................................................................7 6.5 DTMF Receiver, OP............................................................................................8 6.6 Serial IO, Comparator, Current DA, Tone............................................................8 6.7 IO ........................................................................................................................8 6.8 Expand Program/Data ROM Interface ................................................................9 Function Description ...............................................................................................11 7.1 Operational Register .........................................................................................11 7.2 Operational Register Detail Description............................................................11 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 R0 Indirect Addressing Register........................................................................11 R1 Page 0 TCC Data Buffer..............................................................................12 R1 Page 1 Interrupt Flag 1 Real Value .............................................................12 R1 Page 2 Interrupt Flag 2 Real Value .............................................................12 R1 Page 3 UART Receiver Data Buffer ............................................................13 R2 Program Counter .........................................................................................13 R3 Status Register ............................................................................................14 R4 RAM Select for Common Registers R20~R3F, UART Control Register .....15 7.2.8.1 Page 0................................................................................................ 15 7.2.8.2 Page 1 Undefined Register................................................................ 15 7.2.9 Page 2 UART Control Register 1 ......................................................................15 7.2.10 Page 3 UART Control Register 2 ......................................................................16 Product Specification (V2.4) 02.17.2006 • iii Contents 7.2.11 R5 Program Page Selection, CNT CLK & Scale Setting, CNT1 Data (L) .........20 7.2.11.1 Page 0 Program Page ....................................................................... 20 7.2.11.2 Page 1 Counter 1 Counter 2 CLK and Scale Setting ........................ 20 7.2.11.3 Page 2 Counter 1 Low 8-bit Data Buffer ............................................ 21 7.2.11.4 Page 3 DA Control ............................................................................. 21 7.2.12 R6 Port 6 I/O Data, Data ROM Data Buffer, CNT1 Data (H), DA Control .........22 7.2.12.1 Page 0 Port 6 I/O Data....................................................................... 22 7.2.12.2 Page 1 Data ROM Data Buffer .......................................................... 22 7.2.12.3 Page 2 Counter 1 High 8-bit Data Buffer ........................................... 22 7.2.12.4 Page 3 DA Control ............................................................................. 23 7.2.13 R7 Port 7 I/O Data, Data ROM Address, CNT2 Data, SPI Control ...................23 7.2.13.1 Page 0 Port 7 I/O Data....................................................................... 23 7.2.13.2 Page 1 Data ROM Address................................................................ 23 7.2.13.3 Page 2 Counter 2 Data Buffer............................................................ 24 7.2.13.4 Page 3 SPI Control Register.............................................................. 24 7.2.14 R8 Port 8 I/O Data, Data ROM Address, DTMF Receiver, SPI Data ................28 7.2.14.1 Page 0 Port 8 I/O Data....................................................................... 28 7.2.14.2 Page 1 Data ROM address................................................................ 28 7.2.14.3 Page 2 DTMF Receiver ..................................................................... 29 7.2.14.4 Page 3 SPI Data Buffer...................................................................... 31 7.2.15 R9 Port 9 I/O Data, Data ROM Address, Keytone Control................................31 7.2.15.1 Page 0 Port 9 I/O Data....................................................................... 31 7.2.15.2 Page 1 Data ROM Address................................................................ 32 7.2.15.3 Page 2 FSK/CW/DTMF Power Select ............................................... 32 7.2.15.4 Page 3 Keytone Control..................................................................... 32 7.2.16 RA CPU Power Saving, Main CLK Select, FSK, WDT Timer Comparator Control, Tone 1 Generator ................................................................................33 7.2.16.1 Page 0 Power Saving, Main CLK Select, FSK, WDT Timer .............. 33 7.2.16.2 Page 1 Undefined Register................................................................ 37 7.2.16.3 Page 2 Comparator Control Register ................................................ 37 7.2.16.4 Page 3 Tone 1 Control Register......................................................... 39 7.2.17 RB Port B I/O Data, Key Strobe, Tone 2 Generator ..........................................40 7.2.17.1 Page 0 Port B I/O Data ...................................................................... 40 7.2.17.2 Page 1 Undefined Register................................................................ 40 7.2.17.3 Page 2 Key Strobe Control Register.................................................. 40 7.2.17.4 Page 3 Tone 2 Control Register......................................................... 40 7.2.18 RC Port C I/O Data, Data RAM Data Buffer, Tone 2 Generator........................41 7.2.18.1 Page 0 Port C I/O Data ...................................................................... 41 7.2.18.2 Page 1 Data RAM Data Buffer 1........................................................ 41 7.2.18.3 Page 2 Key Strobe Control Register.................................................. 41 7.2.18.4 Page 3 Undefined Register:............................................................... 41 iv • Product Specification (V2.4) 02.17.2006 Contents 7.2.19 RD Port D I/O Data, Data RAM address ...........................................................42 7.2.19.1 Page 0 Port D I/O Data, Data RAM Address ..................................... 42 7.2.19.2 Page 1 Data RAM Address 1 (Low 8 Bits)......................................... 42 7.2.19.3 Page 2 Undefined Register................................................................ 42 7.2.19.4 Page 3 Undefined Register................................................................ 42 7.2.20 RE Interrupt Flag 1, Data RAM Address 1 (H) CAS, Key Scan ........................42 7.2.20.1 Page 0 Interrupt Flag 1 ...................................................................... 42 7.2.20.2 Page 1 Data RAM Address 1(H) ........................................................ 43 7.2.20.3 Page 2 CAS Detected Flag, Keyscan................................................ 43 7.2.20.4 Page 3 UART Transmitter Data Buffer............................................... 46 7.2.21 RF Interrupt flag ................................................................................................46 7.2.21.1 Page 1 External Data ROM ............................................................... 47 7.2.21.2 Page 2 External Data ROM ............................................................... 47 7.2.21.3 Page 3 Unused .................................................................................. 47 7.2.22 R10~R3F (General Purpose Register)..............................................................47 7.3 Special Purpose Registers................................................................................47 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 A (Accumulator).................................................................................................47 CONT (Control Register)...................................................................................48 IOC5 Address Automatic Increase/Decrease Control, Data RAM Data Buffer 2 ...........49 7.3.3.1 Page 0 Address Automatic Increase/Decrease Control Register ...... 49 7.3.3.2 Page 1 Data RAM Data Buffer 2........................................................ 50 IOC6 Port 6 I/O Control, Data RAM Address (L)...............................................51 7.3.4.1 Page 0 Port 6 I/O Control................................................................... 51 7.3.4.2 Page 1 Data RAM Address 2 (L)........................................................ 51 IOC7 PORT 7 I/O Control, Data RAM Address 2 (H)........................................51 7.3.5.1 Page 0 Port 7 I/O Control................................................................... 51 7.3.5.2 Page 1 Data RAM Address 2 (H) ....................................................... 51 IOC8 Port 8 I/O Control .....................................................................................52 7.3.6.1 Page 0 Port 8 I/O Control................................................................... 52 7.3.6.2 Page 1 Undefined Register................................................................ 52 IOC9 Port 9 I/O Control .....................................................................................52 7.3.7.1 Page 0 Port 9 I/O Control................................................................... 52 7.3.7.2 Page 1 Undefined Register................................................................ 52 IOCA Undefined Register..................................................................................52 7.3.9 IOCB Port B I/O Control, External LCD Driver Interface (for EMC 65×132) .....53 7.3.9.1 Page 0 Port B I/O Control .................................................................. 53 7.3.9.2 Page 1 External LCD Driver Controller.............................................. 53 7.3.10 IOCC Port C I/O Control, Port 6 Pull-high Register ..........................................56 7.3.10.1 Page 0 Port C I/O Control .................................................................. 56 7.3.10.2 Page 1 Port 6 Pull-high Register ....................................................... 56 7.3.11 IOCD Port D I/O Control, Port 7 Pull-high Register ..........................................56 7.3.11.1 Page 0 Port D I/O Control .................................................................. 56 7.3.11.2 Page 1 Port 7 Pull-high Register ....................................................... 57 Product Specification (V2.4) 02.17.2006 v Contents 7.3.12 IOCE Interrupt Mask, Differential Energy Detect ..............................................57 7.3.12.1 Page 0 Interrupt Mask Register 1 ...................................................... 57 7.3.12.2 Page 1 Differential Energy Detect...................................................... 57 7.3.13 IOCF Interrupt Mask Register 2 ........................................................................58 7.4 I/O Port..............................................................................................................59 7.5 Reset.................................................................................................................60 7.6 Wake-up............................................................................................................61 7.7 Interrupt.............................................................................................................61 7.8 Instruction Set ...................................................................................................61 7.9 Code Option Register .......................................................................................63 7.9.1 Code Option Register 1 (Program ROM)..........................................................63 7.10 Call Waiting Function Description .....................................................................64 8 9 10 11 12 7.11 Differential Energy Detector (DED) ...................................................................65 Absolute Maximum Ratings ................................................................................... 66 DC Electrical Characteristic ................................................................................... 66 AC Electrical Characteristic ................................................................................... 67 Timing Diagrams ..................................................................................................... 71 Application Circuit .................................................................................................. 74 APPENDIX A Application Note...................................................................................................... 75 Specification Revision History Doc. Version Date 1.0 Initial version 1.1 Changed the FSK, DTMF and CW Power Control 2.0 2.1 1. Removed the 256K byte data ROM 2. Removed the expand program/data memory interface 3. Embedded 1.2%, 2.0% and 5.5% CAS frequency range deviation 1. Added 256K byte data ROM 2. Added expand program/data memory interface 3. Removed 1.2% CAS frequency range deviation 4. Removed UART function 2003/03/04 2.2 Modified the Current DA resolution from 7 bit to 10 bit 2003/08/19 2.3 Added UART function 2003/10/08 2.4 vi • Revision Description 1. Removed Idle mode 2. Added application note item 7 2006/02/17 Product Specification (V2.4) 02.17.2006 EM78815 8-Bit Microcontroller 1 General Description The EM78815 is an 8-bit CID (Call Identification) RISC type microprocessor with low power, high speed CMOS technology. Integrated onto a single chip are on chip watchdog (WDT), programmable real time clock/counter, external/internal interrupt, power down mode, EMC65132 LCD controller, FSK decoder, Call waiting decoder, Energy Detector (DED) , DTMF receiver, Programming Tone generator, build-in Keytone clock generation, Comparator and tri-state I/O. The EM78815 provides a single chip solution to design a CID of calling message display. 2 Features 2.1 CPU Operating voltage range: 2.2V~3.6V(Normal mode), 2.0V~3.6V(Green mode) 64K×13 on-chip Program ROM, supports a max. of 128K word program 256K×8 on-chip data ROM, supports a max. of 2M byte data 4Kx8 data RAM 128×8 common register Up to 56 bidirectional tri-state I/O ports IO with internal Pull high, wake-up and interrupt functions Stack: 24-level stack for subroutine nesting TCC: 8-bit real time clock/counter (TCC) with 8-bit prescaler Counter 1: 16 bit counter with 8-bit prescaler can be an interrupt source Counter 2: 8-bit counter with 8-bit prescaler can be an interrupt source Watchdog: Programmable free running on-chip watchdog timer CPU modes: Mode CPU Status Main Clock 32.768kHz Clock Status Sleep mode Turn off Turn off Turn off Green mode Turn on Turn off Turn on Normal mode Turn on Turn on Turn on 15 interrupt source: 8 external, 7 internal Key Scan: Port key scan function up to 16×4 keys Sub-Clock: 32.768kHz crystal Main-clock: 3.5862MHz multiplied by 0.5, 1, 1.5 or 3 generated by internal PLL Keytone output: 4kHz, 2kHz, 1kHz (shared with IO) Comparator: 3-channel comparators, internal (16 level) or external reference voltage (shared with IO) Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) •1 EM78815 8-Bit Microcontroller 2.2 Serial Transmitter/Receiver Interface Serial Peripheral Interface (SPI): Interrupt flag available for the read buffer full, Programmable baud rates of communication, Three-wire synchronous communication (shared with IO) Universal asynchronous receiver transmitter interface. User can select (7/8/9 bits) with/without parity bit, Baud rate setting and error detection function. Interrupt available for RX buffer full or TX buffer empty. Two wire asynchronous communication (shared with IO) 2.3 Current D/A Operating Voltage: 2.5V~3.6V 10-bit resolution and 3-bit output level control Current DA output can drive the speaker through a transistor for sound playing. (shared with IO) 2.4 Programmable Tone Generators Operating Voltage: 2.2V~3.6V Programmable Tone 1 and Tone 2 generators Independent single tone generation for Tone 1 and Tone 2 Mixed dual tone generation by Tone 1 and Tone 2 with 2dB difference Can be programmed for DTMF tone generation Can be programmed for FSK signal (Bell202 or V.23) generation 2.5 CID 2• Operating Voltage: 2.4V~3.6V for FSK Operating Voltage: 2.4V~3.6V for DTMF receiver Compatible with Bellcore GR-30-Core (formerly as TR-NWT-000030) Compatible with British Telecom (BT) SIN227 & SIN242 FSK demodulator for Bell 202 and ITU-T V.23 (formerly as CCITT V.23) Differential Energy Detector (DED) for line energy detection Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller 2.6 Call Waiting Operating Voltage: 2.4V~3.6V Compatible with Bellcore special report SR-TSV-002476 Call-Waiting (2130Hz plus 2750Hz) Alert Signal Detector Good talk-down and talk-off performance Sensitivity compensated by adjusting input OP gain 2.7 External LCD controller (64 × 256 dot max for a pair of Master and Slave LCD Driver) Multi-chip operation (Master, Slave) available for external LCD device 2.8 Package Type 3 105-pin Chip: EM78815H 128-pin QFP: (EM78815AQ, POVD disable) (EM78815BQ, POVD enable) Application SMS phone Feature phones Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 3 EM78815 8-Bit Microcontroller 4 Pin Configuration EXD2 EXD3 EXD4 EXD5 EXD6 EXD7 RD WR CS EXA0 EXA1 EXA2 EXA3 EXA4 EXA5 EXA6 EXA7 EXA8 EXA9 EXA10 EXA11 EXA12 EXA13 EXA14 EXA15 EXA16 EXA17 EXA18 EXA19 EXA20 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 EXD1 EXD0 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 PB0/LD0 PB1/LD1 PB2/LD2 PB3/LD3 PB4/LD4 PB5/LD5 PB6/LD6 PD7/DAOUT VDD XIN XOUT /RESET P70/INT0 P71/INT1 P72/INT2 P73/INT3 P74/INT4 P75/INT5 P76/INT6/KTONE P77/INT7 EXSEL GND TEST PC7 PC6 PC5 PC4/A0 PC3/RD PC2/WR PC1/CS1 PC0/CS2 PB7/LD7 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 AVDD PLLC TONE TIP RING CWGS CWIN EGIN1 EGIN2 AVSS P60/STGT P61/EST P62 P63 P64 P65CMP1 P66/CMP2 P67/CMP3 PD0 PD1 PD2/UR PD3/UT PD4/SCK PD5/SDO PD6/SDI Fig.1a 105-pin Chip Assignment 4• Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller CS EXA0 NC NC NC NC NC NC EXA1 EXA2 EXA3 EXA4 EXA5 EXA6 EXA7 EXA8 EXA9 EXA10 EXA11 EXA12 EXA13 EXA14 EXA15 EXA16 EXA17 EXA18 EXA19 EXA20 AVDD PLLC TONE TIP 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 WR RD EXD7 EXD6 EXD5 EXD4 EXD3 EXD2 EXD1 EXD0 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 PB0/LD0 PB1/LD1 PB2/LD2 NC NC NC NC NC NC NC NC NC P70/INT0 P71/INT1 P72/INT2 P73/INT3 P74/INT4 P75/INT5 P76/INT6/KTONE P77/INT7 EXSEL GND TEST PC7 PC6 PC5 PC4/A0 PC3/RD PC2/WR PC1/CS1 PC0/CS2 PB7/LD7 PB6/LD6 PB5/LD5 PB4/LD4 PB3/LD3 NC NC NC NC NC RING CWGS CWIN EGIN1 EGIN2 AVSS P60/STGT P61/EST P62 P63 P64 P65CMP1 P66/CMP2 P67/CMP3 PD0 PD1 PD2 PD3 PD4/SCK PD5/SDO PD6/SDI PD7/DAOUT VDD VDD XIN XOUT /RESET NC NC Fig. 1b 128-pin QFP Assignment Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 5 EM78815 8-Bit Microcontroller 5 Functional Block Diagram VDD P ro g ra m ROM D a ta D ATA RAM S e ria l IO MCU D ATA ROM GND AVDD TO NE Dual Tone G e n e ra to r DTMF s ig n a l DTM F R e c e iv e r PLL CW D ecoder CAS FSK D ecoder FSK s ig n a l FSK DTM F CAS s ig n a l A n a lo g in p u t C o m p a ra to r E n e rg y D e te c to r C u rre n t DA DAOUT AVSS Fig. 2 Block Diagram 1 Xin Xout PLLC Prescalar R1 (TCC) Control sleep and wake-up on I/O port Stack R2 ROM WDT Timer Oscillator Timing Control General RAM Interrupt Control Instruction Register ALU R3 R5 Instruction Decoder R4 ACC Data & Control Bus Data RAM FSK Decoder Call Waiting Decoder DTMF DUAL TONE DTMF Receiver GENERATOR Dualreceiver Tone Generator Keytone KEY TONE Serial I/O SERIAL I/O COMPARATO Comparator Current R DA Energy Detect Port 6 Port 7 Port 8 Port 9 Port B Port C Port D IOC6 R6 IOC7 R7 IOC8 R8 IOC9 R9 IOCB RB IOCC RC IOCD RD P60~P67 P70~P77 P80~P87 P90~P97 PB0~PB7 PC0~PC7 PD0~PD7 Fig. 3 Block Diagram 2 6• Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller 6 Pin Descriptions 6.1 Power Pin Pin I/O Description VDD Power Digital Power AVDD Power Analog Power GND Power Digital Ground AVSS Power Analog Ground 6.2 Clock Pin Pin I/O XIN I Input pin for 32.768 kHz oscillator Description XOUT O PLLC I Output pin for 32.768 kHz oscillator Phase lock loop capacitor, connect a 0.01µ capacitor to 0.047µ with GND. 6.3 External LCD Device Control Pin Pin I/O LCDD0~LCDD7 I/O /WR O /RD O A0 O /CS1 ~ /CS2 O Description External LCD driver data bus. This is pin-shared with Port B0~Port B7. Write enable output (active low signal). This is pin-shared with Port C2. Read enable output (active low signal). This is pin-shared with Port C3. Used as register selection. When A0 is equal to 1, the data bus transmits LCD Data. When A0 is equal to 0, the data bus transmits LCD Address. This is pin-shared with Port C4. Chip Select signal output. This is pin-shared with Port C1~ Port C0 6.4 FSK, CW Pin I/O TIP I RING I CWGS O Description Should be connected to the TIP side of the twisted pair lines for FSK. Should be connected to the RING side of the twisted pair lines for FSK. Gain adjustment of single-ended input OP Amp. CWIN I Single-ended input OP Amp for call waiting decoder. Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 7 EM78815 8-Bit Microcontroller 6.5 DTMF Receiver, OP Pin I/O EST O STGT I/O Description Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone-pair (signal condition). Any momentary loss of signal condition will cause the EST to return to a logic low. This is pinshared with Port 61. Steering input/guard time output (bi-directional). A voltage greater than Vtst detected at ST causes the device to register the detected tone-pair and update the output latch. A voltage less than Vtst frees the device to accept a new tone-pair. The GT output acts to reset the external steering time-constant; its state is a function of EST and the voltage on ST. This is pin-shared with Port 60. 6.6 Serial IO, Comparator, Current DA, Tone Pin I/O SCK I/O SDO O SDI UR UT CMP1 CMP2 CMP3 I I O I I I DAOUT O KTONE TONE O O Description Master: output pin, Slave: input pin. This is pin-shared with Port D4. Output pin for serial data transferring. This is pin-shared with Port D5. Input pin for receiving data. This is pin-shared with Port D6. Data receiver pin for UART. This pin shared with Port D2 Data transmitter pin for UART. This is pin-shared with Port D3. Comparator input pins. This is pin-shared with Port 65. Comparator input pins. This is pin-shared with Port 66 Comparator input pins. This is pin-shared with Port 67. Current DA output pin. It can be a control signal for sound generation. This is pin-shared with Port D7. Key tone output. This is pin-shared with Port 76. Dual tone output pin 6.7 IO 8• Pin I/O P60 ~P67 I/O P70 ~ P77 I/O P80 ~ P87 P90 ~ P97 PB0 ~ PB7 PC0 ~ PC7 I/O I/O I/O I/O PD0 ~ PD7 I/O P70 ~ P76 I P77 I /RESET I Description Each bit in Port 6 can be Input or Output port. Internal pull high. Each bit in Port 7 can be Input or Output port. Internal Pull high function, Auto key scan function, and Interrupt function. Each bit in Port 8 can be Input or Output port. Each bit in Port 9 can be Input or Output port. Each bit in Port B can be Input or Output port. Each bit in Port C can be Input or Output port. Each bit in Port D can be Input or Output port. This is pin-shared with SPI pin and CMP input pin. Interrupt sources. When any pin from Port 70 to Port 76 has a falling edge signal, it will generate a corresponding interrupt. Interrupt source. Once Port 77 has a falling edge or rising edge signal (controlled by CONT register), it will generate an interrupt. Low reset Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller 6.8 Expand Program/Data ROM Interface Pin I/O Description EXD0 ~ EXD7 I/O Expand Program/Data memory Data Bus /RD O Expand Program/Data memory Read request output /WR O Expand Program/Data memory Write request output /CS O Expand Program/Data memory CS request output EX0~EXA20 O Expand Program/Data memory Address Bus EXSEL I 0/1 Æ Internal 64K Program ROM used/unused EXSEL pin : 0/1 → On-chip program ROM used/unused switch. The EM78815 supports a max. of 128K Program. User can support program for both 64K EM78815 on-chip ROM and 64K expanded ROM. User can also ignore the 64K EM78815 on-chip ROM and support all programs for an external 128K ROM. Using this function, user can easily upgrade programs or download new functions. The EM78815 provides Data ROM expanded function. When user access data of which address is over 256K, the external ROM will be loaded. User must set the expanded start address of the Data ROM to RF Page 1, Page 2 and IOCB Page 1. A diagram of the expanded function is shown below. Max. of 2M Byte Expanded ROM (FLASH ROM) Expanded Data ROM Start Address 64K Program ROM (Page 0 ~ Page 63) 64K word Program ROM (Page 64 ~ Page127 IOCB B7 B7 RF Page 2 RF Page 1 B0 B7 B0 0 0 0 X X X X X X X X X X X X X X X X X 0 ROM Address 17 ROM Address 9 ROM Address 0 256K Byte Data ROM Expanded Data ROM EM78815 (EXSEL pin go low) Fig. 4a EXSEL = 0, Both Internal and External Programs are Used Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 9 EM78815 8-Bit Microcontroller Max. of 2M Byte Expanded ROM (FLASH ROM) Expanded Data ROM Start Address 64K Program ROM Unused 128K word Program ROM (Page 0 ~ Page 127) IOCB B7 B7 RF Page 2 RF Page 1 B0 B7 B0 0 0 0 X X X X X X X X X X X X X X X X X 0 ROM Address 17 ROM Address 9 ROM Address 0 256K byte Data ROM Expanded Data ROM EM78815 (EXSEL pin pull high) Fig. 4b EXSEL = 1, Only External Program is Used Setting the expanded Data ROM’s Starting Address The EM78815 supports a maximum of 2M Bytes expanding data memory, but user must fix the start address of the external program at 0x00000 and set the start address of the expanded Data ROM since the program ROM size is adjustable. In this way, the MCU will get data from the external memory if the data ROM is over 256K. The instruction width is 13 bits and the data bus for external memory is 8 bits, so an instruction will capture two address sizes and the LSB address of the start address at the external ROM will be 0. Besides, the EM78815 only supports a max of 128K program, so the start address of the Data ROM will be smaller than 256K+2 and A20, A19 and A18 will also be 0. User must set the expanded start address of the Data ROM at A17~A1 to IOCB Page 2, Bit 7, RF Page 3 and RF Page 2. 10 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller 7 Function Description 7.1 Operational Register REGISTER REGISTER REGISTER REGISTER PAGE0 PAGE1 PAGE2 PAGE3 Control Control REGISTER REGISTER PAGE0 PAGE1 Address R1 (Real Interrupt Flag 1) 01 R1 (TCC Buffer) 02 R2 (PC) 03 R3 (STATUS) 04 R4 (RSR, Bank Select) 05 R5 (Program Page) 06 R1 (Real Interrupt Flag 2) R1 (UART Receiver Buffer) R3 (6, 7) R4 (UART Control 1) R4 (UART Contro l2) R5 (Counter Setting) R5 (CNT1 low 8-bit data) R5 (Current DA Control) IOC5 (Address auto inc/dec Control) IOC5 (DRAM2 Data Buffer) R6 (Port 6 IO data) R6 (DROM Data Buffer) R6 (CNT1 high 8-bit data) R6 (Current DA Control) IOC6 (Port 6 I/O Control) IOC6 (DRAM2 Address) 07 R7 (Port 7 IO data) R7 (DROM Address) R7 (CNT2 data) R7 (SPI Control) IOC7 (Port 7 I/O Control) IOC7 (DRAM2 Address) 08 R8 (Port 8 IO data) R8 (DROM Address) R8 (DTMF receiver) R8 (SPI Data Buffer) IOC8 (Port 8 I/O Control) IOC8 (Unused) R9 (CMP IO control) R9 (Keytone Control, UART MSB) IOC9 (Port 9 I/O Control) IOC9 (Unused) RA (Comparator Control) RA (Tone 1 Control) IOCA (Stack Pointer) IOCA (Unused) IOCB (External LCD Driver Control Interface) 09 0A R4 (Unused) R3 (5) R9 (Port 9 IO data) R9 (DROM Address) RA (Power saving , FSK) RA (Unused) RB (Unused) RB (Key Strobe Control) RB (Tone 2 Control) IOCB (Port B I/O control) RC (DRAM1 Data Buffer) RC (Key Strobe Control) RC (Unused) IOCC (Port C I/O Control) IOCC (P6 Pull-high Control) RD (DRAM1 Address) RD (Unused) RD (Unused) IOCD (Port D I/O Control) IOCD (P7 Pull-high Control) RE (Key Scan , CAS) RE (Unused) IOCE (Interrupt Mask 1) RF (External Data ROM Start Address High) RF (Unused) IOCE (Interrupt Mask 2) 0B RB (Port B IO data) 0C RC (Port C IO data) 0D RD (Port D IO data) 0E RE (Interrupt Flag 1) RE (DRAM 1 Address, DED Output ) 0F RF (Interrupt Flag 2) RF (External Data ROM Start Address Low) IOCE (DED Control) 10 : 16 Byte Commom register 1F DATA ROM R7 PAGE1 : address(L) R8 PAGE1 : address(M) R9 PAGE1 : address(H) R6 PAGE1 : data 20 : R4 P1(7,8) 3F Bank0 32x8 Bank1 32x8 Bank2 32x8 Bank3 32x8 DATA RAM (Index 1) RD PAGE1 : address(L) RE PAGE1 : address(H) RC PAGE1 : data DATA RAM (Index2) IOC6 PAGE1 : address(L) IOC7 PAGE1 : address(H) IOC5 PAGE1 : data Commom register Fig. 5 Control Register Configuration 7.2 Operational Register Detail Description 7.2.1 R0 Indirect Addressing Register R0 is not a physically implemented register. It is provided as an indirect addressing pointer. Any instruction using R0 as register actually accesses data pointed to by the RAM Select Register (R4). Example: mov A , @0x20 mov mov 0x04 , A A , @0xAA mov 0x00 , ;store an address at R4 for indirect ;addressing ;write data 0xAA to R20 at Bank 0 ;through R0 A Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 11 EM78815 8-Bit Microcontroller 7.2.2 R1 Page 0 TCC Data Buffer This is increased by 16.38 kHz or by the instruction cycle clock (controlled by CONT register). Written and read by the program as any other register. 7.2.3 R1 Page 1 Interrupt Flag 1 Real Value Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTR7 INTR6 INTR5 INTR4 INTR3 INTR2 INTR1 INTR0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0~Bit 7(INTR0~INTR7) : Interrupt Flag 1 real value. User can clear this page from 1 to 0 but cannot set this register to 1. The relation of R1 Page1, RE Page 0 and IOCE Page 0 is shown in the figure. When user disables the interrupt mask, whether an interrupt occurs or not, the interrupt flag (RE Page 0) will appear “0”. Opposite of RE Page 0, R1 Page 1 will show real interrupt occur status regardless whether this interrupt mask is enabled or disabled. User can clear the corresponding external interrupt flag in RE Page 0 or R1 Page 1. Interrupt occurs Interrupt Mask IOCE, IOCF Interrupt Flag (RE, RF) Real Interrupt Flag (R0 P1,P2) Fig. 6 Relationship between Interrupt Mask, Flag and Real Flag 7.2.4 R1 Page 2 Interrupt Flag 2 Real Value Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RBF/STD FSK/CW - UART DED CNT2 CNT1 TCC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0~Bit 7 (Internal Interrupt Flag Real Value) : Interrupt Flag 1 real value. User can clear this page from 1 to 0 but cannot set this register to 1. The relationship between R1 Page 2, RF Page 0 and IOCF Page 0 is shown in Fig. 6. When user disables an interrupt mask, whether an interrupt occurs or not, the interrupt flag (RF Page 0) will appear “0”. Opposite of RF Page 0, R1 Page 1 will show real interrupt occur status regardless whether this interrupt mask is enabled or disabled. User can clear the corresponding interrupt flag in RF Page 0 or R1 Page 2. 12 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller 7.2.5 R1 Page 3 UART Receiver Data Buffer Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 URR7 URR6 URR5 URR4 URR3 URR2 URR1 URR0 R R R R R R R R Bit 0~Bit 7(URR0~URR7) : UART receiver low 8 bit data buffer. UART receiver data buffer is a read-only register. 7.2.6 R2 Program Counter There are 128K × 13 External Program ROM addresses at the relative programming instruction codes. The structure is depicted on Fig. 5. "JMP" instruction allows a direct loading of the low 10 program counter bits. "CALL" instruction loads the low 10 bits of the PC, PC+1, and then pushed into the stack. "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack. "MOV R2,A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are cleared to "0''. "ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are cleared to "0''. "TBL" allows a relative address be added to the current PC, and contents of the ninth and tenth bits do not change. The most significant bit (A10~A14) will be loaded with the contents of bits PS0~PS3 in the status register (R5) upon the execution of a "JMP'', "CALL'', "ADD R2, A'', or "MOV R2,A'' instruction. If there is an interrupt trigger, the Program ROM will jump to Address 8 at Page 0. The CPU will store ACC, R3 status and R5 Page automatically, it will restore after instruction RETI. Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 13 EM78815 8-Bit Microcontroller R5(PAGE) CALL and INTERRUPT A16 A15 A14 A13 A12 A11 A10 A9 A8 STACK1 STACK2 STACK3 STACK4 STACK5 STACK6 STACK7 STACK8 A7~A0 0000000 PAGE0 00000~003FF RET RETL RETI 0000001 PAGE1 00400~007FF 0000010 PAGE2 00800~00BFF : : STACK22 STACK23 STACK24 store ACC,R3,R5(PAGE) restore 1111110 PAGE126 1F800~1FBFF 1111111 PAGE127 1FC00~1FFFF Fig. 7 Program Counter Organization 7.2.7 R3 Status Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RS1 RS0 IOCS T P Z DC C R/W-0 R/W-0 R/W-0 R/W-X R/W-X R/W-X R/W-X R/W-X Bit 0 (C) : Carry Bit 1 (DC) : Auxiliary carry flag Bit 2 (Z) : Zero flag Bit 3 (P) : Power down bit Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 4 (T) : Time-out bit Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout. Event WDT wake up from sleep mode 14 • T P 0 0 WDT time out (not sleep mode) 0 1 /RESET wake up from sleep 1 0 Power up 1 1 Low pulse on /RESET × × Remark ×: don't care Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller Bit 5 (IOCS) : IOC register select bit. Change IOC5 ~ IOCE to another page Bit 6~Bir 7 (RS0 ~ RS1) : R register select bits. Change R1, R2, R4 ~ RE to another page. RS1 RS0 R Page 0 0 Page 0 0 1 Page 1 1 0 Page 2 1 1 Page 3 7.2.8 R4 RAM Select for Common Registers R20~R3F, UART Control Register 7.2.8.1 Page 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RBS1 RBS0 RSR5 RSR4 RSR3 RSR2 RSR1 RSR0 R/W-0 R/W-0 R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X Bit 0 ~ Bit 5 (RSR0 ~ RSR5) : Indirect addressing for common registers R20 ~ R3F RSR bits are used to select up to 32 registers (R20 to R3F) in indirect addressing mode. Bit 6 ~ Bit 7 (RB0 ~ RB1) : Bank selection bits for common registers R20 ~ R3F These selection bits are used to determine which bank is activated among the 4 banks of the 32 registers (R20 to R3F). Refer to Fig. 4 Control Register Configuration for details. 7.2.8.2 Page 1 Undefined Register This register is unimplemented, not for use. 7.2.9 Page 2 UART Control Register 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TRS2 TRS1 TRS0 URM1 URM0 ERE TXE RXE Bit 0 (RXE) : Enable UART receiving function & UART interrupt mask 1 → Enable 0 → Disable Bit 1 (TXE) : Enable UART transmission function & UART interrupt mask 1 → Enable 0 → Disable Bit 2 (ERE) : Enable UART receiver error interrupt mask Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 15 EM78815 8-Bit Microcontroller RF Bit 4 (UART) Interrupt Trigger Event ERR TXE REX × 0 0 UART interrupt disable 0 0 1 UART read buffer full 1 0 1 UART read buffer full or Receiver Data Error × 1 0 UART transmitter buffer empty 0 1 1 1 1 1 UART read buffer full or UART transmitter buffer empty UART read buffer full or UART transmitter buffer empty or Receiver Data Error I/O Status PD2ÆIO PD3ÆIO PD2ÆUART receiver pin PD3ÆIO PD2ÆUART receiver pin PD3ÆIO PD2ÆIO PD3ÆUART transmitter pin PD2ÆUART receiver pin PD3ÆUART transmitter pin PD2ÆUART receiver pin PD3ÆUART transmitter pin Bit 4~Bit 3 (URM1~URM0) : UART Mode Select URM1 URM0 Mode Status 0 0 7 bit data 0 1 8 bit data 1 0 9 bit data 1 1 × Bit 7~Bit 5 (TRS2~TRS0) : Baud Rate Select TRS2 TRS1 TRS0 Baud Rate 0 0 0 600 baud 0 0 1 1200 baud 0 1 0 2400 baud 0 1 1 9600 baud 1 0 0 19200 baud 1 0 1 38400 baud 1 1 0 57600 baud 1 1 1 115200 baud Note: 600 and 1200 baud rates can be run in green mode 7.2.10 Page 3 UART Control Register 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 − EVEN PRE PRERR OVERR FMERR UTBE URBF × R/W-X R/W-0 R/W-0 R/W-0 R/W-0 R R Bit 0 (URBF) : UART read buffer full flag . Set to 1 when one character is received. Reset to 0 automatically when read from UART data buffer. 16 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller Bit 1 (UTBE) : UART transfer buffer empty flag. Set to 1 when transfer buffer is empty. Reset to 0 automatically when writing into the UART data buffer. Bit 2 (FMERR) : Receiver error flag . Set to 1 when frame error occurs. Clear this bit to 0 by software. Bit 3 (OVERR) : Receiver error flag . Set to 1 when over running error occurs. Clear this bit to 0 by software. Bit 4 (PRERR) : Receiver error flag . Set to 1 when parity error occurs. Clear this bit to 0 by software. Bit 5 (PRE) : Enable parity addition 1 → Enable 0 → Disable Bit 6(EVEN) : EVEN/ODD parity check select 1 → Even parity 0 → Odd parity In Universal Asynchronous Receiver Transmitter (UART), each transmitted or received character is individually synchronized by framing it with a start bit and stop bit. The figure below shows the general format of one character sent or received. The communication channel is normally held in the mark state (high). Character transmission or reception starts with a transition to the space state (low). The first bit transmitted or received is the start bit (low). It is followed by the data bits, in which the least significant bit (LSB) comes first. The data bits are followed by the parity bit. If present, then the stop bit or bits (high) confirm the end of the frame. In receiving, the UART synchronizes on the falling edge of the start bit. When two or more “0” are detected during 3 samples, it is recognized as normal start bit and the receiving operation is started. START bit D0 D1 D2 1 bit 7 or 8 bits Dn Parity STOP bit bit 1 bit Idle state (mark) 1 bits One character or frame Fig. 8 UART Data Frame Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 17 EM78815 8-Bit Microcontroller There are three modes in UART. Mode 1 (7 bits data) and Mode 2 (8 bits data) allow the addition of a parity bit. The parity bit addition is not available in Mode 3. The Figure below shows the data format in each mode. UMODE Mode 1 Mode 2 Mode 3 PRE 1 2 3 4 5 6 7 8 9 10 11 0 0 0 START 7 bits DATA STOP 0 0 1 START 7 bits DATA Parity 0 1 0 START 8 bits DATA STOP 0 1 1 START 8 bits DATA Parity STOP 1 0 X START 9 bits DATA STOP STOP Fig. 9 UART Mode In transmitting serial data, the UART operates as follows. 1. Set TXE bit of the UARTCON register to enable the UART transmission function. 2. Write data into the UART data buffer. Then start transmitting. 3. Serial transmit data are transmitted in the following order from UT (Port C7) pin. (a) Start bit: output one “0” bit (b) Transmit data: 7, 8 or 9 bits data are output from LSB to MSB (c) Parity bit: output one parity bit (odd or even selectable) (d) Stop bit: output one “1” bit (stop bit) (e) Mark state: output “1” continues until the start bit of the next transmit data 4. After transmitting the stop bit, the UART generates a UART interrupt (if enabled) 5. UTBE bit will be set to 1 In receiving, the UART operates as follows: 1. Set the RXE bit of the UARTCON register to enable the UART receiving function. The UART monitors the UR (Port C6) pin and synchronizes internally when it detects a start bit. 2. Receive data is shifted into the UARTRx register in the order from LSB to MSB. 18 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller 3. The parity bit and the stop bit are received. After one character is received, the UART generates a UART interrupt (if enabled). URBF bit will be set to 1. 4. The UART makes the following checks: (a) Parity check: The number of 1 in receive data must match the even or odd parity setting of the EVEN bit in the UARTSTA register. (b) Frame check: The start bit must be 0 and the stop bit must be 1. (c) Overrun check: URBF bit of UARTCON register must be cleared (which means that the UARTRx register should be read out) before the next received data is loaded into the UARTRx register. If any checks failed, a UART interrupt will be generated (if enabled). The error flag should be cleared by software else a UART interrupt will occur when the next byte is received. 5. Read received data from the UART register. URBF bit will be cleared by hardware. Selector Fsystem RXE Baud rate generator RX Control TX Control Interrupt TXE Control RXD RX shift register UINVEN URR8 URR7~URR0 Parity control Error flag TXD URT8 Data Bus URT7~URT0 UINVEN Fig. 10 UART Function Block Bit 7 : Unused Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 19 EM78815 8-Bit Microcontroller 7.2.11 R5 Program Page Selection, CNT CLK & Scale Setting, CNT1 Data (L) 7.2.11.1 Page 0 Program Page Bit 7 × Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PS6 PS5 PS4 PS3 PS2 PS1 PS0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 6 (PS0 ~ PS6) : Program page selection bits PS6 PS5 PS4 PS3 PS2 PS1 PS0 Program Memory Page (Address) 0 0 0 0 0 0 0 Page 0 0 0 0 0 0 0 1 Page 1 0 0 0 0 0 1 0 Page 2 0 0 0 0 0 1 1 Page 3 : : : : : : : : : : : : 1 1 1 1 1 1 0 Page 126 1 1 1 1 1 1 1 Page 127 User can use the Page instruction to change page and maintain user’s program page. Bit 7 : This bit is undefined, not for use. 7.2.11.2 Page 1 Counter 1 Counter 2 CLK and Scale Setting Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CNT2S C2P2 C2P1 C2P0 CNT1S C1P2 C1P1 C1P0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0~Bit 2(C1P0~C1P2) : Counter 1 scaling C1P2 C1P1 C1P0 Counter 1 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Bit 3 (CNT1S) : Counter 1 clock source 0/1 → 16.384kHz/instruction clock 20 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller Bit 4~Bit 6 (C2P0~C2P2) : Counter 2 scaling. Prescaler is different for Bit 0~Bit 2. C2P2 C2P1 C2P0 Counter 2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 Bit 7 (CNT2S) : Counter 2 clock source 0/1 → 16.384kHz / instruction clock 7.2.11.3 Page 2 Counter 1 Low 8-bit Data Buffer Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CN17 CN16 CN15 CN14 CN13 CN12 CN11 CN10 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0~Bit 7 (CN10~CN17) : Counter 1 data buffer Counter 1 is a 16 bits up-counter with 8-bit prescaler and user can read or write into the counter through R5 Page 2 and R6 Page 2. After an interrupt, it will reload the preset value. Example: write: MOV 0x05,A ; write the accumulator data to Counter 1 (preset) Example: read: MOV A,0x05 ; read R5 data and write into the accumulator Example: write: MOV 0x06,A ; write the accumulator data (high 8 bits) to Counter 1 Example: read: MOV A,0x06 ; read R6 data (high 8 bits) and write into the accumulator 7.2.11.4 Page 3 DA Control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 − − − − CDAS CDAL2 CDAL1 CDAL0 − − − − R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 2 (CDAL0 ~ CDAL2) : Change output level of the current DA CDAL2 CDAL1 CDAL0 Output Level 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 L0 (ratio = 1/8) L1 (ratio = 2/8) L2 (ratio = 3/8) L3 (ratio = 4/8) L4 (ratio = 5/8) L5 (ratio = 6/8) L6 (ratio = 7/8) L7 (ratio =1) Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 21 EM78815 8-Bit Microcontroller Bit 3 (CDAS) : Current DA switch 0 → normal Port D7 1 → Current DA output Bit 4 ~ Bit 7 : Undefined Register. These bits are undefined and not for use. 7.2.12 R6 Port 6 I/O Data, Data ROM Data Buffer, CNT1 Data (H), DA Control 7.2.12.1 Page 0 Port 6 I/O Data Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P67 P66 P65 P64 P63 P62 P61 P60 R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X Bit 0 ~ Bit 7 (P60 ~ P67) : 8-bit Port 6 (0~7) I/O data register User can use IOC register to define whether each bit is input or output. 7.2.12.2 Page 1 Data ROM Data Buffer Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DRD7 DRD6 DRD5 DRD4 DRD3 DRD2 DRD1 DRD0 R R R R R R R R Bit 0 ~ Bit 7 (DRD0 ~ DRD7) : Data ROM data buffer for ROM reading. Example. MOV A,@1 MOV R7_PAGE1,A MOV A,@0 MOV R8_PAGE1,A MOV A,@0 MOV R9_PAGE1,A MOV A,R6_PAGE1 ;read the data at the Data ROM, of which ;address is "00001". 7.2.12.3 Page 2 Counter 1 High 8-bit Data Buffer Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CN1F CN1E CN1D CN1C CN1B CN1A CN19 CN18 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0~Bit 7 (CN18~CN1F) : Counter 1 high 8 bits data buffer. Refer to R5 Page 2 Counter 1 low 8-bit data buffer for details. 22 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller 7.2.12.4 Page 3 DA Control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 7 (DA2 ~ DA9) : Current DA most significant 8 bits of Current DA output buffer Combine these 8 bits and R9 Page 3 Bit 4~Bit 5, 2 bits as complete 10 bits Current DA output data. Control register Bit 3 is Current DA power control. VDD DA9..DA0 DAOUT Current DA Circuit Port D7 MUX Port D7 DAEN DAS Fig 11 s Current DA structure 7.2.13 R7 Port 7 I/O Data, Data ROM Address, CNT2 Data, SPI Control 7.2.13.1 Page 0 Port 7 I/O Data Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P77 P76 P75 P74 P73 P72 P71 P70 R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X Bit 0 ~ Bit 7 (P70 ~ P77) : 8-bit Port 7(0~7) I/O data register User can use the IOC register to define whether each bit is input or output. 7.2.13.2 Page 1 Data ROM Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DRA7 DRA6 DRA5 DRA4 DRA3 DRA2 DRA1 DRA0 R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X Bit 0 ~ Bit 7 (DRA0 ~ DRA7) : Data ROM address ( 0~7 ) for ROM reading Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 23 EM78815 8-Bit Microcontroller 7.2.13.3 Page 2 Counter 2 Data Buffer Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CN27 CN26 CN25 CN24 CN23 CN22 CN21 CN20 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0~Bit 7(CN20~CN27) : Counter 2's data buffer User can read and write into this buffer. Counter 2 is an 8-bit up-counter with 8-bit prescaler that user can use R7 page2 to preset and read the counter (write = preset). After an interrupt, it will reload the preset value. Example: write: MOV 0x07 , A ; write the data at accumulator to counter1 (preset) Example: read: MOV A , 0x07 ; read R7 data and write to accumulator 7.2.13.4 Page 3 SPI Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RBF SPIE SRO SE SCES SBR2 SBR1 SBR0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Fig.12 shows how SPI to communicate with other device by SPI module. If SPI is a master controller, it sends clock through the SCK pin. An 8-bit data is transmitted and received at the same time. If SPI, however, is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be shifted basing on the clock rate and the selected edge. SDO SDI Master Device Slave Device R5 Page 1 SPIR register SPIW register SPIS Reg Bit 7 SDI SDO SCK SCK Bit 0 SPI module Fig 12: Single SPI Master / Salve Communication 24 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller Bit 0 ~ Bit 2 (SBR0 ~ SBR2) : SPI baud rate selection bits SBR2 SBR1 SBR0 Mode Baud Rate 0 0 0 Master Fsco 0 0 1 Master Fsco/2 0 1 0 Master Fsco/4 0 1 1 Master Fsco/8 1 0 0 Master Fsco/16 1 0 1 Master Fsco/32 Slave 1 1 0 1 1 1 × Note: Fsco = CPU Instruction Clock Example: If PLL enable and RA Page 0 (Bit 5, Bit 4) = (1, 1), instruction clock is 3.58 MHz/2 → Fsco=3.5862MHz/2 If PLL enable and RA Page 0 (Bit 5, Bit 4) = (0, 0), instruction clock is 0.895 MHz/2 → Fsco=0.895 MHz/2 If PLL disable, instruction clock is 32.768kHz/2 → Fsco=32.768kHz/2. Bit 3 (SCES) : SPI clock edge selection bit 0 → Data shifts out on a rising edge, and shifts in on falling edge. Data is hold during the low level. 1 → Data shifts out on falling edge, and shifts in on rising edge. Data is hold during the high level. Bit 4 (SE) : SPI shift enable bit 0 → Reset as soon as the shifting is complete, and the next byte is ready to shift. 1 → Start to shift, and remain a 1 while the current byte is still being transmitted. NOTE This bit has to be reset by software. Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 25 EM78815 8-Bit Microcontroller Bit 5 (SRO) : SPI read overflow bit 0 → No overflow 1 → A new data is received while the previous data is still being hold in the SPIB register. In this situation, the data in SPIS register will be destroyed. To avoid setting this bit, users have to read the SPIB register even if only the transmission is implemented. Note that this can only occur in slave mode. Bit 6 (SPIE) : SPI enable bit 0 → Disable SPI mode 1 → Enable SPI mode Bit 7 (RBF) : SPI read buffer full flag 0 → Receive is not finished yet, SPIB is empty. 1 → Receive is finished, SPIB is full. Write R5 Read R5 RBF RBFI SPIWC SPIR reg. SPIW reg. set to 1 SPIE Buffer Full Detector SDI SDI/P62 M UX SPIS reg. shift right PORT62 bit 7 bit 0 SDO SDO/P61 M UX SPIC reg. (R4 page1) PORT61 Edge Select SPIE 0 3 SBR0 ~SBR2 Noise Filter SBR2~SBR0 3 2 Clock Select T sco Prescaler 4, 8, 16, 32, 64, 128 Edge Select SCK PORT60 16.38kHz MUX SCK/P60 SCK SPIE Fig. 13 SPI Structure 26 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller SPIC reg : SPI control register SDO/P61 : Serial data out SDI/P62 : Serial data in SCK/P60 : Serial clock RBF : Set by buffer full detector, and reset by software. RBFI : Interrupt flag. Set by buffer full detector, and reset in software. Buffer Full Detect : Set to 1, while an 8-bit shifting is complete. SE : Loads the data in SPIW register, and begins to shift SPIE : SPI control register SPIS reg. :Shifting byte out and in. The MSB will be shifted first. Both the SPIS register and the SPIW register are loaded at the same time. Once data is being written to, SPIS starts transmission / reception. The received data will be moved to the SPIR register, as the shifting of the 8-bit data is completed. The RBF (Read Buffer Full) flag and the RBFI (Read Buffer Full Interrupt) flag are set. SPIR reg. : Read buffer. The buffer will be updated as the 8-bit shifting is completed. The data must be read before the next reception is finished. The RBF flag is cleared as the SPIR register is read. SPIW reg. : Write buffer. The buffer will deny any write until the 8-bit shifting is completed. The SE bit will be kept in 1 if the communication is still undergoing. This flag must be cleared as the shifting is finished. Users can determine if the next write attempt is available. SBR2 ~ SBR0: Programs the clock frequency/rates and sources. Clock Select : Selects either the internal instruction clock or the external 16.338kHz clock as the shifting clock. Edge Select : Selects the appropriate clock edges by programming the SCES bit Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 27 EM78815 8-Bit Microcontroller SCK (SCES=0) SCK (SCES=1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SDO SDI RBF Shift data in Shift data out Clear by software Fig. 14 SPI Timing 7.2.14 R8 Port 8 I/O Data, Data ROM Address, DTMF Receiver, SPI Data 7.2.14.1 Page 0 Port 8 I/O Data Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P87 P86 P85 P84 P83 P82 P81 P80 R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X Bit 0 ~ Bit 7 (P80 ~ P87) : 8-bit Port 8 ( 0~7 ) I/O data register User can use the IOC register to define each bit either as input or output. 7.2.14.2 Page 1 Data ROM address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DRA15 DRA14 DRA13 DRA12 DRA11 DRA10 DRA9 DRA8 R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X Bit 0 ~ Bit 7 (DRA8 ~ DRA15) : Data ROM address ( 8~15 ) for ROM reading 28 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller 7.2.14.3 Page 2 DTMF Receiver Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CMPFLAG STD − − Q4 Q2 Q1 Q0 R R/W-0 × × R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 3 (Q1 ~ Q4) : DTMF receiver decoding data These provide the code corresponding to the last valid tone-pair received (see code table). The STD signal with steering output presents a logic high when a received tone-pair has been registered and the Q4 ~ Q1 output latch updated, and generates an interrupt (IOCF has enabled); returns to logic low when the voltage on ST/GT falls below Vtst. F low F high Key DREN Q4~Q1 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 Any 1209 1336 1477 1209 1336 1477 1209 1336 1477 1209 1336 1477 1633 1633 1633 1633 Any 1 2 3 4 5 6 7 8 9 0 * # A B C D Any 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 ×××× Note: “×” means unknown Bit 4~Bit 5 : Undefined Register Bit 6 (STD) : Delayed steering output Presents a logic high when a received tone-pair has been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below Vtst. 0/1 → Data invalid/data valid Be sure to open the main clock before using the DTMF receiver circuit. A logic ”0, 0” applied to R5 Page 3 B 4 and B 3 will shut down power of the device to minimize the power consumption in standby mode. It stops functions of the filters. Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 29 EM78815 8-Bit Microcontroller In many situations not requiring independent selection of received and paused, the simple steering circuit is applicable. Component values are chosen according to the following formula: t REC = t DP + t GTP t ID = t DA + t GTA The value of t DP is a parameter of the device and t REC is the minimum signal duration to be recognized by the receiver. A 0.1 µF value for C is recommended for most applications, leaving R to be selected by the designer. For example, a suitable value of R for a t REC of 30mS would be 300k. Different steering arrangements may be used to select independently the guard-times for tone-present (t GTP) and tone-absent (t GTA). This may be necessary to meet system specifications which place both accept and reject limits on both tone duration and inter digital pause. Guard-time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. Increasing t REC improves talk-off performance, since it reduces the probability that tones simulated by speech will maintain signal condition long enough to be registered. On the other hand, a relatively short t REC with a long t DO would be appropriate for extremely noisy environments where fast acquisition time and immunity to drop-outs would be required. VDD VDD C ST/GT EST R Fig. 15 DTMF Receiver Delay Time Control 30 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller TONE TONE Tdp 5~20mS by S/W EST Tgta 30mS Typ. Tgtp 30mS Typ. Vtst 1/2 VDD ST/GT Tpq 8 uS Typ. Q4..Q1 STD LINE_ENG Fig. 16 DTMF Receiver Timing Bit 7 (CMPFLAG) : Comparator output flag 0 → Input voltage < reference voltage 1 → Input voltage > reference voltage NOTE Refer to Sec. 7.2.16.3 RA Page 2 Comparator Control Register. 7.2.14.4 Page 3 SPI Data Buffer Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPIB7 SPIB6 SPIB5 SPIB4 SPIB3 SPIB2 SPIB1 SPIB0 R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X Bit 0 ~ Bit 7 (SPIB0 ~ SPIB7) : SPI data buffer If you write data to this register, the data will be written to the SPIW register. If you read this data, it will read the data from the SPIR register. Refer to Fig. 9. 7.2.15 R9 Port 9 I/O Data, Data ROM Address, Keytone Control 7.2.15.1 Page 0 Port 9 I/O Data Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P97 P96 P95 P94 P93 P92 P91 P90 R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 31 EM78815 8-Bit Microcontroller Bit 0 ~ Bit 7 (P90 ~ P97) : 8-bit Port 9 ( 0~7 ) I/O data register User can use the IOC register to define each bit either as input or output. 7.2.15.2 Page 1 Data ROM Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - DRA20 DRA19 DRA18 DRA17 DRA16 - - - R/W-X R/W-X R/W-X R/W-X R/W-X Bit 0 ~ Bit 4 (DRA16 ~ DRA20) : Data ROM address (16~20) for ROM reading.. Bit 5~Bit 7 : Unused 7.2.15.3 Page 2 FSK/CW/DTMF Power Select Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PCTRL1 PCTRL0 ADCS3 ADCS2 ADCS1 - - - R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 - - - Bit 0 ~ Bit 1 : Unused Bit 3 ~ Bit 5(ADCS1 ~ ADCS3) : PORT65 ~ Port 67 normal IO / CMP input control bit. ADCSX = 1 → Comparator input ADCSX = 0 → Normal IO Bit 6~Bit 7 (PCTRL0~PCTRL1) : FSK and DTMF power control bits PCTRL1 PCTRL0 Select 0 0 1 0 1 0 FSK and DTMFr power off FSK power on DTMF receiver power on 1 1 Cannot be used Relation Register RA Page 0 R8 Page 2 - * Do not set both the bits to 1, or FSK and DTMF function will fail. * When User turns on the DTMF receiver power, Port 60 and Port 61 will switch to /STGT and EST pin. 7.2.15.4 Page 3 Keytone Control Bit 7 Bit 6 URT8 URR8 R/W-X R Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DA1 DA0 URINV KT1 KT0 KTS R/W-X R/W-X R/W-X R/W-0 R/W-0 R/W-0 Bit 0 (KTS) : Key tone output switch 0 → Normal Port 76 1 → Keytone output 32 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller Bit 1 ~ Bit 2 (KT0 ~ KT1) : Keytone output frequency and its power control KT1 KT0 Keytone Frequency and Power 0 0 32.768kHz/32 = 1.024kHz clock and enable 0 1 32.768kHz/16 = 2.048kHz clock and enable 1 0 32.768kHz/8 = 4.096kHz clock and enable 1 1 Power-off keytone Bit 3 (URINV) : Enable UART TXD, RXD port inverse output 0 → Disable UART TXD, RXD port inverse output 1 → Enable UART TXD, RXD port inverse output Bit 4 ~ Bit 5 (DA0~DA1) : These two bits are the least significant bits of the Current DA. Combine R6 Page 3 and these 2 bits as complete 10 bits Current DA output data. Bit 6 (URR8) : MSB of UART receiver data buffer. Bit 7 (URT8) : MSB of UART transmitter data buffer. 7.2.16 RA CPU Power Saving, Main CLK Select, FSK, WDT Timer Comparator Control, Tone 1 Generator 7.2.16.1 Page 0 Power Saving, Main CLK Select, FSK, WDT Timer Bit 7 Bit 6 0 PLLEN R/W-0 R/W-0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CLK1 CLK0 ROMRI FSKDATA /CD WDTEN R/W-0 R/W-0 R/W-0 R R R/W-0 Bit 0 (WDTEN) : Watchdog control register User can use WDTC instruction to clear the watchdog counter. The counter's clock source is 32768/2 Hz. If the prescaler is assigned to TCC, the Watchdog will time out by (1/32768 )*2 * 256 = 15.616ms. If the prescaler is assigned to WDT, the time out will be more times depending on the prescaler ratio. 0/1 → disable/enable Bit 1 (/CD) : FSK carrier detect indication 0/1 → Carrier Valid/Carrier Invalid It is a read only signal. If the FSK decoder detects the energy of the marked or space signal, the Carrier signal will go to low level. Otherwise it will go to high. Note that this should be in normal mode. Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 33 EM78815 8-Bit Microcontroller Bit 2 (FSKDATA) : FSK decoding data output It is a read only signal. If the FSK decodes the mark or space signal, it will output a high level signal or low level signal at this register. It is a raw data type. That means the decoder just decodes the signal and has no process on the FSK signal. Note that this should be in normal mode. User can use FSK data falling edge interrupt function to help in data decoding. Example: MOV A,@01000000 IOW IOCF CLR RF ;enable FSK interrupt function ENI ;wait for FSK data's falling edge : 0 = Space data (2200 Hz) 1 = Mark data (1200 Hz) FSK block power is controlled by R5 Page 3 Bit 3, 4. When PCTRI1=0 and PCTRL0=1, FSK power is turned on. The relation between R5 Bit 3 to Bit 4 and RA Bit 1 to Bit 2 are shown in Fig.17. You have to power up the FSK decoder first, then wait for a setup time (Tsup) and check carrier signal (/CD). If the carrier is low, the program can process the FSK data. FIRST RING 2 SECONDS 0.5 SEC 0.5 SEC SECOND RING 2 SECONDS FSK signal TIP/RING Tcdh Tcdl /CD Tdoc FSKDATA DATA Tsup PCTRL0 PCTRL1 Fig. 17 Relationship between R5 Bit 3 to Bit 4 and RA Bit 1 to Bit 2 34 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller The controller is a CMOS device designed to support the Caller Number Deliver feature which is offered by the Regional Bell Operating Companies. The FSK block comprises one path: the signal path. The signal path consist of an input differential buffer, a band pass filter, an FSK demodulator and a data valid with carrier detect circuit. In a typical application, user can use his own external ring detect output as a triggering input to IO port. User can use this signal to wake up the chip by external ring detect signal. Setting “0, 1” to R5 B4 and B3 (PCTRL1 & PCTRL0) of the RA register activates the FSK decoder block. If B4 and B3 of register R5 is set to “0, 1”, the FSK decoder block will be powered down. The input buffer accepts a differential AC coupled input signal through the TIP and RING input and feeds this signal to a band pass filter. Once the signal is filtered, the FSK demodulator decodes the information and sends it to a post filter. The output data is then made available at Bit 2 (FSKData) of register RA. This data, as sent by the central office, includes the header information (alternate "1" and "0") and 150 ms of marking which precedes the date, time and calling number. If no data is present, the Bit 2 (Data) of register RA is held at “1” state. This is accomplished by a carrier detect circuit which determines if the in-band energy is high enough. If the incoming signal is valid, Bit 1 (/CD) of register RA will be “0” otherwise it will be held at “1”. Thus the demodulated data is transferred to Bit 2 (Data) of register RA. If it is not, then the FSK demodulator is blocked. Bit 3 (ROMRI) : External Data ROM read data address auto_increase enable. RO_IDEN ROMRI Result 0 × Regardless Read/Write external Data ROM, Address flag cannot increase or decrease. 1 0 Address flag will auto_increase or decrease after a Read/Write of the external Data ROM. 1 1 Address flag will auto_increase or decrease after a Write to the external Data ROM, but the address flag is constant after reading the external Data ROM. Bit 4 ~ Bit 5 (CLK0 ~ CLK1) : Main clock selection bits User can choose different frequency for the main clock by CLK1 and CLK2. All the clock selection is listed below. PLLEN CLK1 CLK0 Sub Clock Main Clock 1 1 1 1 0 0 0 0 0 0 1 1 Don’t care Don’t care Don’t care Don’t care 0 1 0 1 don’t care don’t care don’t care don’t care 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 5.374MHz 5.374MHz (Normal mode) 1.7913MHz 1.7913MHz (Normal mode) 10.7479MHz 10.7479MHz (Normal mode) 3.5826MHz 3.5826MHz (Normal mode) Don’t care 32.768kHz (Green mode) Don’t care 32.768kHz (Green mode) Don’t care 32.768kHz (Green mode) Don’t care 32.768kHz (Green mode) Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) CPU Clock 35 EM78815 8-Bit Microcontroller Bit 6 (PLLEN) : PLL enable control bit It is CPU mode control register. If PLL is enabled, the CPU will operate in normal mode (high frequency, main clock), otherwise it will run in green mode (low frequency, 32768 Hz). 0/1 → disable/enable 3.5826 MHz to analog circuit ÷ 2 =>1.7913MHz × 1 =>3.5826MHz × 1.5 => 5.374MHz × 3 =>10.7479MHz PLL Sub-clock 32.768kHz 1 switch 0 ENPLL System clock CLK1 ~ CLK0 Fig. 18 Relationship between 32.768kHz and PLL Bit 7: Unused Register. Always keep this bit to 0, otherwise some un-expected error will occur. Wake-up Signal TCC time out IOCF Bit 0=1 And "ENI" Counter 1 time out IOCF Bit 1=1 And "ENI" Counter 2 time out IOCF Bit 2=1 And "ENI" WDT time out Port 7 Any one bit in IOCE Page 0 = 1 And "ENI" DED interrupt IOCE page1 bit 6 = 1 And RF Bit 3 logic level variation (switch by EDGE bit) And “ENI” 36 • Sleep Mode Green Mode Normal Mode RA (7, 6) = (0, 0) + SLEP RA (7, 6) = (x, 0) no SLEP RA (7, 6) = (x, 1) no SLEP Interrupt (jump to Address 8 at Page 0) Interrupt (jump to Address 8 at Page 0) Interrupt (jump to Address 8 at Page 0) Interrupt (jump to Address 8 at Page 0) Interrupt (jump to Address 8 at Page 0) Interrupt (jump to address 8 at Page 0) RESET and Jump to Address 0 RESET and Jump to Address 0 RESET and Jump to Address 0 RESET and Jump to Address 0 Interrupt (jump to Address 8 at Page 0) Interrupt (jump to Address 8 at Page 0) No function Interrupt (jump to Address 8 at Page 0) Interrupt (jump to Address 8 at Page 0) No function No function No function Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller NOTE Port 70 ~ Port 76's wake-up function is controlled by IOCE Page 0 Bit 0~Bit 6 and ENI instruction. They are falling edge trigger. Port 77's wake-up function is controlled by IOCE Page 0 Bit 7. It can be triggered by a falling edge or rising edge (controlled by CONT register). 7.2.16.2 Page 1 Undefined Register: This register is not for use. 7.2.16.3 Page 2 Comparator Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CMPEN CMPREF CMPS1 CMPS0 CMPB3 CMPB2 CMPB1 CMPB0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 If user defines Port 63, Port 64 or Port 65 (by ADCS1, ADCS2, ADCS3 at R9 Page 2) as a comparator input or Port 6, then user can use this register to control the comparator's function. Bit 0~Bit 3(CMPB0 ~ CMPB3) : Reference voltage selection of the internal bias circuit for the comparator. Reference voltage for comparator = VDD x (N + 0.5) / 16, N = 0 to 15 Bit 4~Bit 5(CMPS0~CMPS1) : Channel selection from CMP1 to CMP3 for comparator CMPS1 CMPS0 Input 0 0 1 1 0 1 0 1 CMP1 CMP2 CMP3 Reserved Bit 6(CMPREF) : Switch for comparator reference voltage type 0 → internal reference voltage 1 → external reference voltage Bit 7(CMPEN) : Enable control bit of comparator. 0/1 → disable/enable, when CMPEN bit is set to “0” , the 2.0V ref circuit will be powered off. The relationship between these registers is shown in Fig.19. Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 37 EM78815 8-Bit Microcontroller P65/CMP1 CM P1 MUX PORT65 ADCS1 CMP2 P66/CMP2 MUX + MUX CMPFLAG PORT66 2 ADCS2 P67/CMP3 CMPS1 CMPS0 CMP3 MUX PORT67 1 0 ADCS3 MUX VDD V2_0 ref. MUX VR CMPREF 2.0V CMPEN CMPEN 1/2R 1111 VRSEL R 1110 R MUX 0000 1/2R 4 CMPB3 to CM PB0 Fig. 19 Comparator Circuit CMPEN CMP1 to CMP3 Reference Voltage Set-up time 10us CPU Clock CMPFLAG Compare Start Compare End Fig. 20 Comparator Timing 38 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller 7.2.16.4 Page 3 Tone 1 Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T17 T16 T15 T14 T13 T12 T11 T10 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0~Bit 7 (T10~T17) : Tone Generator 1 frequency divider and power control. Run in Normal mode. Clock source = 85300Hz T17~T10 = ‘11111111’ → Tone Generator 1 will has 334 (85300/255) Hz Sine wave output. : T17~T10 = ‘00000010’ → Tone Generator 1 will has 41150(85300/2) Hz Sine wave output. T17~T10 = ‘00000001’ → DC bias voltage output T17~T10 = ‘00000000’ → Power off Built-in tone generator can generate dialing tone signals for dialing tone type telephones or just a single tone. In DTMF application, there are two kinds of tones, One is the row frequency group (Tone 1), the other is the column frequency group (Tone 2). Each group has four kinds of frequency, user can get a total of 16 kinds of DTMF frequency. A Tone generator contains a row frequency sine wave generator for generating the DTMF signal which is selected by RA Page 3 and a column frequency sine wave generator for generating the DTMF signal which is selected by RB Page 3. This block can generate a single tone by filling one of these two registers. If all the values are low, the power of the tone generators will be turned off. Tone 2 (RB Page 3) High Group Freq. Tone 1 (RA page3) Low group freq. 699.2Hz (0x07A) 768.5Hz (0x06F) 853.0Hz (0x064) 937.4Hz (0x05B) 1201.4Hz 1332.8Hz 1470.7Hz 1640.4Hz (0X47) (0X40) (0X3A) (0X34) 1 2 3 A 4 5 6 B 7 8 9 C * 0 # D Tone 1 and Tone 2 are asynchronous tone generators and both can be used to generate Caller ID FSK signal. In FSK generator application, Tone 1 or Tone 2 can generate 1200Hz Mark bit and 2200Hz Space bit for Bell202 or 1300Hz Mark bit and 2100Hz Space bit for V.23. See the following table. Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 39 EM78815 8-Bit Microcontroller Tone 1 (IOCC Page 1) or Tone 2 (IOCD Page 1) Freq. (Hz) Description 0×47 0×27 0×42 0×29 1201.4 2187.2 1292.4 2080.5 Bell202 FSK Mark bit Bell202 FSK Space bit V.23 FSK Mark bit V.23 FSK Space bit The Tone generator can also generate CW or SMS signal. See the following table. Tone 1 (IOCC Page 1) or Tone 2 (IOCD Page 1) Freq. (Hz) Description 0×28 0×1F 2132.5 2751.6 CAS freq CAS freq 7.2.17 RB Port B I/O Data, Key Strobe, Tone 2 Generator 7.2.17.1 Page 0 Port B I/O Data Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X Bit 0 ~ Bit 7 (PB0 ~ PB7) : 8-bit Port B ( 0~7 ) I/O data register. User can use the IOC register to define each bit as either input or output. 7.2.17.2 Page 1 Undefined Register: This register is not for use. 7.2.17.3 Page 2 Key Strobe Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STRB7 STRB6 STRB5 STRB4 STRB3 STRB2 STRB1 STRB0 R R R R R R R R Bit 0 ~ Bit 7 (STRB0 ~ STRB7) : Key strobe control bits. These key strobe control registers correspond to Port 80 ~ Port 87. Refer to Keystobe explanation (RE Page 3). 7.2.17.4 Page 3 Tone 2 Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T27 T26 T25 T24 T23 T22 T21 T20 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0~Bit 7(T20~T27) : Tone Generator 1 frequency divider and power control. Refer to RA Page 3 Tone 1 control register for details. 40 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller 7.2.18 RC Port C I/O Data, Data RAM Data Buffer, Tone 2 Generator 7.2.18.1 Page 0 Port C I/O Data Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X Bit 0 ~ Bit 7 (PC0 ~ PC7) : 8-bit Port C ( 0~7 ) I/O data register User can use the IOC register to define each bit either as input or output. 7.2.18.2 Page 1 Data RAM Data Buffer 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RAM1D7 RAM1D6 RAM1D5 RAM1D4 RAM1D3 RAM1D2 RAM1D1 RAM1D0 R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X Bit 0 ~ Bit 7 (RAM1D0 ~ RAM1D7) : Data RAM data Buffer 1 for RAM reading or writing. Example. MOV A,@1 MOV RD_PAGE1,A MOV A,@0 MOV RE_PAGE1,A MOV A,@0x55 MOV RC_PAGE1,A MOV ;write data 0x55 to DATA RAM ;which is address "0001" A,RC_PAGE1 ;read data : 7.2.18.3 Page 2 Key Strobe Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STRB15 STRB14 STRB13 STRB12 STRB11 STRB10 STRB9 STRB8 R R R R R R R R Bit 0 ~ Bit 7 (STRB8 ~ STRB15) : Key strobe control bits These key strobe control registers correspond to Port 90 ~ Port 97. Refer to Key stobe explanation (RE Page 3). 7.2.18.4 Page 3 Undefined Register: This register is unimplemented, not for use. Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 41 EM78815 8-Bit Microcontroller 7.2.19 RD Port D I/O Data, Data RAM Address 7.2.19.1 Page 0 Port D I/O Data, Data RAM Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PD7 R/W-X PD6 R/W-X PD5 R/W-X PD4 R/W-X PD3 R/W-X PD2 R/W-X PD1 R/W-X PD0 R/W-X Bit 0 ~ Bit 7 (PD0 ~ PD7) : 7-bit Port D ( 0~6 ) I/O data register User can use the IOC register to define each bit either as input or output. 7.2.19.2 Page 1 Data RAM Address 1 (Low 8 bits) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RAM1A7 R/W-X RAM1A6 R/W-X RAM1A5 R/W-X RAM1A4 R/W-X RAM1A3 R/W-X RAM1A2 R/W-X RAM1A1 R/W-X RAM1A0 R/W-X Bit 0~Bit 7 (RAM1A0 ~ RAM1A7) : Data RAM address1 (Address 0 to Address 7) for RAM reading or writing 7.2.19.3 Page 2 Undefined Register 7.2.19.4 Page 3 Undefined Register These two register are unimplemented, not for use. 7.2.20 RE Interrupt Flag 1, Data RAM Address 1 (H) CAS, Key Scan 7.2.20.1 Page 0 Interrupt Flag 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Interrupt flag registers. User can only clear these bits from 1 to 0 but cannot set them from 0 to 1. Bit 0 (INT0) : External INT0 pin interrupt flag If Port 70 has a falling edge trigger signal, the CPU will set this bit. Bit 1 (INT1) : External INT1 pin interrupt flag If Port 71 has a falling edge trigger signal, the CPU will set this bit. Bit 2 (INT2) : External INT2 pin interrupt flag If Port 72 has a falling edge trigger signal, the CPU will set this bit. Bit 3 (INT3) : External INT3 pin interrupt flag If Port 73 has a falling edge trigger signal, the CPU will set this bit. Bit 4 (INT4) : External INT4 pin interrupt flag If Port 74 has a falling edge trigger signal, the CPU will set this bit. Bit 5 (INT5) : External INT5 pin interrupt flag If Port 75 has a falling edge trigger signal, the CPU will set this bit. 42 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller Bit 6 (INT6) : External INT6 pin interrupt flag If Port 76 has a falling edge trigger signal, the CPU will set this bit. Bit 7 (INT7) : External INT7 pin interrupt flag If Port 77 has a falling (or rising and falling) edge trigger signal, the CPU will set this bit. Signal INT0 : INT6 INT7 Trigger Remark Falling edge Falling/Falling & Rising Edge Controlled by CONT register 7.2.20.2 Page 1 Data RAM Address 1(H) Bit 7 Bit 6 Bit 5 Bit 4 − − − − × × × × Bit 3 Bit 2 Bit 1 RAM1A11 RAM1A10 RAM1A9 R/W-X R/W-X Bit 0 RAM1A8 R/W-X R/W-X Bit 0~Bit 3 (RAM1A8 ~ RAM1A11) : Data RAM address (Address 8 to Address 11) for RAM reading. Bit 4~Bit 7 Undefined Register. These registers are not certain whether 0 or 1. Do not use these registers. 7.2.20.3 Page 2 CAS Detected Flag, Keyscan Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CAS R − × Key strobe R/W-0 Keyscan R/W-0 LCD1 R/W-0 LCD0 R/W-0 − × − × Bit 0~Bit 1 : Undefined register. These bits are unimplemented, not for use. Bit 2~Bit 3 (LCD0~LCD1) : These two bits are used to enable/disable key scan and the LCD controller. LCD1 LCD0 0 0 0 1 1 0 1 1 Sates Keyscan disable (ignore Keyscan bit) External LCD controller disable Keyscan disable (ignore Keyscan bit) External LCD controller disable Keyscan disable (ignore Keyscan bit) External LCD controller disable Keyscan enable (Keyscan bit must = 1) External LCD controller enable Bit 4 (Keyscan) : Key scan function enable control bit. 0/1 → disable/enable If Keyscan function is enabled (LCD0, LCD1 and Keyscan =1), Port 8 and Port 9 will be pulled high automatically and become key strobe pins. Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 43 EM78815 8-Bit Microcontroller The key scan waveform is as follows. K ey scan pi n(P8,P9) V DD 30us GN D Fig.21 Keyscan Waveform Bit 5 (KEYSTRB) : Key strobe enable control bit 0/1 → disable/enable Key strobe signal , if you set this bit , the segment will switch to strobe signal temporally and output a zero signal ( one instruction long ) one by one from Port 80 to Port 87 and Port 90 to Port 97. During one strobe time, the CPU will check whether Port 7 (0:3) is equal to "1111" or not. If not, the CPU will latch a zero at RB Page 1 and RC Page 1 one by one depending on which segment strobe. After strobe, this bit will be cleared. Fig. 22 is a key strobe signal. One instruction REGISTER RB(0) STROBE PORT80 PORT81 PORT82 PORT83 PORT84 PORT85 PORT86 PORT87 PORT90 PORT91 PORT92 PORT93 PORT94 PORT95 PORT96 PORT97 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RB(1) RB(2) 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 RB(3) 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 RB(4) 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 RB(5) 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 RB(6) 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 RB(7) RC(0) RC(1) 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 RC(2) RC(3) 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 RC(4) 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 RC(5) 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 RC(6) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 RC(7) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Fig.22 Key strobe Signal 44 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller Bit 6 Unused The following figure shows the relationship between Keyscan, and Key strobe. Fig.24 is a Keyscan flow by interrupt trigger. Relationship Between Port 8, Port 9, Keyscan, Keystrobe Keyscan Pulse Keyscan Control 0 Port 8, Port 9 Key strobe Signal MUX 1 Key strobe Fig. 23 Keyscan, Key strobe and Segments Set Port 7(3:0) input Port 7 pull high Enable Keyscan signal Set INT0~INT3 interrupt ENI N Interrupt occur? Y Enable main clock (Normal mode) Program delay Execution Key function Analysis external interrupt (column key ) Set strobe function Enable Key strobe Program delay Read strobe data (row key) Get the Key location Fig. 24 Key Scan Flow By Interrupt Trigger Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 45 EM78815 8-Bit Microcontroller Bit 7 (CAS) : Call Waiting decoding output 0/1 → CW data valid / No data 7.2.20.4 Page 3 UART transmitter data buffer Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 URT7 URT6 URT5 URT4 URT3 URT2 URT1 URT0 R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X Bit 0~Bit 7(URT0~URT7) : Low 8-bit UART transmitter data buffer 7.2.21 RF Interrupt flag Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RBF/STD FSK/CW − UART DED CNT2 CNT1 TCC R/W-0 R/W-0 × R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Note: "1" means interrupt request "0" means non-interrupt Bit 0 (TCC) : TCC timer overflow interrupt flag Set when TCC timer overflows. Bit 1 (CNT1) : Counter 1 timer overflow interrupt flag Set when Counter 1 timer overflows. Bit 2 (CNT2) : Counter 2 timer overflow interrupt flag Set when Counter 2 timer overflows. Bit 3 (DED) : Differential Energy Detector (DED) Interrupt flag output data. If DEDD (RE Page 2 Bit 7) has a falling edge signal (or falling & rising edge signal, switch by IOCE Page 1 Bit 5), the CPU will set this bit. Bit 4 (UART) : Universal Asynchronous Receiver Transmitter interrupt flag. When the transmitter buffer is empty, receiver buffer full or receiver data error, this bit will be set. Bit 5: Undefined register. These bits are unimplemented, not for use. Bit 6 (FSK/CW) : FSK data or Call waiting data interrupt flag. If FSKDATA or CAS has a falling edge trigger signal, the CPU will set this bit. Bit 7 ( RBF/STD) : SPI data transfer complete or DTMF receiver signal valid interrupt If serial IO's RBF signal has a rising edge signal (RBF set to "1" when data is transferred completely), the CPU will set this bit. Or when the DTMF receiver’s STD signal has a rising edge signal (the DTMF decodes a DTMF signal). IOCF is the interrupt mask register. User can read and clear. 46 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller Trigger edge is shown in the following table: Signal Trigger TCC Time out Remark Counter 1 Time out Counter 2 Time out DED FSK Signal detect Receiver full, Transmitter empty or error (if enabled) Falling edge RBF/STD Rising edge UART 8/16 bits select by CONT register EM78815 MCU will store ACC, R3 status and R5 Page automatically after an interrupt is triggered. It will be restored after instruction “RETI”. 7.2.21.1 Page 1 External Data ROM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXA8 EXA7 EXA6 EXA5 EXA4 EXA3 EXA2 EXA1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0~Bit 7(EXA1~EXA8) : Expanding Data ROM start address A1~A8 7.2.21.2 Page 2 External Data ROM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXA16 EXA15 EXA14 EXA13 EXA12 EXA11 EXA10 EXA9 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0~Bit 7(EXA9~EXA16) : Expanding Data ROM start address A9~A16,,IOCB Page 1 Bit 7 is the MSB (EXA17) for Expanding Data ROM start address. 7.2.21.3 Page 3 Unused 7.2.22 R10~R3F (General Purpose Register) R10~R3F (Banks 0 ~ 3) : All of them are general purpose registers 7.3 Special Purpose Registers 7.3.1 A (Accumulator) Internal data transfer, or instruction operand holding It's not an addressable register. Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 47 EM78815 8-Bit Microcontroller 7.3.2 CONT (Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INT/EDGE INT TS DAEN PAB RSR2 RSR1 RSR0 Bit 0 ~ Bit 2 (PSR0 ~ PSR2) : TCC/WDT prescaler bits PSR2 PSR1 PSR0 TCC Rate WDT Rate 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 Bit 3 (PAB) : Prescaler assigned bit 0/1 → TCC/WDT Bit 4 (DAEN) : Current DA enable control 0/1 → disable/enable Bit 5 (TS) : TCC signal source Instruction clock / 16.384kHz Instruction clock = MCU clock/2, Refer to RA Bit 4 ~ Bit 6 for PLL and Main clock selection. See Fig.15. Bit 6 (INT) : INT enable flag 0 → interrupt masked by DISI or hardware interrupt 1 → interrupt enabled by ENI/RETI instructions Bit 7(INT_EDGE) : interrupt edge type of P77 0 → P77 's interrupt source is a rising and falling edge signal. 1 → P77 's interrupt source is a falling edge signal. The CONT register is readable (CONTR) and writable (CONTW). There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC only or WDT only at the same time. An 8-bit counter is available for TCC or WDT determined by the status of Bit 3 (PAB) of the CONT register. See the prescaler ratio in the CONT register. Fig. 25 depicts the circuit diagram of TCC/WDT. Both TCC and prescaler will be cleared by instructions which write to TCC each time. The prescaler will be cleared by the WDTC and SLEP instructions, when in WDT mode. The prescaler will not be cleared by SLEP instructions, when in TCC mode. 48 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller Data Bus Instruction clock 16.384kHz M U X M U X TS WDTE TCC(R1) TCC overflow interrupt PAB M U X W DT SYNC 2 cycles 8-bit Counter PSR0 ~ PSR2 8-to-1 MUX PAB MUX PAB WDT timeout Fig. 25 Block Diagram of TCC and WDT 7.3.3 IOC5 Address Automatic Increase/Decrease Control, Data RAM Data Buffer 2 7.3.3.1 Page 0 Address Automatic Increase/Decrease control register Bit 7 Bit 6 Bit 5 Bit 4 DA2_ID R/W-1 DA1_ID R/W-1 DO_ID R/W-1 − × Bit 0 : Bit 3 Bit 2 Bit 1 DA2_IDEN DA1_IDEN DO_IDEN R/W-0 R/W-0 R/W-0 Bit 0 − × Undefined register, not for use Bit 1 (DO_IDEN) : Enable Data ROM address flag Increase/Decrease Enable Function. If this bit is set, the Data ROM address will increase or decrease after accessing (read or write) the Data ROM. When Expanded Data ROM is used, user can read or write into the external memory. By controlling RA Page 0 Bit 3, address auto increase/decrease function can be changed. Refer to RA Page 0 for detailed description. 1/0 → Enable / Disable Bit 2 (DA1_IDEN) : Enable Data RAM address Flag 1 (RD and RE register) Increase/Decrease Enable Function. If this bit is set, the Data RAM address will increase or decrease after accessing (read or write) the Data RAM (RC register). 1/0 → Enable / Disable Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 49 EM78815 8-Bit Microcontroller Bit 3 (DA2_IDEN) : Enable Data RAM Address Flag 2 (IOC6 and IOC7) Increase/Decrease Enable Function. If this bit is set, the Data RAM address will increase or decrease after accessing (read or write) the Data RAM (IOC5 register). 1/0 → Enable / Disable Bit 4 : Undefined register, not for use. Bit 5 (DO_ID) : Data ROM address automatic increase/decrease switch. Set to 1 means auto_increase, clear to 0 means auto_decrease. 1/0 → auto increase / auto decrease Bit 6 (DA1_ID) : Data RAM address (RD and RE register) automatic increase/decrease switch. Set to 1 means auto_increase, clear to 0 means auto_decrease. 1/0 → auto increase / auto decrease Bit 7 (DA2_ID) : Data RAM address (IOC6 and IOC7 register) automatic increase/decrease switch. Set to 1 means auto_increase, clear to 0 means auto_decrease. 1/0 → auto increase / auto decrease 7.3.3.2 Page 1 Data RAM Data Buffer 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RAM2D7 RAM2D6 RAM2D5 RAM2D4 RAM2D3 RAM2D2 RAM2D1 RAM2D0 R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X Bit 0 ~ Bit 7 (RAM1D0 ~ RAM1D7) : Data RAM buffer for RAM reading or writing. Location RC~RE Page 2, user can move a large number of continuous data from an address to another into the data RAM. Example (move data from 0x0000 to 0x1000): BC MOV R3,@5 A , @0xF0 IOW BS BS BC MOV 0x05 R3 , @5 R3 , @6 R3 , @7 A , @0x00 MOV MOV 50 • ;Enable Data RAM Flag 1 and Flag 2 ;auto_increase function :Set corresponding page ;Assign Data RAM Index 1 ;start address ”0x0000” 0x0D , A 0x0E , A Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller IOW 0x06 MOV IOW MOV IOW MOV IOW : : ; Assign DATA RAM Index 2 start ; address ”0x1000” A , @0x10 0x07 A , 0x0C 0x05 A , 0x0C 0x05 ;Read data from Index 1(address:0x0000) ;Write data to Index 2(address:0x1000) ;Read data from Index 1(address:0x0001) ;Write data to Index 2(address:0x1001) 7.3.4 IOC6 Port 6 I/O Control, Data RAM Address (L) 7.3.4.1 Page 0 Port 6 I/O Control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOC67 IOC66 IOC65 IOC64 IOC63 IOC62 IOC61 IOC60 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit 0~Bit 7 (IOC60 ~ IOC67) : Port 6 (0~7) I/O direction control register 0 → put the relative I/O pin as output 1 → put the relative I/O pin into high impedance 7.3.4.2 Page 1 Data RAM Address 2 (L) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RAM2A7 RAM2A6 RAM2A5 RAM2A4 RAM2A3 RAM2A2 RAM2A1 RAM2A0 R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X Bit 0~Bit 7 (RAM2A0 ~ RAM2A7) : Data RAM address (Address 0 to Address 7) for RAM reading or writing 7.3.5 IOC7 PORT 7 I/O Control, Data RAM Address 2 (H) 7.3.5.1 Page 0 Port 7 I/O Control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOC77 IOC76 IOC75 IOC74 IOC73 IOC72 IOC71 IOC70 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit 0~Bit 7 (IOC70 ~ IOC77) : Port 7(0~7) I/O direction control register 0 → relative I/O pin as output 1 → relative I/O pin into high impedance 7.3.5.2 Page 1 Data RAM Address 2 (H) Bit 7 Bit 6 Bit 5 Bit 4 − − − − × × × × Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) Bit 3 Bit 2 Bit 1 RAM2A11 RAM2A10 RAM2A9 R/W-X R/W-X R/W-X Bit 0 RAM2A8 R/W-X 51 EM78815 8-Bit Microcontroller Bit 0~Bit 3 (RAM2A8 ~ RAM2A11) : Data RAM address (Address 8 to Address 11) for RAM reading or writing Bit 4~Bit 7 : Undefined register, not for use. 7.3.6 IOC8 Port 8 I/O Control 7.3.6.1 Page 0 Port 8 I/O Control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOC87 IOC86 IOC85 IOC84 IOC83 IOC82 IOC81 IOC80 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit 0 ~ Bit 7 (IOC80 ~ IOC87) : Port 8 (0~7) I/O direction control register 0 → puts the relative I/O pin as output 1 → puts the relative I/O pin into high impedance 7.3.6.2 Page 1 Undefined register This register is unimplemented, not for use. 7.3.7 IOC9 Port 9 I/O Control 7.3.7.1 Page 0 Port 9 I/O Control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOC97 IOC96 IOC95 IOC94 IOC93 IOC92 IOC91 IOC90 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit 0 ~ Bit 7 (IOC90 ~ IOC97) : Port 9 (0~7) I/O direction control register 0 → puts the relative I/O pin as output 1 → puts the relative I/O pin into high impedance 7.3.7.2 Page 1 Undefined register This register is unimplemented, not for use. 7.3.8 IOCA Undefined Register IOCA Page 0 and Page 1 are unimplemented, not for use. 52 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller 7.3.9 IOCB Port B I/O Control, External LCD Driver Interface (for EMC 65x132) 7.3.9.1 Page 0 Port B I/O Control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit 0~Bit 7 (IOCB0~IOCB7) : Port B(0~7) I/O direction control register 0 → puts the relative I/O pin as output 1 → puts the relative I/O pin into high impedance 7.3.9.2 Page 1 External LCD Driver Controller Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXA17 CWPWR × × CSS CSSON DIS EXLCD R/W-0 R/W-0 × × R/W-0 R/W-0 R/W-0 R/W-0 Bit 0(EXLCD) : External LCD driver enable/disable 0/1 → Port B, Port C normal IO/External LCD driver control (RE Page 2 LCD0, LCD1 = 1) If EXLCD is equal to 0, Port B and Port C output are normal IO. When EXLCD is equal to 1, Port B and Port C are switch to external LCD driver control pin. At this time, when user executes a read or write Port B instruction, Port C timing characteristic is shown below: Tah A0(PC4) CS (PC0/PC1) Taw Tcyc WR(PC2)/ RD(PC3) Tcc Tdh Tds Port B Data Toh Port B Tacc Data Fig. 26 Timing Characteristics of the External LCD Driver Data Read/Write Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 53 EM78815 8-Bit Microcontroller Symbol Rated Value Applicable Pins Unit Min. Max. Tah A0 0 - Taw A0 0 - Tcyc A0 150 - Tcc WR/RD 60 - Tds D0 ~D7 20 - Tdh D0 ~D7 10 - Tacc D0 ~D7 - 60 Toh D0 ~D7 10 40 ns Tah : Address hold time Taw : Address set-up time Tcyc : System cycle time Tcc : Pulse width Tds : Data set-up time Tdh : Data hold time Tacc : Read access time Toh : Output disable time User can operate in coordination with the on-chip Data ROM address automatic increase function to write a large number of data from the internal Data ROM to the external LCD RAM. Example ( To collocate EM9L8580 LCD driver ): START: 54 • MOV A , @0x0C; IOW IOC5_PAGE0 MOV A , @0x09 IOW IOCB_PAGE1 MOV A , @0xB0; MOV RB_PAGE0 , A MOV A , @0x10 MOV RB_PAGE0 , A MOV A , @0x00 MOV RB_PAGE0 , A MOV A , @0x00; ;Set Data ROM address automatic increase ;after read/write data ;External LCD driver Chip 1 Instruction mode ;select ;Set external LCD driver start address Page 0 ; Set external LCD driver start address Column 0 Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller MOV R7_PAGE1 , A; MOV R8_PAGE1 , A; MOV R9_PAGE1 , A MOV A , @0x0B IOW IOCB_PAGE1 ;select data mode MOV A , R6_PAGE1 ;read data from Data ROM and address flag ;increase MOV RB_RAGE0 , A ;write data to external LCD driver ;Start address: 0x00000 CN1: JMP LOOP Bit 1 (DIS) : External LCD driver Data/Instruction switch 0/1 → Instruction/Data When EXLCD is equal to 1 and DIS bit equal to 0, the MCU will transmit/receive instruction. A0 (Port C7) will output a “0”. If the DIS bit is set to 1, the MCU will transmit/receive data. A0 (Port C4) will output a “1”. Bit 2 (CSSON) : External LCD driver select enable CSSON CSS0 0 1 1 CS1..CS2 Low High × − CS1, CS2 0 CS1 CS2 1 CS2 CS1 Example for EMC 65x132 LCD driver : MOV A, @0x01 IOW IOCB_PAGE1 MOV A,@0xB0 MOV RB,A MOV A,@0x10 MOV RB,A MOV A,@0x00 MOV RB,A MOV A,@0x03 IOW IOCB_PAGE1 MOV A,@0xFF MOV RB,A ;Select external LCD driver & Instruction ;mode ;Select external LCD driver COM0 ;Select external LCD driver SEG Upper 4 bit = 0 ;Select external LCD driver SEG Lower 4 bit = 0 ;Switch to DATA mode ;Write 0xFF to COM0 &SEG0 : Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 55 EM78815 8-Bit Microcontroller User must assign an external LCD address for the first time. After writing or reading the display data, the Segment address is automatically incremented. Hence, the MCU can continuously write or read data to the address. Bit 3 (CSS) : External LCD driver chip select bit 0/1 → Chip 1 / Chip 2 Bit 4 ~ Bit 5 : Unused Bit 6(CWPWR) : CAS Decoder Power Control 0/1 → Power off / Power on Bit 7 (EXA17) : Expanded Data ROM start address MSB. This bit can be set only at the connected pin ”EXSAL” to VDD. 7.3.10 IOCC Port C I/O Control, Port 6 Pull-high Register 7.3.10.1 Page 0 Port C I/O Control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOCC7 IOCC6 IOCC5 IOCC4 IOCC3 IOCC2 IOCC1 IOCC0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit 0~Bit 7 (IOCC0~IOCC7) : Port C (0~7) I/O direction control register 0 → puts the relative I/O pin as output 1 → puts the relative I/O pin into high impedance 7.3.10.2 Page 1 Port 6 Pull-high Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PH67 PH66 PH65 PH64 PH63 PH62 PH61 PH60 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0~Bit 7(PH60~PH67) : PORT6(0~7) pull high control register 0 → disable pull-high function 1 → enable pull-high function 7.3.11 IOCD Port D I/O Control, Port 7 Pull-high Register 7.3.11.1 Page 0 Port D I/O Control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOCD7 R/W-1 IOCD6 R/W-1 IOCD5 R/W-1 IOCD4 R/W-1 IOCD3 R/W-1 IOCD2 R/W-1 IOCD1 R/W-1 IOCD0 R/W-1 Bit 0~Bit 6 (IOCD0~IOCD6) : Port D (0~6) I/O direction control register 0 → puts the relative I/O pin as output 1 → puts the relative I/O pin into high impedance 56 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller 7.3.11.2 Page 1 Port 7 Pull High Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PH77 R/W-0 PH76 R/W-0 PH75 R/W-0 PH74 R/W-0 PH73 R/W-0 PH72 R/W-0 PH71 R/W-0 PH70 R/W-0 Bit 0~Bit 7(PH70~PH77) : Port 7(0~7) pull high control register 0 → disable pull-high function 1 → enable pull-high function 7.3.12 IOCE Interrupt Mask, Differential Energy Detect 7.3.12.1 Page 0 Interrupt Mask Register 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 1 Bit 0 Bit 0~Bit 7 : Interrupt enable bits 0/1 → disable interrupt/enable interrupt 7.3.12.2 Page 1 Differential Energy Detect Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 VRSEL DEDD EDGE WUEDD CW_SMB DEDCLK R/W-0 R R/W-0 R/W-0 R/W-0 R/W-0 DEDPWR DEDTHD R/W-0 R/W-0 Bit 0 (DEDTHD) : Minimum detection threshold for Differential Energy Detector (DED) 0/1 → -45dBm/-30dBm Bit 1 (DEDPWR) : Power control of Differential Energy Detector (DED) 0/1 → Power off / Power on Bit 2 (DEDCLK) : Operating clock for Differential Energy Detector (DED) 0/1 → 32.768kHz/3.5826 MHz This bit is used to select operating clock for the Differential Energy Detector (DED). When this bit is set to “1”, the PLL is also enabled regardless of RA Bit 6 (ENPLL). During this time, the Energy detector works at high frequency mode. When this bit is set to “0”, the Energy Detector works at a low frequency mode. The difference between high frequency and low frequency is as follows. DEDPWR DEDCLK ENPLL Energy Detector Clock Main CLK 0 × × × Determined by ENPLL 1 0 0 32.768 kHz Disable 1 0 1 32.768 kHz Enable 1 1 0 3.5826 MHz Enable 1 1 1 3.5826 MHz Enable Note: ”×” means don’t care Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 57 EM78815 8-Bit Microcontroller Bit 3(CW_SMB) : Call Waiting / short message receiver switch 0 → Short message mode select ± 5.5% CAS tone accepted frequency range deviation. (Protocol: ± 5%) 1 → Call Waiting mode select ± 2.0% CAS tone accepted frequency range deviation. Bit 4 (WUEDD) : Wake-up control for the Energy Detector (DED) output data 1/0 → enable/disable Bit 5 (EDGE) : Wake-up and interrupt trigging edge control of the Energy Detector (DED) output 1/0 → Rising edge and Falling edge trigger / Falling edge trigger Bit 6(DEDD) : Output data for Differential Energy Detector (DED). If the input signal from TIP/EGIN1 and RING/EGIN2 pins to Differential Energy Detector is over the threshold level setting at IOCE Page 2 Bit 0 (DEDTHD), the DED will extract the zero-crossing pulse waveform corresponding to the input signal. Bit 7 (VRSEL) : Reference voltage VR selection bit for Comparator 0 → VR = VDD 1 → VR = 2.0V When this bit is set to “0”, V2_0 reference circuit will be powered off. The 2.0V reference circuit is only powered on when this bit and RA Page 2 bit 7 (CMPEN) are all set to “1”. 7.3.13 IOCF Interrupt Mask Register 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RBF/STD FSK/CW − UART DED CNT2 CNT1 TCC R/W-0 R/W-0 × R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0~Bit 7 : Interrupt enable bits 0/1 → Disable interrupt/enable interrupt 58 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller 7.4 I/O Port PCRD PORT Q P R Q C L Q P R Q C L D CLK PCWR IOD D CLK PDWR PDRD 0 1 M U X Fig. 27 I/O Port and I/O Control Register Circuit The I/O registers are bi-directional tri-state I/O ports. The I/O ports can be defined as "input" or "output" pins by the I/O control registers under program control. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuit is shown in Fig. 27. * The MCU will have a large current consumption when the IO is set to input and at floating state. Be careful to set unused IO to output or connect them to VDD or GND when they are set to input status. Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 59 EM78815 8-Bit Microcontroller 7.5 Reset The Reset can be caused by: (1) Power-on voltage detector reset (POVD) and power on reset (2) WDT time-out (if enabled and in Green or Normal mode) (3) /Reset pin pull low NOTE In Case (1), the POVD is controlled by Code Option. If you enable POVD, the CPU will reset at 2V and below, thus, the CPU will consume more current, which is 3µA. The power-on reset circuit is always enabled. It will reset the CPU at 1.4V and consume 0.5µA. Once a Reset occurs, the following functions are performed: 60 • The oscillator is running, or will be started The Program Counter (R2) is set to all "0" When powered on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared The Watchdog timer and prescaler counter are cleared The Watchdog timer is disabled The CONT register is set to all "1" The other register (Bit 7 ~ Bit 0) Address R Register Page 0 R Register Page 1 R Register Page 2 R Register Page 3 IOC Register Page 0 IOC Register Page 1 1 ×××× ×××× 0000 0000 0000 0000 ×××× ×××× -- -- 4 00×× ×××× ×××× ×××× ×××× ×××× ×××× ×××× -- -- 5 ×000 0000 0000 0000 0000 0000 ×××× 0000 1111 0000 ×××× ×××× 6 ×××× ×××× ×××× ×××× 0000 0000 0000 0000 1111 1111 ×××× ×××× 7 ×××× ×××× ×××× ×××× 0000 0000 0000 0000 1111 1111 ×××× ×××× 8 ×××× ×××× ×××× ×××× ×××× 0000 ×××× ×××× 1111 1111 00000000 9 ×××× ×××× ×××× ×××× 0000 0××× ×××× ×000 1111 1111 00000000 A 0000 0××0 ×××× ×××× 0000 0000 0000 0000 ×××× ×××× ×××× ×××× B ×××× ×××× ×××× ×××× 1111 1111 0000 0000 1111 1111 00×× 0000 C ×××× ×××× ×××× ×××× 1111 1111 ×××× ×××× 1111 1111 0000 0000 D ×××× ×××× ×××× ×××× ×××× ×××× ×××× ×××× 1111 1111 0000 0000 E 0000 0000 ×××× ×××× ××00 ×××× ×××× ×××× 0000 0000 0×00 0000 F 00×× 0000 0000 0000 0000 0000 ×××× ×××× 0000 0000 -- Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller 7.6 Wake-up The controller provides a power saving mode: (1) Sleep mode, RA (7) = 0 + "SLEP" instruction The controller will turn off all the CPU and crystal. User has to turn off by software all the other circuits with power control like Keytone control or PLL control (which has an enable register). Wake-up from Sleep mode: (1) WDT time out (2) External interrupt (3) /Reset pull low All these cases will reset the controller, and run the program at address zero. The status is the same as that of the power-on reset. 7.7 Interrupt RE and RF are the interrupt status registers which record the interrupt request in flag bits. The IOCE and IOCF are the interrupt mask registers. The TCC timer, Counter 1 and Counter 2 are internal interrupt sources. P70 ~ P77 (INT0 ~ INT7) are external interrupt input with external interrupt sources. If the interrupts come from these interrupt sources, then the RE or RF register will generate a '1' flag to the corresponding register if the IOCE or IOCF registers are enabled. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (when enabled) is generated, it will cause the next instruction to be fetched from address 008H. Once in the interrupt service routine, the source of the interrupt can be determined by polling the flag bits in the RE and RF registers. The interrupt flag bit must be cleared by software before leaving the interrupt service routine and enabling interrupts, to avoid recursive interrupts. 7.8 Instruction Set Instruction set has the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as general register. That is, the same instruction can operates on I/O register. The symbol "R" represents a register designator which specifies which one of the 64 registers (including operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit, located in the register "R'', affected by the operation. "k'' represents an 8 or 10-bit constant or literal value. Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 61 EM78815 8-Bit Microcontroller Legend: addr: address b: bit Binary Instruction i: Table pointer control p: special file register (0h~1Fh) k: constant r: File Register Hex Mnemonic 0000 0001 0010 0011 0100 rrrr 0000 0001 0010 0000 0001 0002 0003 0004 000r 0010 0011 0012 NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET 0 0000 0001 0011 0013 RETI 0 0000 0001 0100 0 0000 0001 rrrr 0014 001r CONTR IOR R 0 0000 0010 0000 0020 TBL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 0001 0001 0001 0001 0010 0010 0010 0010 0011 0011 0011 0011 0100 0100 01rr 1000 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr rrrr 0000 rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R 0 0 0 0 0 0 0100 0100 0101 0101 0101 0101 10rr 11rr 00rr 01rr 10rr 11rr rrrr rrrr rrrr rrrr rrrr rrrr 04rr 04rr 05rr 05rr 05rr 05rr COMA R COM R INCA R INC R DJZA R DJZ R 0 0110 00rr rrrr 06rr RRCA R 0 0110 01rr rrrr 06rr RRC R 0 0110 10rr rrrr 06rr RLCA R 0 0110 11rr rrrr 06rr RLC R 0 0 0 0 0 0 0 0 0 62 • 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 Operation No Operation Decimal Adjust A A → CONT 0 → WDT, Stop oscillator 0 → WDT A → IOCR Enable Interrupt Disable Interrupt [Top of Stack] → PC [Top of Stack] → PC Enable Interrupt CONT → A IOCR → A R2 + A → R2 bits 9, 10 do not clear A→R 0→A 0→R R-A → A R-A → R R-1 → A R-1 → R A∨R→A A∨R→R A&R→A A&R→R A⊕R→A A⊕R→R A+R→A A+R→R R→A R→R /R → A /R → R R+1 → A R+1 → R R-1 → A, skip if zero R-1 → R, skip if zero R(n) → A(n-1) R(0) → C, C → A(7) R(n) → R(n-1) R(0) → C, C → R(7) R(n) → A(n+1) R(7) → C, C → A(0) R(n) → R(n+1) R(7) → C, C → R(0) Status Affected Instruction Cycle None C None T, P T, P None None None None 1 1 1 1 1 1 1 1 2 None 2 None None 1 1 Z, C, DC 2 None Z Z Z, C, DC Z, C, DC Z Z Z Z Z Z Z Z Z, C, DC Z, C, DC Z Z 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Z Z Z Z None None 1 1 1 1 2 if skip 2 if skip C 1 C 1 C 1 C 1 Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller Binary Instruction Hex Mnemonic 0 0111 00rr rrrr 07rr SWAPA R 0 0 0 0 0 0 0 rrrr rrrr rrrr rrrr rrrr rrrr rrrr 07rr 07rr 07rr 0××× 0××× 0××× 0××× SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b 1 00kk kkkk kkkk 1kkk CALL k 1 1 1 1 1 1 1 kkkk kkkk kkkk kkkk kkkk kkkk kkkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k 1 1110 0000 0001 1E01 INT 1 1110 1kkk kkkk 1 1111 kkkk kkkk 1E8k 1Fkk PAGE k ADD A,k 0111 0111 0111 100b 101b 110b 111b 01kk 1000 1001 1010 1011 1100 1101 01rr 10rr 11rr bbrr bbrr bbrr bbrr kkkk kkkk kkkk kkkk kkkk kkkk kkkk Operation R(0-3) → A(4-7) R(4-7) → A(0-3) R(0-3) ↔ R(4-7) R+1 → A, skip if zero R+1 → R, skip if zero 0 → R(b) 1 → R(b) if R(b)=0, skip if R(b)=1, skip PC+1 → [SP] (Page, k) → PC (Page, k) → PC k→A A∨k→A A&k→A A⊕k→A k → A, [Top of Stack] → PC k-A → A PC+1 → [SP] 001H → PC K→R5(4:0) k+A → A Status Affected Instruction Cycle None 1 None None None None None None None 1 2 if skip 2 if skip 1 1 2 if skip 2 if skip None 2 None None Z Z Z None Z, C, DC 2 1 1 1 1 2 1 None 1 None Z, C, DC 1 1 Note: One instruction cycle = 2 main clock 7.9 Code Option Register The controller has one Code option register which is not part of the normal program memory. The option bits cannot be accessed during normal program execution. 7.9.1 Code Option Register 1 (Program ROM) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 − − − − − − /DED /POVD Bit 0 (/POVD) : Power-on Voltage Detector 0/1 → Enable / disable the Voltage Detector /POVD 2.2V /POVD Reset Voltage 2.2V Power-on Reset Voltage Sleep Mode Current (VDD=5V) 1 No Yes (2.2V) 1µA 0 Yes (2.2V) No 15µA Bit 1(/DED) : Differential Energy Detect function enable bit 0/1 → Enable / disable DED function Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 63 EM78815 8-Bit Microcontroller 7.10 Call Waiting Function Description TIP DATA FSK demodulator RING /CD GAIN CWTIP + Vdd/2 Filter Detection block CAS Voltage reference Fig.28 Call Waiting Block Diagram Call Waiting service works by alerting a customer engaged in a telephone call to a new incoming call. This way the customer can still receive important calls while engaged in a current call. The Call Waiting Decoder can detect CAS (Call-Waiting Alert Signal 2130Hz plus 2750Hz) and generate a valid signal on the data pins. The call waiting decoder is designed to support the Caller Number Deliver feature, which is offered by regional Bell Operating Companies. In a typical application, after enabling the CW circuit (by R5 Page 3 Bit 3 & Bit 4 ) this IC receives Tip and Ring signals from twisted pairs. The signals as inputs by the preamplifier, and the amplifier sends input signal to a band pass filter. Once the signal is filtered, the Detection block decodes the information and sends it to RE Page 2 Bit 7. The output data is made available at RE CAS bit. The data is CAS signals. The CAS is normal high. When this IC detects a 2130Hz and a 2750Hz frequency, the CAS pin goes to low. 64 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller 7.11 Differential Energy Detector (DED) EGIN1 EGIN2 DEDD DED DEDPWR DEDTHD EGCLK Fig.29 DED Block Diagram The Differential Energy Detector is differential input level and zero crossing detector named as DED. It can detect any incoming AC signal above its threshold level and outputs a corresponding zero-crossing frequency pulse. For this energy detector, user can set its minimum detection threshold level at –35dBm or –45dBm through the DEDTHD bit. All the minimum detection value can be achieved under an input capacitor of more than 4700 pF and input resistor of 100 kΩ. The energy detector can be power-controlled by IOCE Page 1 Bit 1 (DEDPWR). Register bits of the Energy Detector : Register Bits Descriptions RF Page 0 Bit 3 (DED) DED : Interrupt flag of DED output data IOCE Page 1 Bit 7 (DEDD) DEDD : Output data of DED IOCE Page 1 Bit 5 (EDGE) IOCE Page 1 Bit 4 (WUEDD) IOCE Page 1 Bit 6 (DED) IOCE Page 1 Bit 0 (DEDTHD) IOCE Page 1 Bit 1 (DEDPWR) EDGE : edge control of DED output data 1/0 → Falling edge trig. / Rising edge and Falling edge trig. WUEDD : Wake-up control of DED output data 1/0 → enable/disable DED : Interrupt mask of DED output data 1/0 → enable/disable interrupt of DED output data DEDTHD : Minimum detection threshold of DED 0/1 → -45dBm/-30dBm DEDPWR : Power control of DED 0/1 → power off/power on DEDCLK : operating clock of DED 0 : low frequency clock 1 : high frequency clock IOCE Page 1 Bit 2 (DEDCLK) Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 65 EM78815 8-Bit Microcontroller 8 Absolute Maximum Ratings Rating Symbol Min. VDD -0.3 Input Voltage Vin VDD-0.5 Operating Temperature Range Ta 0 DC Supply Voltage 9 Typ. Max. Unit 6 V VDD VDD+0.5 V 25 70 °C DC Electrical Characteristic (Operation current consumption for Analog circuit) Parameter Symbol Condition Min. Typ. Max. Unit Operation current for FSK I_FSK VDD=3V, CID power on − 1.5 2.5 mA Operation current for CW I_CW VDD=5V, CID power on − 1.5 2.5 mA Operation current for DTMF Receiver I_DR VDD=3V, DTMFr power on − 1.5 2.5 mA I_DTMF VDD=3V, DTMF power on − 0.5 0.8 mA VDD=3V, CDA power on − 1.5 4 mA VDD=5V, PT power on − 0.1 − mA Min. Typ. Max. Unit Operation current for Tone generator Operation current for Current DA I_DA Operation current for Comparator I_CMP (Ta=0°C ~ 70°C, VDD=3V ± 5%, VSS=0V) Parameter Symbol Condition Input Leakage Current for input pins IIL1 VIN = VDD, VSS − − ±1 µA Input Leakage Current for bidirectional pins IIL2 VIN = VDD, VSS − − ±1 µA Input High Voltage VIH − 2.0 − − V Input Low Voltage VIL − − − 0.8 V Input high threshold Voltage VIHT /RESET, TCC, RDET1 2.0 − − V Input low threshold Voltage VILT /RESET, TCC, RDET1 − − 0.8 V Clock Input High Voltage VIHX OSCI 1.8 − − V Clock Input Low Voltage VILX OSCI − − 1.2 V 2.0 2.4 − V 2.0 2.4 − V IOL = 6mA − − 0.4 V IOL = 10.0mA − − 0.4 V IPH Pull-high active input pin at VSS − -10 -15 µA ISB1 All input and I/O pins at VDD, output pin floating, WDT disabled − 1 4 µA Output High Voltage (Ports 8, 9, B, C, D) VOH1 IOH = -6mA Output High Voltage (Ports 6, 7) Output Low Voltage (Ports 8, 9, B, C, D) Output Low Voltage (Port 6, 7) Pull-high current Power-down current (Sleep mode) 66 • − VOL1 − IOH = -10.0mA Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller Parameter Symbol Low clock current (Green mode) ISB2 Operating supply current (Normal mode) ICC Tone generator reference voltage Condition All input and I/O pins at VDD, CLK=32.768kHz, WDT disabled, Output pin floating All analog circuit disabled /Reset=High, PLL enable CLK=3.579MHz, Output pin floating, All analog circuits disabled − Vref2 Min. Typ. Max. Unit − 30 40 µA 2 3 mA 0.7 VDD 0.5 Differential Energy Detector (DED), (Ta=25°C, VDD=3.0V ± 5%, VSS=0V) Symbol Parameter Condition Min. Typ. Max. Unit EGIN1 Operating current for SED SEDCLK bit = 0 20 25 µA EGIN2 Operating current for SED SEDCLK bit = 0 20 25 µA 10 AC Electrical Characteristic CPU Instruction Timing (Ta=25°C, VDD=3V, VSS=0V) Parameter Symbol Condition Input CLK duty cycle Dclk Instruction cycle time Tins Device delay hold time Tdrh TCC input period Ttcc Note 1 Watchdog timer period Twdt Ta = 25°C Min. Typ. Max. Unit 45 50 55 % 32.768kHz 3.579MHz 60 550 us ns 16 ms (Tins+20)/N ns 16 ms Note: N = selected prescaler ratio Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 67 EM78815 8-Bit Microcontroller FSK AC Characteristic (Vdd = 3V, Ta = +25°C) Characteristic Min. Typ. Max. Unit Low Level Sensitivity Tip & Ring @SNR 20dB -40 -48 − dBm High Level Sensitivity Tip & Ring @SNR 20dB − 0 − dBm Signal Reject − -51 − dBm Positive Twist (High Level) +10 − − dB Positive Twist (Low Level) +10 − − dB Negative Twist (High Level) -6 − − dB Negative Twist (Low Level) -6 − − dB Min. Typ. Max. Unit − -38 − dBm Low Tone Frequency 2130Hz − ±1.2 − % High Tone Frequency 2750Hz − ±1.2 − % Low Tone Frequency 2130Hz − ±2.0 − % High Tone Frequency 2750Hz − ±2.0 − % Low Tone Frequency 2130Hz − ±5.5 − % High Tone Frequency 2750Hz − ±5.5 − % ±7 − − dB FSK Sensitivity FSK Twist CW AC Characteristic (Vdd=3V,Ta=+25°C) Characteristic CW Sensitivity Sensitivity @SNR 20dB USA & Europe Mode Chinese Call Waiting Mode Chinese SMS Mode CW Twist Twist DTMF (DTMF Receiver) AC Characteristic (Vdd = 3V, Ta = +25°C) Characteristic Min. Typ. Max. Unit Low Level Signal Sensitivity − -36 − dBm High Level Signal Sensitivity − 0 − dBm Low Tone Frequency − ±2 − % High Tone Frequency − ±2 − % 15 − − dB DTMF Receiver DTMF Receiver Noise Endurance Signal-to-noise Ratio 68 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller Tone Generators for AC Characteristic (Vdd = 3V, Ta = +25°C) Characteristic Min. Typ. Max. Unit 130 155 180 ｍV Tone 1/Tone 2 signal strength (root mean square voltage) Tone 1 signal strength V1rms *1 Tone 2 signal strength V2rms *1 ｍV 1.259V1rms Tone Twist (Tone 1 – Tone 2) twist − -2 − dB − − ±1 % Tone frequency deviation Frequency deviation 1 Note * : V1rms and V2rms has 2dB difference. It means 20log (V2rms/V1rms) = 20log1.259 = 2 (dB) DED AC Characteristic (Vdd = +3.0V, Ta = + 25°C) Characteristic Min. Typ. Max. Unit Input sensitivity TIP and RING for DED, DEDTHD bit=0 − -45 − dBm Input sensitivity TIP and RING for DED, DEDTHD bit=1 − -35 − dBm Timing characteristic (Vdd = 3V, Ta=+25°C) Description Oscillator Timing Characteristic OSC start up 32.768kHz 3.579MHz PLL Symbol Min. Typ. Max. Unit Tosc − − − − − 1500 10 ms us 3 − − 18 − − uS mS − − − − 10 10 15 − 14 20 20 4 ms ns ms ms − 80 − ms − − 42 26 − − ms ms − *1 − − − 30 − ms − 30 − mS − − 8 *2 − − us ms 560 250 250 250 − − − − − − 15 15 − − − − 30 30 ns − ns ns ns ns Timing characteristic of reset Minimum width of reset low pulse Trst Delay between reset and program start Tdrs FSK Timing Characteristic Carrier detect low Tcdl Carrier detect low to data valid Tcdv Power up to FSK(setup time) Tsup End of FSK to Carrier Detect high Tcdh CW Timing Characteristic CAS input signal length Tcasi (2130, 2750 Hz @ -20dBm) Call waiting data detect delay time Tcwd Call waiting data release time Tcwr DTMF Receiver Timing Characteristic Tone Present Detection Time Tdp The guard-times for tone-present Tgtp (C=0.1µF, R=300K) The guard-times for tone-absent Tgta (C=0.1µF, R=300K) Propagation Delay (St to Q) Tpq Tone Absent Detection Time Tda SPI Timing Characteristic (CPU Clock 3.58MHz and Fsco = 3.58MHz /2) /SS set-up time Tcss /SS hold time Tcsh SCLK high time Thi SCLK low time Tlo SCLK rising time Tr SCLK falling time Tf Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 69 EM78815 8-Bit Microcontroller Description SDI set-up time to the reading edge of SCLK SDI hold time to the reading edge of SCLK SDO disable time Symbol Min. Typ. Max. Unit Tisu Tihd Tdis 25 25 − − − − − − 560 ns ns ns Max. Unit 1 Note * : Controlled by software *2 : Controlled by RC circuit Data ROM access timing characteristic Symbol Description Condition Min. Typ. Tdiea Delay from Phase 3 end to INSEND active Cl=100pF 30 ns Tdiei Delay from Phase 4 end to INSEND inactive Cl=100pF 30 ns Tiew INSEND pulse width Tdca Delay from Phase 4 end to CA Bus valid Tacc ROM data access time 100 ns Tcds ROM data setup time 20 ns Tcdh ROM data hold time 20 ns Tdca-1 Delay time of CA-1 70 • 30 C1=100pF C1=100pF ns 30 30 ns ns Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller 11 Timing Diagrams ins Fig. 30 AC Timing Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 71 EM78815 8-Bit Microcontroller FIRST RING 2 SECONDS 0.5 SEC 0.5 SEC SECOND RING 2SECONDS TIP/RING / TRIG Tcdh Tcdl /CD Tdoc DATA DATA (internal clock) 3.579 M Hz Tsup /358E Fig. 31 FSK Timing Diagram CAS Tcasi plug in on hook Events Normal In use Tcwd Tcwr CAS CWPWR Power-off Power-on Fig. 32 Call Waiting Timing Diagram 72 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller TONE EST TONE Tdp 5~20mS by S/W Tgta 30mS Typ. Tgtp 30mS Typ. Vtst 1/2 VDD ST/GT Tpq 8 uS Typ. Q4..Q1 STD LINE_ENG Fig. 33 DTMF Receiver Timing Diagram VDD OSC Power on reset Toscs Trst /RESET Tdrs Tdrs Program Active Fig. 34 Relationship between OSC Stable And Reset Time Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 73 EM78815 8-Bit Microcontroller 12 Application Circuit LCD pannel 65x264 pixels COMMON SEGMENT VDD SEGMENT COMMON FR CL /DOF LCD driver V0 EM9L8580(master) V1 V2 ( support max 65x132 pixels) V3 V4 P/S M/S D0..D7 /RES CLK A0 /RD /WR /CS1 FR CL /DOF V0 V1 V2 V3 V4 LCD driver EM9L8580(slave) VDD ( support max 65x132 pixels) D0..D7 CLK A0 /RD /WR /CS1 /RES P/S M/S 8 PC3 PC4 PC6 PC5 PC7 Reset XOUT Key matrix PORT80 PB7~PB0 VDD,AVDD VDD PORT95 XIN 27p 32.768k XOUT PORT96 27p 0.1u PLLC EM 78815 EGIN1 TIP LINE PORT97 AVSS,GND 4700p P70 47K P71 P72 P73 VDD EGIN2 RING 4700p 47K STGT TIP 4700p 4700p 47K RING EST 47K CWGS E x pandi ng m em or y CWIN i nter f ace EX T ERN A L M em or y 47p 150K 39K 4700p L i ne Speech I nterf ace N etw ork Fig. 35 External Multi-chip LCD Driver Application Circuit 74 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice) EM78815 8-Bit Microcontroller APPENDIX A Application Note 1. In targeting interrupt and program run to address 0x0008, ACC, R3 (Status), R5 (Program Page) and R4 (6, 7) will be automatically saved and R3 (6, 7) R register page will be set to Page 0, and reload after the instruction “RETI”. 2. 0V reference voltage will power down when both RD Page 2 Bit 7 (DAREF) and RA Page 2 Bit 7 (CMPEN) are cleared to 0. 3. Before using Keytone function, set Port 76 as output type. 4. For accessing data ROM, EM78P815 (OTP) can work at 10.74MHz, but note that only ROM type EM78815 can work at 5.3MHz. 5. While switching the main clock (regardless of high freq to low freq or vice versa), adding 6 instructions delay (NOP) is required. 6. Do not switch the MCU operation mode from normal mode to sleep mode directly. Before going into sleep mode, switch the MCU to green mode first. 7. Always keep RA Page 0 Bit 7 = 0, otherwise, unexpected error will occur. Product Specification (V2.4) 08.01.2004 (This specification is subject to change without further notice) 75 EM78815 8-Bit Microcontroller 76 • Product Specification (V2.4) 02.17.2006 (This specification is subject to change without further notice)