EMC EM78M611E

EM78M611E
Product
Specification
DOC. VERSION 1.1
ELAN MICROELECTRONICS CORP.
November 2006
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Copyright © 2006 by ELAN Microelectronics Corporation
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Contents
1
2
3
4
5
6
7
8
General Description ................................................................................................ 1
Features ................................................................................................................... 1
Type Definition......................................................................................................... 3
Application............................................................................................................... 3
Pin Assignment ....................................................................................................... 4
Pin Description ........................................................................................................ 6
Block Diagram ......................................................................................................... 7
Function Description............................................................................................... 8
8.1 Program Memory .............................................................................................. 8
8.2 Data Memory .................................................................................................... 9
8.2.1
8.2.2
8.2.3
Special Purpose Register ....................................................................................9
Operation Registers ..........................................................................................10
8.2.2.1 R0 (Indirect Addressing Register) ......................................................10
8.2.2.2 R1 (Timer / Clock Counter) ................................................................10
8.2.2.3 R2 (Program Counter & Stack) ..........................................................10
8.2.2.4 R3 (Status Register) ........................................................................... 11
8.2.2.5 R4 (RAM Select Register) ..................................................................13
8.2.2.6 R5 (Port 5 I/O Register)......................................................................13
8.2.2.7 R6 (Port 6 I/O Register)......................................................................13
8.2.2.8 R7 (Port 7 I/O Register)......................................................................13
8.2.2.9 R8 (Port 8 I/O Register)......................................................................13
8.2.2.10 R9 (Port 9 I/O Register)......................................................................13
8.2.2.11 RA (EEPROM Control Register..........................................................14
8.2.2.12 RB (Pattern Detect Application Control Register) ..............................14
8.2.2.13 RC (USB Application Status Register) ...............................................14
8.2.2.12 RD (USB Application FIFO Address Register) ...................................15
8.2.2.13 RE (USB Application FIFO Data Register).........................................15
8.2.2.14 RF (Interrupt Status Register) ............................................................15
Control Registers...............................................................................................16
8.2.3.1 A (Accumulator)..................................................................................16
8.2.3.2 CONT (Control Register)....................................................................17
8.2.3.3 IOC5 ~IOC9 I/O (Port Direction Control Registers) ...........................18
8.2.3.4 IOCA (Operation Mode Control Register) ..........................................18
8.2.3.5 IOCB (Port 9 Wake-up Pin Select Register) ......................................19
8.2.3.7 IOCD (Port 9 Pull High Control Register)...........................................19
8.2.3.8 IOCE (Special Function Control Register)..........................................20
8.2.3.9 IOCF (Interrupt Mask Register)..........................................................21
Product Specification (V1.11) 04.20.2006
• iii
Contents
8.3
8.4
8.5
Extra Control Register..................................................................................... 21
USB Application FIFOs ................................................................................... 21
USB Application .............................................................................................. 22
8.5.1
8.5.2
8.6
Reset .............................................................................................................. 23
8.6.1
8.6.2
8.6.3
8.7
Power-on Reset.................................................................................................23
Watchdog Reset ................................................................................................23
USB Reset.........................................................................................................23
Saving Power Mode........................................................................................ 23
8.7.1
8.7.2
8.8
8.9
USB Device Controller ......................................................................................22
Device Address and Endpoints .........................................................................23
Power Down Mode ............................................................................................23
Dual Clock Mode ...............................................................................................24
Interrupt ......................................................................................................... 24
Pattern Detect Application (PDA) .................................................................... 25
8.9.1
8.9.2
8.9.3
Function Description..........................................................................................25
Control Register ................................................................................................26
Sampling Rate and Debounce Length ..............................................................26
8.10 Pulse Width Modulation (PWM) ...................................................................... 28
8.10.1 Function Description..........................................................................................28
8.10.2 Duty Cycle .........................................................................................................28
8.10.3 Control Register ................................................................................................28
8.11 Analog-To-Digital Converter (ADC) ................................................................. 29
8.11.1 Function Description..........................................................................................29
8.11.2 Control Register ................................................................................................29
9
10
11
8.12 EEPROM ........................................................................................................ 31
Absolute Maximum Ratings.................................................................................. 32
DC Electrical Characteristic.................................................................................. 32
Application Circuit................................................................................................. 34
APPENDIX
A
B
C
Special Register Map ............................................................................................ 35
Instruction Set ....................................................................................................... 37
Code option Register ............................................................................................ 39
Specification Revision History
Doc. Version
iv •
Revision Description
Date
1.0
Preliminary version
2006/04/17
1.1
Released version
2006/11/24
Product Specification (V1.1) 11.22.2006
EM78M611E
Universal Serial Bus Series Microcontroller
1
General Description
The EM78611E is a series of 8-bit Universal Serial Bus RISC architecture microcontroller,
Multi-Time Programming (MTP) microcontrollers. It is specifically designed for USB low
speed device application and to support standard devices such as PS/2 keyboard. The
EM78611E also supports one device address and three endpoints. With no firmware
involved, these series of microcontrollers can automatically identify and decode Standard
USB Command to Endpoint Zero.
The EM78611E has eight-level stacks and six interrupt sources. It has 144 bytes of
general purpose SRAM, 6K bytes of program ROM, and an embedded 4 bytes of
2
E PROM.
These series of ICs have many powerful features, including:
Dual clock mode which allows the device to run on low power saving frequency.
Pattern Detect Application function which is used in a serial transmission to count
waveform width.
Pause Width Modulation that can generate a duty-cycle-programmable signal.
24-channel AD converter with up to 10 bits resolution.
2
Features
Operating voltage: 4.4V ~ 5.5V
Low-cost solution for low-speed USB devices, such as keyboard, joystick, and
Gamepad
USB Specification Compliance
Universal Serial Bus Specification Version 1.1
USB Device Class Definition for Human Interface Device (HID), Firmware
Specification Version 1.1
Supports one device address and three endpoints
USB Application
P75 (D-) has an internal pull-high resistor (1.5 KΩ)
USB protocol handling
USB device state handling
Identifying and decoding of Standard USB commands to EndPoint Zero
PS/2 Application Support
Built-in PS/2 port interface for keyboard and mouse
Product Specification (V1.11) 04.20.2007
(This specification is subject to change without further notice)
•1
EM78M611E
Universal Serial Bus Series Microcontroller
Built-in 8-bit RISC MCU
8-level stacks for subroutine nesting and interrupt
8-bit real time clock/counter (TCC) with overflow interrupt
Six available interrupts
Built-in RC oscillator free running for Watchdog Timer and Dual clock mode
Two independent programmable prescalers for WDT and TCC
Two power saving methods:
1. Power-down mode (Sleep mode)
2. Dual clock mode
Two clocks per instruction cycle
Multi-time programmable
I/O Ports
Up to 11 LED sink pins
Each GPIO pin of Ports 5, 6, 8, P90~P93, P95 and P96; has an internal
programmable pull-high resistor (25KΩ)
Each GPIO pin of Port 6, P74 ~ P77 and Port 9 can wake up the MCU from
sleep mode by input state change
Internal Memory
Built-in 6K×13 bits Program ROM
Built-in 144 bytes general purpose registers (SRAM)
Built-in USB Application FIFOs
Built-in 4 bytes EEPROM with a minimum of 4K write/erase cycles
Operation Frequency
Normal Mode: MCU runs with an external oscillator frequency of 6 MHz or
12 MHz
Dual Clock Mode: MCU runs at a frequency of 256kHz (or 32 kHz, 4kHz,
500Hz), emitted by the internal oscillator with the external ceramic
resonator turned off to save power.
Built-in Pattern Detect Application for serial signal transmission
Built-in Pulse Width Modulation (PWM)
Up to 2 channels PWM function on P92 (PWM1) and P93 (PWM2)
Up to 8-bit resolution PWM output
Up to 8 selections of duty cycles
2•
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
EM78M611E
Universal Serial Bus Series Microcontroller
Built-in 24-Channel Analog-to-Digital Converter (ADC)
Up to 24 channels
Up to 10 bits resolution
4 ADC conversion rates: 256K/128K/64K/32K
Built-in 3.3V Voltage Regulator
For MCU power supply
Pull-up source for the external USB resistor on D-pin
Package Type:
40-pin PDIP (600mil) (EM78M611EXAP)
44-pin QFP (10×10mm, footprint=3.2mm) (EM78M611EXAQ)
20-pin PDIP (300mil)/SOP (300mil) (EM78M611EXBP/BM)
20-pin SSOP (209mil) (EM78M611EXDM)
24-pin PDIP (600mil)/SOP (300mil) (EM78M611EXCP/CM)
24-pin SSOP (150mil) (EM78M611EXEM)
3
Type Definition
The EM78M611E series has six types of packaging. Each type is divided into two
2
modules, namely; original, and with both E PROM and A/D Converter. Hence,
packaging configuration for each series is defined. Table 3.1 below summarizes which
series of the EM78M611E belong to which module.
Table 3-1 Packaging Summary of EM78M611E Series IC
4
Original
With Both
EM78M611EA**
EM78M611ED**
Application
USB Keyboard only
USB and PS/2 both compatible with Keyboard
USB Keyboard with USB Mouse
USB Joystick
Product Specification (V1.11) 04.20.2007
(This specification is subject to change without further notice)
•3
EM78M611E
Universal Serial Bus Series Microcontroller
5
Pin Assignment
VSS
1
40
OSCO
V3.3
2
39
OSCI
D+/CLK.P74
3
38
VDD
D-/DATA/P75
4
37
P70
P90
5
36
P71
P91
6
35
P72
P92/SE1/PWM1
7
34
P67/AD23
P93/SE2/PWM2
8
33
P66/AD22
P94/VPP
9
32
P65/AD21
P64/AD20
VNN
10
31
P50/AD0
11
30
P63/AD19
P51/AD1
12
29
P62/AD18
P52/AD2
13
28
P61/AD17
P53/AD3
14
27
P60/AD16
P54/AD4
15
26
P87/AD15
P55/AD5
16
25
P86/AD14
P56/AD6
17
24
P85/AD13
P57/AD7
18
23
P84/AD12
P80/AD8
19
22
P83/AD11
P81/AD9
20
21
P82/AD10
P70
P76
P77
VDD
OSCI
OSCO
V3.3
VSS
D+/CLK/P74
P90
D-/DATA/P75
Fig. 3-1 EM78M611EXAP (40-Pin DIP)
44 43 42 41 40 39 38 37 36 35 34
P91
1
33
P92/SE1/PWM1
2
32
P71
P72
P93/SE2/PWM2
3
31
P67/AD23
P94/VPP
4
30
P66/AD22
P95
5
29
P65/AD21
P96
6
28
P64/AD20
VNN
7
27
P63/AD19
P50/AD0
8
26
P62/AD18
P51/AD1
9
25
P61/AD17
P52/AD2
10
24
P60/AD16
P53/AD3
11
23
P87/AD15
P86/AD14
P85/AD13
P84/AD12
P83/AD11
P81/AD9
P82/AD10
P80/AD8
P57/AD7
P56/AD6
P55/AD5
P54/AD4
12 13 14 15 16 17 18 19 20 21 22
Fig. 3-2 EM78M611EXAQ (44-Pin QFP)
4•
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
EM78M611E
Universal Serial Bus Series Microcontroller
P56/AD6
1
20
P55/AD5
P57/AD7
2
19
P54/AD4
P60/AD16
3
18
VNN
P61/AD17
4
17
P94/VPP
P62/AD18
5
16
P93/SE2/PWM2
P77
6
15
P92/SE1/PWM1
P76
7
14
D- / DATA /P75
VDD
8
13
D+ / CLK /P74
OSCI
9
12
V3.3
OSCO
10
11
VSS
Fig. 3-3 EM78M611EXBP/BM/DM (20-Pin DIP/SOP/SSOP)
OSCO
1
24
OSCI
VSS
2
23
VDD
V3.3
3
22
P76
D+ / CLK / P74
4
21
P77
D- / DATA /P75
5
20
P66/AD22
P92/SE1/PWM1
6
19
P65/AD21
P93/SE2/PWM2
7
18
P64/AD20
P94/VPP
8
17
P63/AD19
VNN
9
16
P62/AD18
P54/AD4
10
15
P61/AD17
P55/AD5
11
14
P60/AD16
P56/AD6
12
13
P57/AD7
Fig. 3-4 EM78M611EXCP/CM/EM (24-Pin DIP/SOP/SSOP)
Product Specification (V1.11) 04.20.2007
(This specification is subject to change without further notice)
•5
EM78M611E
Universal Serial Bus Series Microcontroller
6
Pin Description
Symbol
I/O
P50 ~ P57
I/O
General 8-bit bidirectional input/output port. All pins on this port can be
internally pulled-high by software control.
P60 ~ P67
I/O
General 8-bit bidirectional input/output port. All pins on this port can be
internally pulled-high by software control.
P70 ~ P72
P76 ~ P77
P80 ~ P87
P90 ~ P93
P95 ~ P96
P94 / Vpp
PWM1
PWM2
Function
LED sink pins
I/O
P76 ~ P77 will have an internally pulled-high resistor when the EM78M611E is
running in PS/2 mode.
I/O
General 8-bit bidirectional input/output port. All pins on this port can be
internally pulled-high by software control.
I/O
General 6-bit bidirectional input/output port. All pins on this port can be
internally pulled-high by software control or LED sink pins.
I
Input only. MTP program pin.
O
PWM output pins.
I/O
When the EM78M611E is running in PS/2 mode, this pin will have an internal
pulled-high resistor (2.2KΩ), with VDD=5.0V.
USB plus data line interface or CLK for PS/2 keyboard.
D+/CLK/P74
USB minus data line interface or DATA for PS/2 keyboard.
D-/DATA/P75
I/O
When the EM78M611E is running in PS/2 mode, this pin will have an internal
pulled-high resistor (2.2KΩ), with V3.3=3.3V.
When the EM78M611E is running in USB mode, this pin will have an internal
pulled-high resistor (1.5KΩ), with VDD=3.3V.
6•
OSCI
I
6MHz / 12MHz ceramic resonator input.
OSCO
O
Return path for 6MHz / 12MHz ceramic resonator.
VNN
−
MTP program pin. Used in programming the on-chip ROM. During normal
operation, this pin is connected to Ground.
V3.3
PWR
3.3V regulator output
VDD
PWR
Power supply pin
GND
PWR
Ground pin
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
EM78M611E
Universal Serial Bus Series Microcontroller
7
Block Diagram
OSCI
Built-in
RC
OSCO
WDT
Timer
V3.3
3.3V
Regulator
Oscillator
Timing
Control
Prescaler
WDT
Reset,
Sleep &
Wake-up
Control
VDD
Prescaler
TCC
R1
(TCC)
D+
D-
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
Stack 6
Stack 7
Stack 8
R2
(PC)
Transceiver
ROM
USB
Device
Controller
Instruction
Register
R3
(Status)
RAM
Interrupt
Control
R4
(RSR)
ALU
Instruction
Decoder
ACC
DATA & CONTROL BUS
I/O
Port 7
P74/D+/Clk
P75/D-/Data
P70
P71
P72
P76
P77
I/O
Port 9
Product Specification (V1.11) 04.20.2007
P90
P91
P92
P93
P94
P95
P96
P97
(This specification is subject to change without further notice)
I/O
Port 8
P80
P81
P82
P83
P84
P85
P86
P87
I/O
Port 6
P60
P61
P62
P63
P64
P65
P66
P67
I/O
Port 5
P50
P51
P52
P53
P54
P55
P56
P57
•7
EM78M611E
Universal Serial Bus Series Microcontroller
8
Function Description
The EM78M611E memory is organized into three spaces, namely; User Program
memory in 6K×13 bits ROM space, Data Memory in 144 bytes SRAM space, EEPROM
space and USB Application FIFOs for EndPoint0, EndPoint1, and EndPoint2.
Furthermore, several registers are used for special purposes.
8.1 Program Memory
The program space of the EM78M611E is 6K words, and is divided into six pages.
Each page is 1K words long. After a reset, the 13-bit Program Counter (PC) points to
location zero of the program space.
The Interrupt Vector is at 0x0001 and accommodates TCC interrupt, RF1 (SE1) timing
counter interrupt, RF2 (SE2) timing counter interrupt, P74~P77 State Changed
interrupt, EndPoint0 interrupt, USB Suspend interrupt, USB Reset interrupt, and USB
Host Resume interrupt.
After an interrupt, the MCU will fetch the next instruction from the corresponding
address as illustrated in the following diagram.
After Reset
PC
0X0000
0X0001
0X03FF
0X0400
0X07FF
0X0800
0X0BFF
0X0C00
0X0FFF
0X1000
0X13FF
0X1400
0X17FF
8•
Address
Reset Vector
Interrupt Vector
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
EM78M611E
Universal Serial Bus Series Microcontroller
8.2 Data Memory
The Data Memory has 144 bytes SRAM space. It has also an on-chip USB Application
FIFO space for USB Application. Figure 8-1 (next page) shows the organization of the
Data Memory Space.
8.2.1 Special Purpose Register
When the microcontroller executes instructions, specific registers are implemented to
ensure proper operation of essential functions such as Status Register which records
the calculation status, Port I/O Control Registers which control the I/O pins’ direction,
etc. Lots of other special purpose registers are provided for various functions.
Note that Special Control Registers can only be read or written to by two instructions:
IOR and IOW.
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Fig. 8-1 Data RAM Organization of EM78M611E
Product Specification (V1.11) 04.20.2007
(This specification is subject to change without further notice)
•9
EM78M611E
Universal Serial Bus Series Microcontroller
8.2.2 Operation Registers
The following subsections describe each of the Operation Registers of the Special
Purpose Registers. The Operation Registers are arranged according to the order of the
registers’ address. Note that some registers are read only, while others are both
readable and writable.
8.2.2.1
R0 (Indirect Addressing Register) Default Value: (0B_0000_0000)
R0 is not a physically implemented register.
Its major function is as an indirect
addressing pointer. Any instruction using R0 as a pointer actually accesses data
pointed by the RAM Select Register (R4).
8.2.2.2
R1 (Timer / Clock Counter) Default Value: (0B_0000_0000)
The TCC register is an 8-bit timer or counter. It is readable and writable as any other
register. The Timer module will be incremented after execution of every instruction
cycles. User can work around this by writing an adjusted value. The Timer interrupt is
generated when the R1 register overflows from FFh to 00h. This overflow sets bit TCIF
(RF[0]). The interrupt can be masked by clearing bit TCIE (IOCF[0]). After Power-on
reset and Watchdog reset, the initial value of this register is 0x00.
8.2.2.3
R2 (Program Counter & Stack) Default Value: (0B_0000_0000)
The EM78M611E Program Counter is a 13-bit register that allows accessing of the 6k
words of the Program Memory with 8 level stacks. The eight LSB bits, A0~A7, are
located at R2, while the three MSB bits, A12~A10, are located at R3. The Program
Counter is cleared after Power-on reset or Watchdog reset. The first instruction that is
executed after a reset is located at address 00h.
10 •
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
EM78M611E
Universal Serial Bus Series Microcontroller
A12 A11 A10
A9 A8
Call
Interrupt
A7~A0
RET
RETL
RETI
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
0000
Stack 6
Stack 7
Page 0
Stack 8
03FF
0400
Page 1
07FF
0800
Page 2
0BFF
1000
0000 : Reset Vector
0001 : Interrupt Vector
Page 0
13FF
1400
Page 0
17FF
8.2.2.4
R3 (Status Register) Default Value:(0B_0001_1XXX)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PS2
PS1
PS0
T
P
Z
DC
C
R3 [0] Carry/Borrow Flag
0 = No carry-out from the result’s Most Significant bit
1 = A carry-out from the result’s Most Significant bit occurred
NOTE
For Borrow, the polarity is reversed. For rotate (RRC, RLC) instructions, this bit is
loaded with either high or low-order bit of the source register.
R3 [1] Auxiliary Carry/Borrow Flag. For ADD, SUB Instructions
0 = No carry-out from the 4th low-order bit of the result
1 = A carry-out from the 4th low-order bit of the result occurred
NOTE
For Borrow, the polarity is reversed.
Product Specification (V1.11) 04.20.2007
(This specification is subject to change without further notice)
• 11
EM78M611E
Universal Serial Bus Series Microcontroller
R3 [2] Zero flag. It will be set to 1 when the result of an arithmetic or logic operation is
zero.
R3 [3] Power down flag. It will be set to 1 during Power-on phase or by “WDTC”
command and cleared when the MCU enters into Power down mode. It remains
in its previous state after a Watchdog Reset.
0: Power down
1: Power-on
R3 [4] Time-out flag. It will be set to 1 during Power-on phase or by “WDTC”
command. It is reset to 0 by WDT time-out.
0: Watchdog timer overflow occurs
1: No Watchdog timer overflow
The various states of Power down flag and Time-out flag at different conditions are
shown below:
T
P
Condition
1
1
Power-on reset
1
1
WDTC instruction
0
*P
WDT time-out
1
0
Power down mode
1
0
Wake up caused by port change during Power down mode
*P: Previous status before WDT reset
R3 [5-7] Page selection bits. These three bits are used to select the program memory
page.
12 •
PS2
PS1
PS0
Program Memory Page [Address]
0
0
0
Page 0 [0000-03FF]
0
0
1
Page 1 [0400-07FF]
0
1
0
Page 2 [0800-0BFF]
0
1
1
Page 3 [0C00-0FFF]
1
0
0
Page 4 [1000-13FF]
1
0
1
Page 5 [1400-17FF]
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
EM78M611E
Universal Serial Bus Series Microcontroller
8.2.2.5
R4 (RAM Select Register) Default Value: (0B_00XX_XXXX)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BK1
BK0
Ad5
Ad4
Ad3
Ad2
Ad1
Ad0
R4 (RAM select register) contains the address of the registers.
R4 [0~5] used to select registers in 0x00h~0x3Fh. The address 0x00~0x1F is common
space. After 0x1Fh, SRAM is divided into four banks, using Bank Select
Register.
R4 [6, 7] used to select the registers bank (refer to the table below). The following are
two examples:
(1) R4=00001100 and R4=10001100 point to the same register 0x0Ch. Since
0x0Ch is in the common space, Bit 6 and Bit 7 are meaningless.
(2) R4=10111100 points to the register 0x3C in Bank 2.
8.2.2.6
R4[7]Bk1
R4[6]Bk0
RAM Bank #
0
0
1
1
0
1
0
1
Bank 0
Bank 1
Bank 2
Bank 3
R5 (Port 5 I/O Register) Default Value: (0B_0000_0000)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P57
P56
P55
P54
P53
P52
P51
P50
8.2.2.7
R6 (Port 6 I/O Register) Default Value: (0B_0000_0000)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P67
P66
P65
P64
P63
P62
P61
P60
8.2.2.8
R7 (Port 7 I/O Register) Default Value: (0B_0000_X000)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P77
P76
D- / P75 / DATA
D+ / P74 / CLK
−
P72
P71
P70
8.2.2.9
R8 (Port 8 I/O Register) Default Value: (0B_0000_0000)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P87
P86
P85
P84
P83
P82
P81
P80
8.2.2.10 R9 (Port 9 I/O Register) Default Value: (0B_X00X_0000)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
−
P96
P95
−
P93
P92
P91
P90
Product Specification (V1.11) 04.20.2007
(This specification is subject to change without further notice)
• 13
EM78M611E
Universal Serial Bus Series Microcontroller
8.2.2.11 RA (EEPROM Control Register) Default Value: (0B_1111_1111)
RA is a command register for EEPROM control. For detailed usage of this register,
refer to Section 8.2.3 which describes the EEPROM embedded in the
EM78M611E.
8.2.2.12 RB (Pattern Detect Application Control Register)
Default Value: (0B_0000_0000)
RB is a control register for controlling the Pattern Detect Application function. For
detailed description of this register, refer to Section 8.7.2 which describes the
PDA function.
8.2.2.13 RC (USB Application Status Register) Default Value: (0B_0000_0000)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EP0_W
EP0_R
EP1_R
EP2_R
EP2_W
Host_Suspend
EP0_Busy
Stall
RC [0]
Stall flag. While the MCU receives an unsupported command or invalid
parameters from host, this bit will be set to 1 by the firmware to notify the UDC
to return a STALL handshake. When a successful Setup transaction is
received, this bit is cleared automatically. T his bit is readable and writable.
RC [1]
EP0_Busy flag. When this bit is equal to “1,” it indicates that the UDC is writing
data into the EP0’FIFO or reading data from it. During this time, the firmware
will avoid accessing the FIFO until UDC finishes writing or reading. This bit is
only readable.
RC [2]
Host Suspend flag. If this bit is equal to 1, it indicates that USB bus has no
traffic for a specified period of 3.0 ms. This bit will also be cleared
automatically when there is bus activity. This bit is only readable.
RC [3] EP2_W flag. This bit is set when the UDC receives a successful data from USB
Host to EP2. Upon detecting that this bit is equal to one, the firmware will
execute a read sequence to the EP2’s FIFO, after which this bit is cleared.
Otherwise, the subsequent data from USB Host won’t be accepted by the
UDC.
RC [4, 5, 6] EP0_R / EP1_R / EP2_R flag. These three bits inform the UDC to read
the data from the FIFO. Then the UDC will send the data to the Host
automatically. After UDC finishes reading the data from the FIFO, this bit will
be cleared automatically.
Therefore, before writing data into FIFO’s, the firmware will first check this bit
to avoid overwriting the data. These three bits can only be set by firmware
and cleared by hardware.
RC [7]
EP0_W flag. After the UDC completes writing data to the FIFO, this bit will be
set automatically. The firmware will clear it as soon as it gets the data from
EP0’s FIFO. Only when this bit is cleared that the UDC will be able to write a
new data into the FIFO.
Therefore, before the firmware can write data into the FIFO, this bit must first
be set by the firmware to prevent the UDC from writing data at the same time.
This bit is both readable and writable.
14 •
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
EM78M611E
Universal Serial Bus Series Microcontroller
8.2.2.12 RD (USB Application FIFO Address Register)
Default Value: (0B_0000_0000)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
UAD4
UAD3
UAD2
UAD1
UAD0
RD [0~4]
USB Application FIFO address registers. These five bits are the address
pointers of USB Application FIFO.
RD [5~7] Undefined registers. The default value is zero.
8.2.2.13 RE (USB Application FIFO Data Register)
Default Value: (0B_0000_0000)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
UD7
UD6
UD5
UD4
UD3
UD2
UD1
UD0
RE (USB Application FIFO data register) contains the data in the register of which
address is pointed by RD.
NOTE
For example, if user wants to read the fourth byte of EndPoint Zero, user has to use the
address of EP0 (0x00) and Data Byte Pointer of EP0 (0x10) to access it.
// Read the 4th byte of the EP0 FIFO
// First, assign the data byte pointer of EP0 register (0X10) with 0X03.
MOV A, @0X10
MOVRD, a
// Move data in A to RD register
MOV A, @0X03
MOVRE , A
// Move data in A to RE register
// Then read the content from EP0 FIFO (0x00) 4th byte
MOV A, @0X00
MOVRD, A
// Assign address point to EP0 FIFO
MOVA, RE
// Read the fourth byte data (Byte 3) of the EP0 FIFO
MOV A, 0X0E // Read the fifth byte data (Byte 4) of the EP0 FIFO
8.2.2.14 RF (Interrupt Status Register) Default Value: (0B_0000_0000)
Bit 7
Bit 6
USB Host
SE2_IF
Resume_IF
RF [0]
Bit 5
SE1_IF
Bit 4
Bit 3
Bit 2
Bit 1
Port7 state
USB
USB
EP0_IF
change_1F Reset_IF Suspend_IF
Bit 0
TCC_IF
TCC Overflow interrupt flag. It will be set while TCC overflows, and is cleared
by firmware.
RF [1]
EndPoint Zero interrupt flag. It will be set when the EM78M611E receives
Vendor/Customer Command to EndPoint Zero. This bit is cleared by
firmware.
Product Specification (V1.11) 04.20.2007
(This specification is subject to change without further notice)
• 15
EM78M611E
Universal Serial Bus Series Microcontroller
RF [2]
USB Suspend interrupt flag. It will be set when the EM78M611E finds the
USB Suspend Signal on USB bus. This bit is cleared by the firmware.
RF [3]
USB Reset interrupt flag. It will be set when the host issues the USB Reset
signal.
RF [4]
P74/P75/P76/P77 Port state change interrupt flag.
In PS2 Mode, only pins configured as inputs can cause this interrupt to occur.
These pins (P74, P75, P76 and P77) are compared with the value latched on
the last read of Port 7.
In USB Mode, P76 and P77 have this function.
NOTE
R F[4]: Port State Change Interrupt Flag,
EM78M611
USB Mode –P76 and P77 DO NOT have interrupt function.
PS2 Mode – P74/P75/P76/P77 have interrupt function.
EM78M611E
P74/P75/P76/P77 all have interrupt function (in USB & PS2 mode)
RF [5, 6] SE1 / SE2 Pattern Detect Interrupt flag. These two flags are used for Pattern
detect application.
RF [7]
USB Host Resume interrupt flag. It will be set only in Dual clock mode when
the USB suspend signal becomes low.
NOTE
RF [7]: USB Host Resume_IF
In EM78M611, this bit is always ‘1’. It is not for use.
In EM78M611E, this bit is O.K. for use.
8.2.3 Control Registers
Some special purpose registers are available for special control purposes. Except for
the Accumulator (ACC), these registers must be read and written with special
instructions. One of these registers, CONT, can only be read by the instruction
"CONTR" and written by "CONTW" instruction. The other special control registers can
be read by the instruction "IOR" and written by the instruction "IOW".
The following paragraphs describe only the general functions of the control registers.
8.2.3.1
A (Accumulator)
The accumulator is an 8-bit register that holds operands and results of arithmetic
calculations. It is not addressable. After an interrupt occurs, the Accumulator is
auto-saved by hardware.
16 •
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
EM78M611E
Universal Serial Bus Series Microcontroller
CONT (Control Register) Default Value: (0B_0011_1111)
8.2.3.2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LED
INT
TSR2
TSR1
TSR0
PSR2
PSR1
PSR0
Except for Bit 6 (Interrupt enable control bit), the CONT register can be read by the
instruction "CONTR" and written by the instruction “CONTW".
CONT [0~2] Watchdog Timer prescaler bits. These three bits are used as the
Watchdog Timer prescaler.
CONT [3~5] TCC Timer prescaler bits.
The relationship between the prescaler value and these bits are shown below:
PSR2/TSR2
PSR1/TSR1
PSR0/TSR0
TCC Rate
WDT Rate
0
0
0
1: 2
1: 1
0
0
1
1: 4
1: 2
0
1
0
1: 8
1: 4
0
1
1
1: 16
1: 8
1
0
0
1: 32
1: 16
1
0
1
1: 64
1: 32
1
1
0
1: 128
1: 64
1
1
1
1: 256
1: 128
NOTE
WDT Timing base is “Power-on time”. Set by the code option [2, 1.]
Ex. Code option [2 ,1] = 01 (2ms), and Prescaler = 1:128.
WDT overflow time is: 2mS * 2^7 = 256 mS
CONT [6] Interrupt enable control bit. This bit toggles Interrupt function between
enable and disable. It is set to 1 by the interrupt disable instruction "DISI"
and reset by the interrupt enable instructions "ENI" or "RETI."
0 : Disable the Interrupt function
1 : Enable the Interrupt function
CONT [7] LED bit. This bit is used to enable the LED sink capacity of P76 and P77.
0 : Disable the LED sink capacity of P76, P77
1 : Enable the LED sink capacity of P76, P77
Product Specification (V1.11) 04.20.2007
(This specification is subject to change without further notice)
• 17
EM78M611E
Universal Serial Bus Series Microcontroller
8.2.3.3
IOC5 ~IOC9 I/O (Port Direction Control Registers)
Default Value: (0B_1111_1111)
These are I/O port (Port 5 ~ Port 7) direction control registers. Each bit controls the I/O
direction of three I/O ports respectively. When these bits are set to 1, the relative I/O
pins become input pins. Similarly, the I/O pins becomes outputs when the relative
control bits are cleared.
0 : Output direction
1 : Input direction
8.2.3.4
IOCA (Operation Mode Control Register) Default Value: (0B_1110_0000)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Dual_Frq.1
Dual_Frq.0
-
Remote_Wake up
ExReg_Sel
PDA
PS/2
USB
IOCA [0, 1]
IOCA[2]
These two bits are used to select the operation mode.
IOCA[1]
IOCA[0]
Operation Mode
0
0
Detect Mode
0
1
USB Mode
1
0
PS/2 Mode
1
1
USB Test Mode
Pattern Detect Application function enable bit. This bit is used to enable the
Pattern Detect Application (PDA) function. For details about this function
refer to Section 8.11.
0 : Disable PDA function
1 : Enable PDA function
IOCA[3]
Extra control register select bit. The five extra control registers (REA, REB,
REC, RED, and REE) are located in 0xA~0xE. To access these five
registers, set the bit as follows:
0 : Select RA~RE
1 : Select Extra Control register ERA~ERE
IOCA[4]
Indicate whether the device is currently requested to support remote wake
up or not. The Remote Wake-up field can be modified by SetFeature () and
ClearFeature () requests.
0 : Do Not support remote wake up
1 : Supports remote wake up
NOTE
IOCA[4]: Remote_Wake up bit
EM78M611 do NOT support this function. Only EM78M611E does.
18 •
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
EM78M611E
Universal Serial Bus Series Microcontroller
IOCA [6, 7] Select the operation frequency in Dual Clock Mode. Four frequencies are
available and can be chosen as Dual Clock Mode in running the MCU
program.
8.2.3.5
Dual_Frq.1
Dual_Frq.0
Frequency
0
0
500Hz
0
1
4kHz
1
0
32kHz
1
1
256kHz
IOCB (Port 9 Wake-up Pin Select Register)
Default Value: (0B_X111_1111)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
−
/P96
/P95
/P94
/P93
/P92
/P91
/P90
IOCB [0~6] These bits are used to select which of the Port 9 pins is to be assigned to
wake up the MCU while in Power down mode.
0 : Enable the function
1 : Disable the function
IOCB[7]
Reserved bit
8.2.3.6
IOCC (Port 9 LED Sink Capacity Control Register)
Default Value: (0B_X00X_0000)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
−
P96
P95
−
P93
P92
P91
P90
IOCC [0~3, 5, 6] LED sink control bit. These bits are used to enable the LED sink
capacity of P90 ~ P97
0 : Disable the LED sink capacity of respective pin
1 : Enable the LED sink capacity of respective pin
IOCC [4, 7]
8.2.3.7
Reserved bits
IOCD (Port 9 Pull High Control Register) Default Value: (0B_X11X_1111)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
−
/PH96
/PH95
−
/PH93
/PH92
/PH91
/PH90
IOCD [0~3, 5, 6] These bits control the 25KΩ pull-high resistor of individual pins in
Port 9.
0 : Enable the pull-high function
1 : Disable the pull-high function
IOCD [4, 7]
Reserved bits
Product Specification (V1.11) 04.20.2007
(This specification is subject to change without further notice)
• 19
EM78M611E
Universal Serial Bus Series Microcontroller
8.2.3.8
IOCE (Special Function Control Register) Default Value: (0B_1101_0111)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/Dual clock
/WUE
WTE
RUN
Device_Resume
/PU8
/PU6
/PU5
IOCE [0, 1, 2] Port 5, Port 6, and Port 8 pull-high control bits.
0 : Enable
1 : Disable
IOCE [3] Setting this bit will allow the UDC to execute resume signaling. This bit is set
by firmware to generate a signal to wake-up the USB host and is cleared as
soon as the USB Suspend signal becomes low. It can only be used in Dual
clock mode when the USB suspend signal becomes low.
NOTE
IOCE[3]: Device_Resume bit
In EM78M611, this bit is always ‘0’. It is not for use.
In EM78M611E, this bit is O.K. for use.
IOCE [4] Run bit. This bit can be cleared by firmware and set during power-on, or by
the hardware at a falling edge of the wake-up signal. When this bit is cleared,
the clock system is disabled and the MCU enters into Power down mode. At
the transition of wake-up signal from high to low, this bit is set to enable the
clock system.
0 : Sleep mode. The EM78M611E is in power down mode.
1 : Run mode. The EM78M611E is working normally.
IOCE [5] Watchdog Timer enable bit. The bit disables/enables the Watchdog Timer.
0 : Disable WDT
1 : Enable WDT
IOCE [6] Enable the wake-up function as triggered by port-changed. This bit is set by
UDC.
0 : Enable the wake-up function
1 : Disable the wake-up function
IOCE [7] Dual clock Control bit. This bit is used to select the frequency of system clock.
When this bit is cleared, the MCU will run on very low frequency for power
saving and the UDC will stop working.
0 : Selects to run on slow frequency
1 : Selects EM78M611E to run on normal frequency
20 •
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
EM78M611E
Universal Serial Bus Series Microcontroller
8.2.3.9
IOCF (Interrupt Mask Register) Default Value
Bit 7
Bit 6
Bit 5
USB Host
Resume_I
E
SE2_IE
SE1_IE
Bit 4
Bit 3
J
(0B_0000_0000)
Bit 2
Port7 state
USB
USB
change_1E Reset_IE Suspend_IE
Bit 1
Bit 0
EP0_IE
TCC_IE
IOCF [0~7] TCC / EP0 / USB Suspend / USB Reset / Port 7 State Change / SE1_IE /
SE2_IE / USB Host Resume interrupt enable bits. These eight bits control
the TCC interrupt function, EP0 interrupt, USB Suspend interrupt, USB
Reset interrupt, Port 7 State Change interrupt and USB Host Resume
interrupt respectively. Individual interrupt is enabled by setting its
associated control bit in the IOCF to "1."
0 : Disable Interrupt
1 : Enable Interrupt
Only when the global interrupt is enabled by the ENI instruction will the individual
interrupt work. After DISI instruction, any interrupt will not work even if the respective
control bits of IOCF are set to 1.
The USB Host Resume Interrupt works only in Dual clock mode. This is because when
the MCU is in sleep mode, it will be automatically woken up by the UDC Resume signal.
8.3 Extra Control Register
Five extra control registers are available to control some special functions. The five
registers are ERA (AD Control register), ERB (AD_LSB), ERC (AD_MSB), ERD
(AD_Rate), and ERE (PWM Control register)
Remember to set IOCA[3] before accessing these five registers. The operating method
is the same as with other control registers.
8.4 USB Application FIFOs
For USB Application, EM78M611E provides an 8-byte First-In-First-Out (FIFO) buffer
for each endpoint. The buffer cannot be accessed directly. However, a corresponding
Data Byte Pointer register for each endpoint is made available to address the individual
byte of the FIFO buffer. The content of the individual byte will map to a special register.
Product Specification (V1.11) 04.20.2007
(This specification is subject to change without further notice)
• 21
EM78M611E
Universal Serial Bus Series Microcontroller
Address
(RD)
0X10
Data Byte Pointer of EP0
0X11
Data Byte Pointer of EP1
0X12
Data Byte Pointer of EP2
Counter
0X00
EP0's FIFO
0X01
EP1's FIFO
0X02
EP1's FIFO
Pointer
Counter
Pointer
Counter
Pointer
0
0
0
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
6
7
7
7
Bi-directional
Uni-directional
Bi-directional
8.5 USB Application
EM78M611E is designed specially for USB device application and has many powerful
functions that support the firmware to free itself from complex situation in various
aspects of USB application.
8.5.1 USB Device Controller
The EM78M611E built-in USB Device Controller (UDC) can interpret the USB Standard
Command and respond automatically without involving firmware. The embedded
Series Interface Engine (SIE) handles the serialization and de-serialization of actual
USB transmission. Thus, a developer can concentrate his efforts more in perfecting
the device actual functions and spend less energy in dealing with USB transaction.
The UDC handles and decodes most Standard USB commands defined in the USB
Specification Rev1.1. If the UDC receives an unsupported command, it will set a flag to
notify the MCU of the receipt of such command. The Standard Commands that the
EM78M611E supports includes; Clear Feature, Get Configuration, Get Interface,
Get Status, Set Address, Set Configuration, Set Feature, and Set Interface.
Each time the UDC receives a USB command, it writes the command into the EP0’s
FIFO. Only when it receives unsupported command will the UDC notify the MCU
through interrupt.
Hence, the EM78M611E is very flexible under USB application since the developer can
freely choose the method of decoding the USB command as dictated by different situation.
22 •
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
EM78M611E
Universal Serial Bus Series Microcontroller
8.5.2 Device Address and Endpoints
EM78M611E supports one device address and three endpoints, EP0 for control
endpoint, EP1 and EP2 for interrupt endpoint. Sending data to USB host in
EM78M611E is very easy. Just write data into EP’s FIFO, then set flag, and the UDC
will handle the rest. It will then confirm that the USB host has received the correct data
from EM78M611E.
8.6 Reset
The EM78M611E provides three types of reset: (1) Power-on Reset, (2) Watchdog
Reset, and (3) USB Reset.
8.6.1 Power-on Reset
Power-on Reset occurs when the device is attached to power and a reset signal is
initiated. The signal will last until the MCU becomes stable. After a Power-on Reset,
the MCU enters into the following predetermined states (see below), and then, it is
ready to execute the program.
a. The program counter is cleared.
b. The TCC timer and Watchdog timer are cleared.
c. Special registers and Special Control registers are all set to their initial values.
8.6.2 Watchdog Reset
When the Watchdog timer overflows, it causes the Watchdog to reset. After it resets,
the program is executed from the beginning and some registers will be reset. The UDC
however, remains unaffected.
8.6.3 USB Reset
When the UDC detects a USB Reset signal on the USB Bus, an MCU interrupt occurs,
after which it proceeds to perform the specified process that follows. After a USB
device is attached to the USB port, it cannot respond to any bus transactions until it
receives a USB Reset signal from the bus.
8.7 Saving Power Mode
The EM78M611E provides two options of power-saving modes for energy conservation,
i.e., Power Down mode and Dual clock mode.
8.7.1 Power Down Mode
The EM78M611E enters into Power Down mode by clearing the RUN register
(IOCE[4]). During this mode, the oscillator is turned off and the MCU goes to sleep. It
will wake up when signal from USB host is resumed, or when a Watchdog reset occurs
or when an input port state changes.
If the MCU wakes up when I/O port status changes, the direction of the I/O port should
be set at input direction, and then read the state of port. For example:
Product Specification (V1.11) 04.20.2007
(This specification is subject to change without further notice)
• 23
EM78M611E
Universal Serial Bus Series Microcontroller
:
// Set the Port 6 to input port
MOV
A, @0xFF
IOW
PORT6
// Read the state of Port 6
MOV
PORT6, PORT6
// Clear the RUN bit
IOR
0xE
AND
A, 0B11101111
IOW
0xE
:
:
8.7.2 Dual Clock Mode
The EM78M611E has one internal oscillator for power saving application. Clearing the
Bit IOCE [7] will enable the low frequency oscillator. At the same time, the external
oscillator will be turned off. Then the MCU will run under very low frequency to
conserve power. Four types of frequency are available for selection in setting bits
IOCA [6, 7].
The USB Host Resume Interrupt can only be used in this mode. If this interrupt is
enabled, the MCU will be interrupted when the USB Host Resume signal is detected on
USB Bus.
8.8 Interrupt
The EM78M611E has one interrupt vector in 0x0001. When an interrupt occurs during
an MCU program run, it will jump to the interrupt vector (0x0001) and execute the
instructions sequentially from the interrupt vector. RF is the interrupt status register,
which records the interrupt status in the relative flags/bits.
The interrupt condition could be one of the following:
TCC Overflow: When the Timer Clock / Counter Register (R1) overflows, the status flag
RF[0] will be set to 1. Its interrupt vector is 0X0001.
Port 7 State Change: When the input signals in Port 7 changes, the status flag RF[4]
will be set to 1. Its interrupt vector is 0X0001.
SE1 Pattern Detection Interrupt Conditions: If the Pattern Detection Application
function is enabled, there will be four conditions with which interrupt is generated,
and the status flag RF[5] is set to 1 (interrupt vector is 0X0001).
a) Signal from P.92 changes to low and the Pattern Counter value is bigger than
R11 register value.
24 •
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
EM78M611E
Universal Serial Bus Series Microcontroller
b) Signal from P.92 changes to high, and Pattern Counter value bigger than R10
register value.
c) P.92 remains high, and the Pattern Counter value is equal to 0XFF.
d) P.92 remains low, and the Pattern Counter value is equal to 0XFF.
SE2 Pattern Counter Interrupt Conditions: If the Pattern Detection Application function
is enabled, there will be three conditions with which interrupt is generated and the
status flag RF[6] is set to 1(interrupt vector is 0X0001).
a) Signal from P.93 changes to low and the Pattern Counter value is bigger than
R13 register value.
b) Signal from P.93 changes to high and the Pattern Counter value is bigger than
R12 register value.
c) P.93 remains high, and the Pattern Counter value is equal to 0XFF.
d) P.93 remains low, and the Pattern Counter value is equal to 0XFF.
EP0 interrupt: When the UDC successfully accepts a setup transaction from host to
EndPoint0, the status flag RF[1] is set to 1. Its interrupt vector is 0X0001.
USB suspend: When UDC detects a USB Suspend signal on the USB bus, the status
flag RF[2] is set to 1. Its interrupt vector is 0X0001.
USB Reset: When the UDC detects a USB Reset signal on the USB bus, the status flag
R[3] is set to 1. Its interrupt vector is 0X0001.
USB Host Resume: When the UDC detects that the USB bus is no longer in Suspend
condition and without Device Resume signal, the status flag R[7] is set to 1. Its
interrupt vector is 0X0001.
IOCF is an interrupt mask register which can be set bit by bit. While their respective bit
is written to 0, the hardware interrupt will inhibit, that is, the EM78M611E will not jump
to the interrupt vector to execute instructions. But the interrupt status flags still records
the conditions no matter whether the interrupt is masked or not. The interrupt status
flags must be cleared by firmware before leaving the interrupt service routine and
enabling other interrupt.
The global interrupt is enabled by the ENI (RETI) instruction and is disabled by the DISI
instruction.
8.9 Pattern Detect Application (PDA)
8.9.1 Function Description
This function is designed for the serial signal transmission, e.g., the transmission
between a wireless device and its receiver box. The EM78M611 has two sets of built-in
Pattern Detect Application block that ensures the EM78M611 is equipped with a
compound device, such as the receiver box controller for a wireless keyboard paired
with a wireless mouse.
Product Specification (V1.11) 04.20.2007
(This specification is subject to change without further notice)
• 25
EM78M611E
Universal Serial Bus Series Microcontroller
Pattern Detect Application (PDA) can calculate the length of one pattern and interrupt
the MCU while the serial signal is transiting from high to low (or vise-versa). Then the
MCU reads the length value from a specified register.
8.9.2 Control Register
The PDA includes an enable control bit, one control register and 4-length counter
registers in 0x10 ~0x13.
IOCA [2] PDA Enable Control Bit
When this bit is set, the PDA function starts and the P92 and P93 become input pin
automatically to sample the serial signal.
0 : disable PDA function
1 : enable PDA function
RB (PDA Control Register) Default Value: (0B_0000_0000)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SE2.F
SE1.F
SR.2
SR.1
SR.0
DB2
DB1
DB0
This register is used to define two parameters of PDA function; signal sampling rate
and debounce length. When a pattern ends, the value in the counter is loaded into its
respective register and the RB[6] or RB[7] is set to indicate which type of pattern (high
or low) is at its end or which type of pattern counter is on overflow.
0: low pattern
1: high pattern
R10 (P.92 Low Pattern Counter)
This register records the length of P.92 in low status.
R11 (P.92 High Pattern Counter)
This register records the length of P.92 in high status.
R12 (P.93 Low Pattern Counter)
This register record the length of P.93 in low status.
R13 (P.93 High Pattern Counter)
This register records the length of P.93 in high status.
R10~R13 function as general registers if this function is not enabled. Once the enabled
bit is set, these four registers will be loaded with the value of the pattern counter.
8.9.3 Sampling Rate and Debounce Length
Although the two-pattern detect pins are separate, and each pin has its own pattern
counter, both pins use the same Sampling Rate and Debounce Length parameters.
The PDA samples the serial signal every fixed interval. The pattern counter will be
incremented by one at sampling time if the signal remains unchanged. If the signal is at
26 •
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
EM78M611E
Universal Serial Bus Series Microcontroller
high state, then the “high pattern counter“ will increase; otherwise the “low pattern
counter” increases. As long as the signal state changes, the PDA will debounce signal
and load the value of pattern counter into the respectively register for the firmware to
read. For example, if the signal in P.92 is in “low” state, the low counter of P.92 will
count continuously until the state of the input signal in P.92 changes. When a state
change occurs (in this case, the signal changes from “low” to “high” state), the PDA will
take a time break (which is equal to the result of sampling interval multiplied by the
debounce length), to avoid possible noise. After the debounce length time, if the signal
remains in high state, the high pattern counter will start to count and load the low
pattern counter’s value into R10. At the same time, RB[6] is cleared to indicate that low
pattern is over.
The correlation between the control register value and debounce time are as follows:
DB.2
DB.1
DB.0
Debounce Time
0
0
0
0
0
0
1
Sampling clock
0
1
0
Sampling clock × 2
0
1
1
Sampling clock × 3
1
0
0
Sampling clock × 4
1
0
1
Sampling clock × 5
1
1
0
Sampling clock × 6
1
1
1
Sampling clock × 7
On the other hand, when the signal of P92 always remains “low”, the low pattern
counter of P92 will eventually overflow. Once the counter overflows, the content of the
counter will also be loaded into R10, that is, the register is written to 0xFF, and the
counter is reset to count from zero again.
If the hardware interrupt of PDA function is enabled, (IOCF[5] is equal to “1”), then the
program will go to 0x0001 to execute interrupt routine while the content of a pattern
counter is loaded into the register.
The correlation between the value of control register and actual sampling rate are as
shown below:
SR.2 SR.1 SR.0
Sampling Rate
Sampling Rate
(External oscillator frequency = 6MHz) (External oscillator frequency = 12MHz)
0
0
0
0
0
1
N.A.
N.A.
0
1
0
1500 (Count / mSec)
N.A.
0
1
1
750 (Count / mSec)
1500 (Count/ mSec)
1
0
0
375 (Count / mSec)
750 (Count / mSec)
1
0
1
188 (Count / mSec)
375 (Count / mSec)
1
1
0
94 (Count / mSec)
188 (Count / mSec)
1
1
1
47 (Count / mSec)
94 (Count / mSec)
Product Specification (V1.11) 04.20.2007
N.A.
(This specification is subject to change without further notice)
N.A.
• 27
EM78M611E
Universal Serial Bus Series Microcontroller
After the PDA function is enabled (by setting IOCA[2] to 1), user can write a default
value to the High Pattern counter register and Low Pattern counter register. Then set
the corresponding interrupt enable bit (IOCF[5]). When the counting value of one “H”
pattern is bigger than the default value of R11, the Pattern Detecting interrupt will be
generated. Similarly, if the counting value of one “L” pattern is bigger than the default
value of R10, Low Pattern Detecting interrupt will occur. Thus, the EM78M611 is
notified and aware that one effective pattern is received from P.92.
If user does not need these two interrupts, they can be masked. The new value of
counting a pattern will still be loaded to the R10 and R11. The firmware must poll and
determine whether the value of these two registers has changed or not.
8.10 Pulse Width Modulation (PWM)
8.10.1 Function Description
In PWM mode, both PWM1 (P.92) and PWM2 (P.93) produce plus programmable
signal of up to 8 bits resolution.
The PWM Period is defined as 0xFF × Timer Counter Clock. The Timer Counter clock
source is controlled by an extra control register, ERE. For example; if the Clock source
is 1MHz, then the Period will be 255 µseconds.
Period = 255 × (1/Timer Counter Clock)
Period (0xFF * Clock)
Duty Cycle
Fig. 8-2 The PWM Output Timing
8.10.2 Duty Cycle
The PWM duty cycle is defined by writing to the R10/R11 Register for PWM1/PWM2.
Duty Cycle = ( R10 / 255 ) × 100% for PWM1
( R11 / 255 ) × 100% for PWM2
8.10.3 Control Register
R10 (PWM1 Duty Cycle Register)
A specified value keeps the output of PWM1 to remain at high for a Period.
R11 (PWM2 Duty Cycle Register)
A specified value keeps the output of PWM2 to remain at high for a Period.
ERE(PWM Control Register) Default Value: (0B_0000_0001)
28 •
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PEN2
PEN1
-
-
-
PS2
PS1
PS0
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
EM78M611E
Universal Serial Bus Series Microcontroller
ERE [0~2] PWM Clock Prescaler
PS2
PS1
PS0
Clock (Hz)
Period/255 (s)
0
0
0
Fosc/3
0.5µ
0
0
1
Fosc/6
1µ
0
1
0
Fosc/12
2µ
0
1
1
Fosc/24
4µ
1
0
0
Fosc/48
8µ
1
0
1
Fosc/96
16µ
1
1
0
Fosc/192
32µ
1
1
1
Fosc/384
64µ
ERE [6, 7] PWM1/PWM2 Enable Bit
0 : Disable
1 : Enable
8.11 Analog-To-Digital Converter (ADC)
8.11.1 Function Description
The Analog to Digital converter consists of a 5-bit analog multiplexer, one Control
Register (ERA), and two data registers (RBS & RCS) for 10-bit resolution.
The ADC module utilizes successive approximation to convert the unknown analog
signal to a digital value. The result is fed to the ADDATA. Input channels are selected
by the analog input multiplexer via the ADCS/RAS bits AD0~AD4.
10-bit resolution: 0x00-00~0xC0-FF (0b11000000-11111111)
Start (0x00-00): 0 Vref~(1/1024) × Vref
Full (0xC0-FF): (1023/1024) × Vref~Vref
Conversion Time: 12 clock time of internal clock source
8.11.2 Control Register
ERA (AD Channel Select Register) Default Value: (0B_0001_1111)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC
0
0
AD4
AD3
AD2
AD1
AD0
Product Specification (V1.11) 04.20.2007
(This specification is subject to change without further notice)
• 29
EM78M611E
Universal Serial Bus Series Microcontroller
ERA [0~4]: AD Channel Selector
AD4
AD3
AD2
AD1
AD0
Channel
I/O Port
0
0
0
0
0
0
P50
0
0
0
0
1
1
P51
0
0
0
1
0
2
P52
0
0
0
1
1
3
P53
0
0
1
0
0
4
P54
0
0
1
0
1
5
P55
0
0
1
1
0
6
P56
0
0
1
1
1
7
P57
0
1
0
0
0
8
P80
0
1
0
0
1
9
P81
0
1
0
1
0
10
P82
0
1
0
1
1
11
P83
0
1
1
0
0
12
P84
0
1
1
0
1
13
P85
0
1
1
1
0
14
P86
0
1
1
1
1
15
P87
1
0
0
0
0
16
P60
1
0
0
0
1
17
P61
1
0
0
1
0
18
P62
1
0
0
1
1
19
P63
1
0
1
0
0
20
P64
1
0
1
0
1
21
P65
1
0
1
1
0
22
P66
1
0
1
1
1
23
P67
ERA [7] AD Converter ready flag
0
1: Start AD Conversion (set by firmware).
1
0: When AD conversion is finished and has moved digital data into the AD
Data Register, this bit will be set by hardware.
NOTE
Hardware can enable this function only at AD Channel Select of the functional I/O port.
After a power-on reset, the initial value of this register is 0b0001_1111.
ERB (AD LSB Data Register) Default Value: (0B_0000_0000)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 1
Bit 0
0
0
0
0
0
0
8 bits AD LSB Digital Data
30 •
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
EM78M611E
Universal Serial Bus Series Microcontroller
ERC (AD MSB Data Register) Default Value: (0B_0000_0000)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
2 bits AD MSB Digital Data.
ERD (AD Control Register) Default Value: (0B_0000_0000)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
-
ADPS1
ADPS0
ERD [0 1]: The clock source of AD converting time.
00: 256kHz
01: 128kHz
10: 64kHz
11: 32kHz
8.12 EEPROM
Four bytes of EEPROM are located in the R2C~R2F of Bank 3. The stored data of
EEPROM are not erased when the power is off and can be read and re-written by
firmware. In some special case of application, for example, cordless keyboard
controller, it can store important data, such as the cordless keyboard’s device identical
number.
A control register, ERA controls the EEPROM, that is, to read, write, or to erase the
data from EEPROM. Writing a command into this register will execute an action to the
EEPROM. The command value is defined in the following tale. Note that there is an
execution time laps for each command. Before writing the next command into the
control register, allow enough time for the EEPROM to finish the previous command.
Command Value
Action
Execution Time
0B_0000_0000
Read
1 ms
0B_0000_0001
Write
9 ms
0B_0000_0010
Erase
128 ms
0B_0000_0011
Disable
N.A.
Product Specification (V1.11) 04.20.2007
(This specification is subject to change without further notice)
• 31
EM78M611E
Universal Serial Bus Series Microcontroller
9
Absolute Maximum Ratings
Symbol
Min
Temperature under bias
Max
Unit
0
70
ºC
Storage temperature
-65
150
ºC
Input voltage
-0.5
6.0
V
Output voltage
-0.5
6.0
V
Min
Type Max
10 DC Electrical Characteristic
T = 25ºC, VDD=5V, VSS=0V
Symbol
Parameter
Condition
Unit
3.3V Regulator
VRag
Output voltage of 3.3V Regulator
VResetL
Low Power Reset detecting low
Voltage
VResetH
Low Power Reset detecting high
Voltage
Ireg
3.3V Regulator driving capacity
VDD = 5V
3.0
3.3
3.6
V
−
−
−
2.2
V
−
3.0
−
−
V
−
−
100
mA
−
−
1
µA
V3.3 = 3.3V
MCU Operation
IIL
Input Leakage Current for input pins VIN=VDD, VSS
VIHX
Clock Input High Voltage
OSCI
2.5
−
−
V
VILX
Clock Input Low Voltage
OSCI
−
−
1.0
V
ICC1
VDD operating supply current –
Normal frequency operation mode
Freq. = 6MHz
−
−
10
mA
ICC2
VDD operating supply current –
Normal frequency operation mode
Freq. = 12MHz
−
−
20
mA
Freq. = 256kHz
−
−
250
µA
−
−
100
µA
ICC3
ISB1
VDD operating supply current –
Dual clock mode
Operating supply current 1 – Power
WDT disabled
down mode
K
GPIO Pins
32 •
VIH
Input High Voltage
Port 5 & Port 6 &
Port 7 & Port 8 &
Port 9
2.0
−
−
V
VIL
Input Low Voltage
Port 5 & Port 6 &
Port 7 & Port8 &
Port 9
−
−
0.8
V
IOH1
Output High Voltage
(P70~P73, P76 and P77)
ISink = 10.0mA
VDD = 5V
−
10
−
mA
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
EM78M611E
Universal Serial Bus Series Microcontroller
Symbol
Parameter
Condition
Min
Type Max
Unit
IOH2
Output High Voltage
(P74, P75)
ISink = 5.0mA
VDD = 5V
−
5
−
mA
IOH3
Output High Voltage
(Port 5 & Port 6 & Port 8 and
P90~P93, P95, P96)
ISink = 10.0mA
VREG = 3.3V
−
10
−
mA
IOL1
Output Low Voltage
(P76 and P77 normal mode)
ISink = 10.0mA
VDD = 5V
−
10
−
mA
IOL2
Output Low Voltage
(P74, P75)
ISink = 10.0mA
VDD = 5V
−
5
−
mA
IOL3
Output Low Voltage
ISink = 10.0mA
(P70~P73, P76 and P77 sink LED) VDD = 5V
−
10
−
mA
IOL4
Output Low Voltage
(P90 ~ P93, P95, P96 normal
mode)
ISink = 10.0mA
VREG = 3.3V
−
10
−
mA
IOL5
Output Low Voltage
(P90 ~ P93, P95, P96 sink LED)
ISink = 10.0mA
VREG = 3.3V
−
10
−
mA
Input pin with
pull-high
resistor ,
VREG = 3.3V
−
25
−
KΩ
Input pin with
pull-high
resistor ,
VDD = 5V
−
2.2
−
KΩ
RPH1
RPH2
Pull-high resistor
(Port 5, 6, 8, 9)
Pull-high resistor(P.74 ~ P.77)
(P74/P75) PS2 mode
USB Interface
VOH
Static Output High
2.8
−
3.6
V
VOL
Static Output Low
−
−
0.3
V
VDI
Differential Input Sensitivity
0.2
−
−
V
VCM
Differential Input Command Mode
Range
0.8
−
2.5
V
VSE
Single Ended Receiver Threshold
0.8
−
2.0
V
CIN
Transceiver Capacitance
−
−
20
pF
VRG
Output Voltage of Internal Regulator
3.0
−
3.6
V
RPH3
Pull-high resistor (P.75 / D-)
−
1.5
−
KΩ
Product Specification (V1.11) 04.20.2007
(This specification is subject to change without further notice)
USB operation
Mode
• 33
EM78M611E
Universal Serial Bus Series Microcontroller
11 Application Circuit
NOTE
A. BC1 , BC2 : load Capacitor
B. C1 (bypass capacitor) : that placed adjacent to VDD pin , to minimize noise.
C. C2 , C3 (power capacitor) : that placed adjacent to the Power source , will improve
transient response and ripple rejection.
34 •
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
EM78M611E
Universal Serial Bus Series Microcontroller
APPENDIX
A Special Register Map
Operation Registers
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit1
Bit 0
Default Value
0x00
R0
Indirect Addressing Register
0B_0000_0000
0x01
R1 (TCC)
Timer/Clock Counter
0B_0000_0000
0x02
R2 (PC)
Program Counter
0B_0000_0000
0x03
R3 (STATUS)
PS2
PS1
PS0
0x04
R4 (RSR)
BK1
BK0
Select the register( Address: 00~3F) in indirect addressing mode
0x05
R5 (Port 5)
P57
P56
P55
P54
P53
P52
P51
P50
0B_0000_0000
0x06
R 6 (Port 6)
P67
P66
P65
P64
P63
P62
P61
P60
0B_0000_0000
0x07
R 7 (Port 7)
P77
P76
P75/D-
P74/D+
/DATA
/CLK
P72
P71
P70
0B_0000_u000
0x08
R8 (Port 8)
P87
P86
P85
P84
P83
P82
P81
P80
0B_0000_0000
0x09
R9 (Port 9)
-
P96
P95
-
P93
P92
P91
P90
0B_u00u_0000
0x0A
RA
-
-
-
-
EE_OK
EE_C1
EE_C0
0B_1111_1111
0x0B
RB
SE2.F
SE1.F
DB2
DB1
DB0
0B_1111_1111
0x0C
RC
EP0_W
EP0_R
UDC
UDC
_SUSPEND
_Writing
STALL
0B_0000_0000
0x0D
RD
USB Application FIFO Address Register
0B_0000_0000
0x0E
RE
USB Application FIFO Data Register
0B_0000_0000
T
SR.2
EP1_
R
P
-
-
SR.1
SR.0
EP2_R
EP2_W
Z
DC
C
0B_0001_1xxx
USB
0x0F
RF
Host
Resume
_IF
SE1_IF
Product Specification (V1.11) 04.20.2007
SE1_IF
Port 7 state
change_1F
(This specification is subject to change without further notice)
USB
Reset_IF
USB
Suspend_IF
EP0_IF
TCC_IF
0B_0000_0000
• 35
EM78M611E
Universal Serial Bus Series Microcontroller
Control Registers
Address
Name
CONT
Bit 7
S7
Bit 6
INT
Bit 5
TSR2
Bit 4
Bit 3
SR1
Bit 2
TSR0
PSR2
Bit 1
Bit 0
Default Value
PSR1
PSR0
0B_0011_1111
0x05
IOC5
Port 5 Direction Control Register
0B_1111_1111
0x06
IOC6
Port 6 Direction Control Register
0B_1111_1111
0x07
IOC7
Port 7 Direction Control Register
0B_1111_1111
0x08
IOC8
Port 8 Direction Control Register
0B_1111_1111
0x09
IOC9
Port 9 Direction Control Register
0B_1111_1111
0x0A
IOCA
Dual_
Frq.1
0x0B
IOCB
-
/P96
/P95
0x0C
IOCC
-
P96
P95
0x0D
IOCD
-
/P96
/P95
0x0E
IOCE
/Dual
clock
/WUE
WTE
0x0F
IOCF
SE2_IE
SE1_IE
Dual_
Frq.0
-
USB Host
Resume_
IE
Remote_
Wake Up
ExReg_
Sel
PDA
PS/2
USB
0B_11x0_0000
/P94
/P93
/P92
/P91
/P90
0B_x111_1111
-
P93
P92
P91
P90
0B_x00x_0000
-
/P93
/P92
/P91
/P90
0B_x00x_0000
RUN
Device_R
esume
/PU8
/PU6
/PU5
0B_1101_0111
Port 7 state
USB
change_1F
Reset_IE
Suspend_
IE
EP0_IE
TCC_IE
0B_0000_0000
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default Value
USB
Extra Register (IOCA[3] = 1)
Address
Name
0x0A
ERA
0x0B
ERB
Digital Data (Bit 1~Bit 0)
0B_0000_0000
0x0C
ERC
Digital Data (Bit 10~Bit 2)
0B_0000_0000
0x0D
ERD
-
0x0E
ERE
PEN2
36 •
Bit 7
ADC
Bit 6
Bit 5
-
-
PEN1
AD4
AD3
AD2
-
-
-
-
-
-
AD1
PS2
AD0
0B_0001_1111
ADSP1
ADSP0
0B_0000_0000
PS1
PS0
0B_0000_0001
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
EM78M611E
Universal Serial Bus Series Microcontroller
B Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. All instructions are executed within one single instruction cycle
(consisting of two oscillator periods), unless the program counter is changed by(a) Executing the instruction "MOV R2, A", "ADD R2,A", "TBL", or any other instructions
that write to R2 (e.g. "SUB R2,A", "BS R2,6", "CLR R2", ⋅⋅⋅⋅).
(b) Execute CALL, RET, RETI, RETL, JMP, Conditional skip (JBS, JBC, JZ, JZA, DJZ,
DJZA) which were tested to be true.
Under these cases, the execution takes two instruction cycles.
In addition, the instruction set has the following features:
(1). Every bit of any register can be set, cleared, or tested directly.
(2). The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
Legend:
R = Register designator that specifies which one of the 64 registers (including operation and general
purpose registers) is to be utilized by the instruction.
Bits 6 and 7 in R4 determine the selected register bank.
b = Bit field designator that selects the value for the bit located in the register R and which affects the
operation.
k = 8 or 10-bit constant or literal value
Binary Instruction
Hex
Mnemonic
Operation
Status Affected
0 0000 0000 0000
0000
NOP
No Operation
0 0000 0000 0001
0001
DAA
Decimal Adjust A
0 0000 0000 0010
0002
CONTW
A → CONT
None
0 0000 0000 0011
0003
SLEP
0 → WDT, Stop oscillator
T, P
0 0000 0000 0100
0004
WDTC
0 → WDT
T, P
0 0000 0000 rrrr
000r
IOW R
A → IOCR
None
0 0000 0001 0000
0010
ENI
Enable Interrupt
None
0 0000 0001 0001
0011
DISI
Disable Interrupt
None
0 0000 0001 0010
0012
RET
[Top of Stack] → PC
None
[Top of Stack] → PC,
Enable Interrupt
None
None
C
1
0 0000 0001 0011
0013
RETI
0 0000 0001 0100
0014
CONTR
CONT → A
None
0 0000 0001 rrrr
001r
IOR R
IOCR → A
None
0 0000 0010 0000
0020
TBL
0 0000 01rr rrrr
00rr
MOV R,A
A→R
None
0 0000 1000 0000
0080
CLRA
0→A
Z
0 0000 11rr rrrr
00rr
CLR R
0→R
Z
0 0001 00rr rrrr
01rr
SUB A,R
R-A → A
Z, C, DC
0 0001 01rr rrrr
01rr
SUB R,A
R-A → R
Z, C, DC
Product Specification (V1.11) 04.20.2007
(This specification is subject to change without further notice)
R2+A → R2,
Bits 8~9 of R2 unchanged
1
Z, C, DC
• 37
EM78M611E
Universal Serial Bus Series Microcontroller
Binary Instruction
Hex
Mnemonic
Operation
Status Affected
0 0001 10rr rrrr
01rr
DECA R
R-1 → A
Z
0 0001 11rr rrrr
01rr
DEC R
R-1 → R
Z
0 0010 00rr rrrr
02rr
OR A,R
A ∨ VR → A
Z
0 0010 01rr rrrr
02rr
OR R,A
A ∨ VR → R
Z
0 0010 10rr rrrr
02rr
AND A,R
A&R→A
Z
0 0010 11rr rrrr
02rr
AND R,A
A&R→R
Z
0 0011 00rr rrrr
03rr
XOR A,R
A⊕R→A
Z
0 0011 01rr rrrr
03rr
XOR R,A
A⊕R→R
Z
0 0011 10rr rrrr
03rr
ADD A,R
A+R→A
Z, C, DC
0 0011 11rr rrrr
03rr
ADD R,A
A+R→R
Z, C, DC
0 0100 00rr rrrr
04rr
MOV A,R
R→A
Z
0 0100 01rr rrrr
04rr
MOV R,R
R→R
Z
0 0100 10rr rrrr
04rr
COMA R
/R → A
Z
0 0100 11rr rrrr
04rr
COM R
/R → R
Z
0 0101 00rr rrrr
05rr
INCA R
R+1 → A
Z
0 0101 01rr rrrr
05rr
INC R
R+1 → R
Z
0 0101 10rr rrrr
05rr
DJZA R
R-1 → A, skip if zero
None
0 0101 11rr rrrr
05rr
DJZ R
R-1 → R, skip if zero
None
C
0 0110 00rr rrrr
06rr
RRCA R
R(n) → A(n-1),
R(0) → C, C → A(7)
0 0110 01rr rrrr
06rr
RRC R
R(n) → R(n-1),
R(0) → C, C → R(7)
C
0 0110 10rr rrrr
06rr
RLCA R
R(n) → A(n+1),
R(7) → C, C → A(0)
C
0 0110 11rr rrrr
06rr
RLC R
R(n) → R(n+1),
R(7) → C, C → R(0)
C
0 0111 00rr rrrr
07rr
SWAPA R
0 0111 01rr rrrr
07rr
SWAP R
0 0111 10rr rrrr
07rr
JZA R
R(0-3) → A(4-7),
R(4-7) → A(0-3)
None
R(0-3) ↔ R(4-7)
None
R+1 → A, skip if zero
None
0 0111 11rr rrrr
07rr
JZ R
R+1 → R, skip if zero
None
0 100b bbrr rrrr
0xxx
BC R,b
0 → R(b)
None
0 101b bbrr rrrr
0xxx
BS R,b
1 → R(b)
None
0 110b bbrr rrrr
0xxx
JBC R,b
if R(b)=0, skip
None
0 111b bbrr rrrr
0xxx
JBS R,b
if R(b)=1, skip
None
1 00kk kkkk kkkk
1kkk
CALL k
PC+1 → [SP],
(Page, k) → PC
None
(Page, k) → PC
None
k→A
None
2
1 01kk kkkk kkkk
1kkk
JMP k
1 1000 kkkk kkkk
18kk
MOV A,k
1 1001 kkkk kkkk
19kk
OR A,k
1 1010 kkkk kkkk
1Akk
1 1011 kkkk kkkk
1Bkk
1 1100 kkkk kkkk
1Ckk
RETL k
k → A, [Top of Stack] → PC
1 1101 kkkk kkkk
1Dkk
SUB A,k
k-A → A
Z, C, DC
1 1111 kkkk kkkk
1Fkk
ADD A,k
k+A → A
Z, C, DC
A∨k→A
Z
AND A,k
A&k→A
Z
XOR A,k
A⊕k→A
Z
None
1
Note: This instruction is applicable to IOCx only.
2
38 •
This instruction is not recommended for RE, RF operation.
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
EM78M611E
Universal Serial Bus Series Microcontroller
C Code Option Register
EM78M611E has two Code option registers, which are not part of the normal program
memory. The option bits cannot be accessed during normal program execution.
Address 000:
Bit
12
11
10
9
8
7
6
5
4
3
2
1
0
Mnemonic ID_8 ID_7 ID_6 ID_5 ID_4 ID_3 ID_2 ID_1 ID_0 OST_1 OST_0 Frequency /Protect
Address 001:
Bit
5
4
3
2
1
0
Mnemonic
/AD_Hold
/R.S.
−
−
Package_1
Package_0
Bit
12
11
Mnemonic QTP_Code1 QTP_Code0
10
9
8
7
6
EP2_
EP2_
EP2_
EP2_
EP2_
Maxsize_2
Maxsize_1
Maxsize_0
DIR
Enable
Address 000:
Bit 1 (Frequency) : Frequency Selection
0 : MCU run on 12 MHz
1 : MCU run on 6 MHz
Bits 3~2 (OST_1 ~ OST_0) : Oscillator start-up time.
00 : 500µs
01 : 2ms
10 : 8ms
11 : 16ms
Bits 4~12 : User ID
Address 001:
Bits 1~0 (Package_1 ~ Package_0) : Package type selection
00 : Not defined
01 : 40 pins
10 : Not defined
11 : 44 pins
Bits 3~2 : Reserved bits
Product Specification (V1.11) 04.20.2007
(This specification is subject to change without further notice)
• 39
EM78M611E
Universal Serial Bus Series Microcontroller
Bit 4 (/R.S.) : D- Pull-up Resistance
0 : Connect Resistor Switch
1 : Disconnect Resistor Switch
Bit 5 (/AD_Hold) : Halts the MCU during AD conversion
0 : Halts the MCU during AD conversion
1 : MCU keeps running during AD conversion
Bit 6 (EP2_Enable) : Endpoint 2 Enable
0 : Disable
1 : Enable
Bit 7 (EP2_Dir) : Endpoint 2 Direction
0 : OUT
1 : IN
Bits 10~8 (EP2_Maxsize_2~0) : Endpoint 2 maximum size
000 : 1 Byte
001 : 2 Bytes
010 : 3 Bytes
011 : 4 Bytes
100 : 5 Byte
101 : 6 Bytes
110 : 7 Bytes
111 : 8 Bytes
Bits 12~11: Values are fixed
40 •
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)